D3.1 green tag design aspects and IC technology choice 2.0 UA - … · 2017-04-21 · Project SELECT - Smart Efficient Location, idEntification and Cooperation Techniques Proje ct

Project SELECT - Smart Efficient Location, idEntification and Cooperation Techniques Project - No 257544

Work Package WP3. Tag design WP – No WP3

Document Deliverable D3.1 Save Date 15/03/2011

D3.1_green_tag_design_aspects_and_IC_technology_choic

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Dissemination Level: PU Page 1/99

THEME ICT

ICT 2009.3.9 Microsystems and Smart Miniaturised Systems

Programme Title Collaborative project / Small or medium-scale focused research projects

Project Title

Smart Efficient Location, idEntification and Cooperation Techniques Acronym

SELECT Project No

257544

DELIVERABLE D3.1

“Green” tag design aspects and IC technology choice

Work Package 3 Leading Partner: CEIT

Document Editor: Unai Alvarado

Dissemination Level: PU

Delivery date: 28/02/2011

Version 2.0





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Contributors

Partner Contributing authors

DATALOGIC

Fraunhofer

LETI Dominique Morche

CNIT

CEIT Unai Alvarado, Aitor Juanicorena

ARMINES

NOV Dag T. Wisland

ORIA

Versioning and contribution history

Version Description Contributing authors Date

0.0 First draft Unai Alvarado 21/01/2011

0.1 NOVELDA’s contribution added Dag T. Wisland 24/01/2011

0.2 New edits in tag architectures, and use of batteries after the second project meeting discussion

Unai Alvarado 01/02/2011

0.3 New contributions of LETI to the power management section added

Dominique Morche 11/02/2011

0.4 Document with new template_V4 Unai Alvarado 14/02/2011

0.5 Update on the technology selection Dag T. Wisland 14/02/2011

0.6 References added Dominique Morche 15/02/2011

1.0 Document ready for review Unai Alvarado 16/02/2011

1.1 Internal Revision Davide Dardari 03/03/2011

1.2 Internal Revision Giancarlo Micheletti 04/03/2011

2.0 Document reviewd. Delivery ready Unai Alvarado 08/03/2011





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LIST OF ACRONYMS

Acronym Name

AC Alternating Current

AsGa Gallium Arsenide

ASIC Application Specific Integrated Circuit

BiCMOS Bipolar CMOS

CAD Computer Aided Design

CMOS Complementary Metal Oxide Semiconductor

CW Continuous Wave

DC Direct Current

DIBL Drain Induced Barrier Lowering

DoW Description of Work

EEPROM Electrically Erasable Programmable Read Only Memory

ETSI European Telecommunications Standard Institute

FB Front to Back

FEP Fluorinated Ethylene Propylene

FPC Flexible Printed Circuit Board

GSM Global System for Mobile Communications

IC Integrated Circuit

LCP Liquid Cristal Polymer

MCM Multi Chip Module

MEMS Micro Electro Mechanical Systems

MPW Multi Project Wafer

MIM Metal Insulator Metal

MIMCAP Metal Insulator Metal Capacitor

MOMCAP Metal Oxide Metal Capacitor

MTCMOS Multiple Threshold CMOS

NDA Non Disclosure Agreement

NMOD N-Type Metal Oxide Semiconductor





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Acronym Name

ORB Organic Radical Battery

PCB Printed Circuit Board

PCE Power Conversion Efficiency

PEI Polyetherimide

PEN Polyethylene Napthalate

PET Polyester

PI Polyamide

PMOS P-Type Metal Oxide Semiconductor

PTFE Polytetrafluoroethylene

PV Photo Voltaic

RBB Reverse Body Bias

RF Radio Frequency

RFID Radio Frequency Identification

ROI Return On Investment

RoHS Restriction of Hazardous Substances

RPC Redistributed Chip Package

RTLS Real Time Location Systems

RX Receiver

SCCMOS Super Cut-OFF CMOS

SCM Supply chain management

SEM Scanning Electron Microscope

SiGe Silicon-Germanium

SNR Signal to Noise Ratio

SoC System on Chip

SoP System on Package

SRAM Static Random Access Memory

STC Standard Testing Condition

TEG Thermo Electric Generator

TX Transmitter

UHF Ultra High Frequency

UWB Technology Ultra-Wideband





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Acronym Name

VDD Main Voltage Supply

VDDH Higher VDD

VDDL Lower VDD

WARP Wireless Open Access Research Platform

WP Work Package

WSN Wireless Sensor Networks





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EXECUTIVE SUMMARY

D3.1: “Green” tag design aspects and IC technology choice presents the results obtained

within tasks T3.1: “Green” tag design aspects and T3.2: IC technology choice. It describes the

“green” aspects related to the tag from a low power consumption perspective, as well as the

IC technology selection for tag fabrication.

Section 1 deals with the “green” issues, in terms of low power design for the electronic

circuits. This way, different techniques and concepts that allow the minimization of the

energy requirements and therefore maximizing the lifespan of the tags are analyzed. Also in

this section different considerations about the use of batteries and materials for the tag

implementation in relation with the environmental impact are described.

As a critical aspect for the project work flow, as it implies all the technological WPs, the tag

candidate architectures are discussed in section 2. The conclusions agreed by the consortium

partners in the second Project meeting regarding to the pre-selected architecture are also

pointed in this section.

On the other hand, the technology selection process is described in section 3, and the

preliminary choice is also here mentioned, based on the feedback from the analysis of CMOS

90 nm processes from UMC and TSMC described through section 4.

Finally, conclusions and next steps are summarized in section 5.





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INTRODUCTION: THE SELECT PROJECT

The SELECT project focuses on studying innovative solutions enabling high-accuracy

detection, identification, and location of objects/persons equipped with small ultra-low

power tags using a network of intelligent self-configuring radio devices. Network

functionalities will be enhanced to include the detection and tracking of moving

objects/persons without tags eventually present in the same area.

To achieve this goal, several technologies such as radio frequency identification (RFID), ultra

wideband backscattering modulation, time reversal, relaying and energy scavenging, and

associated advanced algorithms, will be considered and partly or totally integrated in a

demonstrator. This will require the design of multi-frequency/multi-technology tags for

system-neutral identification along the use lifetime of a tag, based on advanced concepts in

low-consumption chip and antenna design.

Innovative techniques will be considered to improve the location accuracy, increase tag

energy efficiency and extend system coverage by a mixture of progress in the system

architecture, in the detection and tag activation techniques, and in the complexity-

performance trade off of chip design.

Special emphasis will be given to the analysis and design of “green” solutions by considering

low complexity and low power tags through the exploitation of semi-passive communication

(without energy supply for communication) as well smart cooperation strategies.

Finally, single system components and the overall system performance will be validated

through experimental characterization, hardware implementation, as well as simulation.

Identification/detection reliability, tracking accuracy, power consumption will be amongst

the major evaluation criteria.

A wireless network integrating detection, identification, and location would lead to relevant

improvements in the development of a wide range of advanced applications including

logistics (package tracking) and supply chain management (SCM).





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Table of contents

LIST OF ACRONYMS .......................................................................................................................................3

EXECUTIVE SUMMARY...................................................................................................................................6

INTRODUCTION: THE SELECT PROJECT ...........................................................................................................7

1. “GREEN” TAG DESIGN ASPECTS................................................................................................................11

1.1. Low power issues ............................................................................................................................. 12

1.1.1. IC technology for low power consumption .................................................................................12

1.1.2. Tag architecture considerations ................................................................................................15

1.1.3. Power management..................................................................................................................16

1.1.3.1. Multi-VDD................................................................................................................................16

1.1.3.2. Energy harvesting ....................................................................................................................18

1.1.3.3. Voltage regulation ...................................................................................................................25

1.1.3.4. Stand-By Operation and Power Gating ....................................................................................31

1.1.3.5. Energy Storage.........................................................................................................................33

1.2. Considerations about the use of batteries......................................................................................... 34

1.2.1. Batteries main classification......................................................................................................34

1.2.2. Primary batteries ......................................................................................................................35

1.2.2.1. Carbon Zinc batteries ...............................................................................................................35

1.2.2.2. Zinc Chloride batteries .............................................................................................................36

1.2.2.3. Alkaline batteries .....................................................................................................................36

1.2.2.4. Organic Radical Battery ...........................................................................................................36

1.2.2.5. Lithium batteries......................................................................................................................37

1.2.2.6. Summary of Primary batteries .................................................................................................37

1.2.3. Lithium batteries.......................................................................................................................37

1.2.3.1. Lithium/Manganese Dioxide ....................................................................................................38

1.2.3.2. Lithium/Sulfur Dioxide .............................................................................................................38

1.2.3.3. Lithium/Thionyl Chloride ..........................................................................................................38

1.2.3.4. Lithium/Polycarbon Monofluoride ...........................................................................................39

1.2.3.5. Advanced Lithium Carbon Fluoride Batteries............................................................................39

1.2.3.6. Summary of Lithium batteries ..................................................................................................40

1.2.4. Conclusions about the use of batteries ......................................................................................41

1.3. Materials for tag implementation..................................................................................................... 42

1.3.1. RPC (Rigid printed circuit)..........................................................................................................43

1.3.2. FPC (Flexible printed circuit) ......................................................................................................43

1.3.2.1. Paper Substrate .......................................................................................................................44

1.3.2.2. Liquid Crystal Polymer substrate ..............................................................................................45





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1.3.2.3. RFID substrate trends...............................................................................................................45

1.3.3. Circuit Fabrication Techniques...................................................................................................46

2. TAG PRELIMINARY ARCHITECTURES .........................................................................................................48

2.1. Tag functionality description ............................................................................................................ 48

2.2. UWB subsection considerations........................................................................................................ 49

2.2.1. Option 1: active UWB................................................................................................................49

2.2.2. Option 2: semi-passive UWB .....................................................................................................50

2.3. First tag architecture (A_1) ............................................................................................................... 51

2.4. Second tag architecture (A_2)........................................................................................................... 51

2.4.1. A_2 with UHF wake-up (A_2.1)..................................................................................................52

2.4.2. A_2 with RFID wake-up (A_2.2) .................................................................................................53

2.5. Third tag architecture (A_3).............................................................................................................. 54

2.6. Preliminary decision about tag architecture...................................................................................... 54

3. IC TECHNOLOGY CHOICE ..........................................................................................................................56

3.1. Criterions ......................................................................................................................................... 56

3.1.1. Technical criterions ...................................................................................................................56

3.1.2. Design flow criterions................................................................................................................57

3.1.3. Economical criterions ................................................................................................................57

3.1.4. Availability/Ease of access criterions .........................................................................................58

3.1.5. Existing knowledge/IP criterions ...............................................................................................58

3.1.6. Environmental / Ethical criterions .............................................................................................58

3.2. Decision steps .................................................................................................................................. 59

3.2.1. Semiconductor technology ........................................................................................................59

3.2.2. Technology node.......................................................................................................................59

3.2.3. Foundry / MPW provider...........................................................................................................60

3.2.4. Technology version ...................................................................................................................60

3.2.5. Specific process /options ...........................................................................................................60

3.3. MPW providers ................................................................................................................................ 60

3.3.1. CMP..........................................................................................................................................61

3.3.2. Europractice..............................................................................................................................61

3.3.3. Mosis........................................................................................................................................62

3.4. Foundries ......................................................................................................................................... 62

3.4.1. IBM...........................................................................................................................................62

3.4.2. ST .............................................................................................................................................62

3.4.3. TSMC ........................................................................................................................................63

3.4.4. UMC .........................................................................................................................................63

4. CMOS 90 nm TECHNOLOGY ASSESSMENT ................................................................................................64





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4.1. UMC technology analysis.................................................................................................................. 64

4.1.1. Diode selection .........................................................................................................................64

4.1.2. Capacitor selection....................................................................................................................77

4.1.2.1. Type of capacitors....................................................................................................................77

4.1.2.2. Size influence ...........................................................................................................................78

4.2. TSMC 90 nm technology analysis ...................................................................................................... 80

4.2.1. Diode selection .........................................................................................................................80

4.2.2. Capacitor selection....................................................................................................................81

4.2.3. UWB front-end components ......................................................................................................81

4.3. Detailed technology comparison ...................................................................................................... 84

5. CONCLUSIONS AND FUTURE WORK .........................................................................................................87

5.1. CONCLUSIONS .................................................................................................................................. 87

5.1.1. Low power issues ......................................................................................................................87

5.1.2. Use of batteries.........................................................................................................................88

5.1.3. Tag architecture........................................................................................................................88

5.1.4. Tag substrate............................................................................................................................89

5.1.5. IC technology ............................................................................................................................89

5.2. NEXT STEPS ...................................................................................................................................... 90

REFERENCES ................................................................................................................................................92

TABLES ........................................................................................................................................................92

FIGURES ......................................................................................................................................................93

LITERATURES...............................................................................................................................................95





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1. “GREEN” TAG DESIGN ASPECTS

This first section deals with the “green” design aspects related to the tag. Due to the

exponential growth experienced by RFID-based technologies, a vast number of tags are

utilized in many different applications. The maturity of this technology has allowed the

dramatic reduction of the cost of tags, making feasible sub-5 cent RFID tags [Smartres] fully

[EPC_GEN2] compliant. Due to this huge amount of tags demanded by the industry and

service providers, a significant waste is generated, due to the short life-cycle of tags.

Presently, RFID tags are typically manufactured from a silicon chip (IC), a polymer substrate

and a metal (etched/wired) antenna which are held together by adhesives. None of the

typical components are environmentally friendly in terms of ability to decompose, while

many of the materials could lend themselves to recycling and re-use if they could be

effectively managed on a commercial scale currently not available. However, recent research

has been focused on investigating environmental-friendly solutions for tags: this way,

biodegradable materials have been proposed for the tag’s substrate [Smartrac]. In this case,

the tag’s plastic substrate is totally biodegraded within 70 days.

However, the approach of SELECT is slightly different. In our case, tags are intended to be

reutilized within different goods for an expected lifetime up to two years. Therefore,

biodegradable materials are not feasible solutions for tags. However, to design energy

efficient tags is a key aspect to extend the life of the batteries and therefore the turnaround

time for waste generation.

Within this context, our “green” approach is faced from a double perspective:

• On the one hand, low power issues are discussed in section 1.1; to reduce the power

consumption of the tag directly impacts on the environment, as the lower the power

consumption, the longer the operation life of the tags without battery replacement.

This way, the waste generated by the battery replacement has a longer duty cycle.

• On the other hand, a clearer focus on the environmental impact related to the tag

performance is provided in sections 1.2 and 1.3, where some considerations about

the use of batteries are given, as well as the most popular materials for the tag

implementation.

However, the environmental impact of the tags and also the whole SELECT system will be

deeply analyzed in a further stage of the project, to be precise within WP7, task T7.3:

Environmental impact, sustainability and privacy aspects. This task will analyze the

opportunities for implementation of reusable RFID tags and packaging in logistics processes.

The combination of reusable packaging and reusable RFID tags is an important element for

achieving stronger ROI and to attain sustainability, cost-benefit analysis will be performed on

the use-cases. The possible implications of the developed system to the environment and

sustainability will be analyzed. The result of this task will be included in the

recommendations for future use.





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1.1. Low power issues

One of the key aspects to increase the tag's lifetime is directly related to its power

consumption: the lower the power consumption, the lower the battery energy requirements,

and hence the longer the tag's lifetime. This way, the environmental impact is lower due to

the fact that less waste is generated by the use of batteries. Therefore, to analyze

techniques that allow reducing the tag's power consumption is the goal of this subsection.

First, some hints about the relationship of CMOS technology downscaling and power

consumption is analyzed in section 1.1.1. Then, some preliminary considerations about the

tag architecture are summarized in section 1.1.2, although a deeper analysis is carried out

within section 2. Finally, several techniques related to the tag's power management are

summarized in section 1.1.3, where the following concepts are addressed:

• Multi-VDD

• Energy harvesting technologies

• Voltage regulation

• Stand-by operation and power gating

• Energy storage

1.1.1. IC technology for low power consumption

The strong demand on new electronic devices with better performances and at lower cost

has led the electronic industry to the production of devices in submicron CMOS technologies

[Baschirotto09] reducing intensively the length of the transistor gate. Due to this reduction,

a noticeable increase in maximum transistor switching frequency is obtained and, as a

consequence, there is an enhancement of the performances at the same time that power

consumption is reduced for microprocessors and digital memories.

Supply voltage downscaling is perhaps the most effective way of reducing logic circuits

power [Chen10], as the dynamic switching of transistors scales quadratically with VDD.

Voltage downscaling also increases latency, especially when VDD is scaled to the

subthreshold region. Even though leakage power also scales down with VDD, leakage energy

per cycle increases because of this increased latency. However, as shown in Figure 2, the

competing trends in dynamic and leakage energy result in an intermediate voltage where

total energy per cycle is minimized [Zhai04].





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Figure 1. Reduction of the size of MOS transistors in the last years (ITRS Roadmap)

Figure 2. Dynamic energy and leakage power vs. supply voltage [Chen10]

However, analog circuits do not benefit from technology scaling, as several second order

effects in the transistor that were irrelevant with classical techniques become now





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dominant, (i.e. the increase in the leakage current or the decrease on the output resistance).

These effects highlight the need to develop new design techniques based on smart biasing,

auto-calibration and/or oversampling, which, at the end, cause an increase in power

consumption.

Some of the major challenges that analog designers have to face are:

• Improving signal to noise ratio (SNR). As technology scales down, the available signal

swing decreases with the supply voltage. In addition, the threshold voltage does not

diminish in the same proportion so that the available voltage headroom is even more

limited.

• Achieving a high gain. Precision in analog design is obtained thanks to feedback,

which requires a high gain to be effective. The small signal gain of the transistor is

given by gm/gds, where gm is the transistor transconductance and gds is the output

conductance. As the technology scales down, the transistor gain of the basic MOS

transistor decreases significantly from typical 15.2 to 6.1 for a 250 nm and 65n m

technology [Pekarik04] respectively.

• A high leakage current. In modern technologies, the leakage current through the

gate of the MOS transistor and the drain current for a transistor in the cut-off region

are no longer negligible.

• Bad matching. The matching between MOS transistors improves with the scale of the

technology [Baschirotto09], [Pekarik04], [Pelgrom89], [Annema05], [Iwai99];

however, small devices suffer from a higher mismatch as it is inversely proportional

to , where W and L are the width and length of the MOS transistor respectively

[Pelgrom89], [Iwai99], [Iwai05], [Garg03]. In addition, quantum effects could be

limiting the matching as the oxide width has been reduced to only a few layers. In

fact, these effects are becoming so important that they are also affecting digital

circuits as, for example, SRAM memories [Baschirotto06], [Nauta05], [Singh09],

[Fayomi04], [Torrens10].

• Large deviation of transistor parameters. Several effects, most of them difficult to

control, cause large variations in the threshold voltage of the MOS transistors in deep

submicron technologies. These effects include short channel effects; the influence of

vertical fields on the mobility of charge carriers, lateral field or Drain Induced Barrier

Lowering (DIBL). These variations make the dispersion in the analog behavior one of

the major problems encountered in nanometer technologies, so that further research

is needed to guarantee correct operation of the analog circuits in spite of changes in

the device parameters.

On the other hand, technology downscaling also causes significant positive effects such as:

• Maximum operating frequency. The maximum operating frequency of transistors

increases significantly.

• MIM capacitors. The characteristics of the vertical Metal-Insulator-Metal capacity

benefit from the increase in the number of metals layers in modern technologies and

the improvement in the control of photolithography process that allows for

capacitors with improved matching and lower parasitic capacitances. A short study of





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the capacitance values of MIM capacitors by both UMC and TSMC 90 nm is

summarized in section 4.1.2 and 4.2.2 respectively.

The highly positive consequences of technology downscaling in the logic circuitry can be

used to digitally compensate the lack of precision of analog circuits. Therefore, mixed signal

circuit design without using high precision analog blocks is one of the most promising

research lines in analog microelectronics [Chae08], [Veldhoven08], [Fiorenza06],

[Anthony08], [Nazemi08]. Described below are some trends in analog microelectronic design

for deep submicron technologies that might be researched within this project.

• Trends at the circuit level:

o New dynamic biasing techniques which reduce the power taken from the

supply when the input signal allows it.

o New techniques to compensate for manufacturing process based on tuning

circuits and/or local feedback.

o Validation of current low power design techniques for nanometer

technologies.

o New techniques to increase the gain in amplifiers mainly based on “gain

boosting” and cascade amplifiers.

• Trends at the system level: Use of digital circuits to compensate for the lack of

precision of analog blocks mainly through digital calibration, analog circuit

redundancy and/or oversampling [Lewyn09].

1.1.2. Tag architecture considerations

The tag architecture plays a key role with regard to its cost, but also, and more importantly,

to its power consumption and therefore tag's lifetime. Within the SELECT tags, two different

systems (RFID and UWB) must operate in the same chip; therefore more complexity is

required in the tag's IC for both systems coexistence. However, a top-down approach for the

tag design seems to be a good point to try to reduce such complexity and therefore device

size and power consumption.

To do so, some design decisions have been taken with regard to the design of the tag:

• Both sections (RFID and UWB) will share the same antenna

• Both sections (RFID and UWB) will share the logic memory.

• The UWB section will be power assisted by a single battery (see section 1.2).

How both tag's sections coexist with each other will be discussed in Section 2, where several

architectures will be considered for the tag IC as preliminary candidates for its

implementation. Then, after comparing their performance in terms of complexity and power

consumption, a preliminary architecture will be selected. However, the final decision about

the tag architecture has to be taken in task T3.4 after performance evaluations carried out in

WP2 will be available.





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1.1.3. Power management

One of the main sources of power consumption of the tags is the digital subsystem. The

digital circuits of tags decode recovered data, handle the commands, read/write data

from/to the EEPROM, and generate backscattered data. Digital circuits of GEN2 tags

[EPC_GEN2] can consume the same magnitude power as analog circuits due to the

complexity of the protocol [Luo09].

The total power consumed by a digital circuit can be categorized into four different terms

[Sadegui06], [Chandrakasan92]:

• Capacitive switching power

• Short circuit current

• Sub-threshold leakage power

• Leakage current

All these effects are included in the following equation, which evaluates the total power

consumption of any circuit:

[Eq. 1]

where the first term represents the power consumption due to switching activity in the

system (dynamic power): α is the switching activity, C is the capacitance of the load, f is the

clock frequency and VDD is the supply voltage. The second term is usually called static power

and represents the effect of the static current (or dc current), that arises due to the presence

of coupling paths between VDD and ground (ISC). The power consumption due to static

current is highly undesirable in low power designs. Finally, the third and the last terms in the

equation represent the power consumption due to leakage currents. Leakage current results

from substrate injection and sub threshold effects (ISUB) [Chandrakasan92]. The other form

of leakage current is gate leakage current (IGL), arising from gate oxide which is mostly

dependent on gate oxide thickness.

Among these four effects, the power consumption of CMOS digital circuit is mostly

dominated by the dynamic power consumption [Sadeghi06], [Mohanty01]. This is because

the dominant feature in any well designed circuit is its switching activity [Chandrakasan92].

For this reason, reducing the clock frequency could result in a significative power reduction

in the tag [Luo09].

1.1.3.1. Multi-VDD

All the terms in eq. 1 are VDD dependent. Therefore, a straightforward solution for reducing

the power consumption is to down-scale the voltage supply (VDD). As it has been mentioned

in section 1.1.1, technology downscaling reduces the circuits power consumption, as it

allows lower voltage supplies, while maintaining a good performance regarding to the digital

subsystems. More precisely, all digital circuits in the tag would run with the highest energy

efficiency at subthreshold or near-threshold supply voltage, ranging from 300 mV up to 600





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mV. However, analog circuits usually require higher VDD to ensure proper voltage headroom

and transmission power levels (ranges from 1.2 V to 2.5 V).

A good solution to cope with both analog and digital subsystems’ needs in terms of supply

voltage is the utilization of multi-VDD techniques. The idea behind these techniques consists

on the use of multiple VDD values for a single chip by dividing the integrated circuits into

regions, called voltage islands [Puri05], operating at different voltages, as it is shown in

Figure 3. This way, RF and analog circuits are supplied with higher voltages (VDDH), and the

digital circuits (except those being in critical paths) are supplied with lower voltages (VDDL).

Eventually some digital subsystems could by supplied with higher voltages (i.e. EEPROM

memories for write operations).

Figure 3. Multi-VDD technique overview

Although multi-VDD seems to be a straightforward solution to lower the power consumption

in mixed-mode systems as the voltage islands might seem clearly separated, the

introduction of voltage islands could result in a very complicated issue when used in complex

digital systems. The main issues are with respect to static timing, power routing,

floorplanning, etc. In particular, the complexity grows significantly with the number of

allowed islands. Thus, a designer using voltage islands needs to group together the cores

powered by the same voltage source and ensure that the created grouping does not violate

other design metrics such as timing and wiring congestion. Different methodologies for a

power-efficient system floorplanning have been reported in [Hu04] and [Puri05], including

temperature aware methodologies [Hung05], where up to 30% power consumption

reduction have been reported.

If not at such complicated level, multi-VDD will be used in SELECT for the design of tag’s

subsystems, as different supply voltages for analog, mixed-signal, digital circuits and logic

memory will result in a better performance with regard to power consumption.





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1.1.3.2. Energy harvesting

Energy harvesting (i.e. energy scavenging) is the process of harvesting energy from the

environment or from a surrounding system, and converting it to available power supply

for the electronic circuits. Recent advances in wireless technology and ultra-low-power

electronics such as MEMS devices have brought an increasing research in this topic

[Huang10], [Marzencki09], [Topal11]: given the wireless nature of the nodes in a wireless

sensor network (WSN), it becomes necessary that each of them contain some autonomous

mean of power supply which is, in most cases, a battery. However, when the battery has

consumed all of its energy, the node (e.g. the sensor) must be retrieved and the battery

replaced. In long-life applications and because of the remote placement of these kinds of

devices, retrieving the sensor simply to replace the battery can become an expensive task.

Furthermore, it can become a tedious (and even impossible) task: for example, in implanted

medical devices and civil infrastructures, where sensors are placed into the structures and

therefore the battery replacement is not feasible. For these reasons, it is desirable to obtain

and utilize the ambient energy in the surrounding medium; this way, the captured energy

can then be used to prolong the life of the battery or, ideally, provide unlimited energy for

the operation life of the device.

These are the reasons why the amount of research devoted to energy harvesting has been

rapidly increasing in long-life wireless applications, such as WSN. Most common ambient

energy harvesting technologies are sunlight, thermal gradient, vibration, electromagnetic RF

energy, body motion and human heat. The energy density of some available (and portable)

energy sources are compared in [Roundy03] and shown in Table 1. This study concludes that

for WSN devices that are supposed to last for about 1 year, battery technology alone is

sufficient to provide enough energy. However, if a device requires a longer service life, an

energy harvester can provide a better solution than battery technologies, although the form

factor and cost of the device might be carefully analyzed with regard to the operation life.

Table 1. Comparison of energy sources [Roundy03]

Energy harvesting source Power density (µW/cm3) Source of info

Solar (outdoors) 15000 (direct sun)

150 (cloudy day) Commonly available

Solar (indoors) 6 (office desk) [Roundy03]

Vibrations 200 [Roundy03]

Acoustic noise 0.003 @ 75 dB

0.96 @ 100 dB Theory

Daily Temp. variation 10 Theory

Temp. gradient 15 @ 15°C gradient [Stordeur97]





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Table 2. Energy harvesting capabilities by [Paradiso05]

Energy harvesting source Performance

Ambient RF < 1 µW/cm2

Ambient light 100 mW/cm2 (direct sun)

100 µW/cm2 (illuminated office)

Thermoelectric 60 µW/cm2

Vibrational

microgenerators

4 µW/cm3 (human motion – Hz)

800 µW/cm3 (machines – kHz)

Ambient airflow 1 mW/cm2

Shown in

Table 2 is another comparison of energy harvesting capabilities performed by [Paradiso05],

which are slightly different from those summarized by Table 1, which shows that still more

accurate performance parameters shall be provided for the energy harvesting technologies

performance comparison. Other studies [Glynne01, Qiwai04, Mateu05] suggest that the

combined use of several energy harvesting strategies in the same device can increase the

harvesting capabilities in many different situations and applications. Nevertheless, as

suggested by [Mateu05] the better way to close the gap between required and harvested

energy is to minimize the circuits’ power consumption.

On the other hand, commercial available energy harvesters are still bulky and relatively

expensive, when referring to ultra-low-cost and low-form-factor applications such as tags. In

this section, some considerations about the most common energy harvesting technologies

are provided. However, it is not intended to be a deep review of possible energy sources for

energy harvesting, as excellent articles can be found in the literature. Only a short

background on each technology and its applicability within SELECT tags will be analyzed.

1.1.3.2.1. Solar energy harvesting

Solar energy is a mature technology for large scale energy generation. Photovoltaic (PV)

systems can be found from the Megawatt to the milliwatt range, generating electrical

energy for a wide range of applications: from handheld devices to grid-connected PV

systems.

Outdoors, solar radiation is the energy source for PV systems. It varies over the earth’s

surface due to weather conditions and location (longitude and latitude). For example, yearly

irradiance in the Netherlands is 992 kWh/m2, whereas it is higher than 2000 kWh/m2 in

Tanzania. For each geo-localization it exists an optimum inclination angle and orientation of

the PV solar cells in order to obtain the maximum radiation over the surface of such cell.

However, indoor irradiance is smaller; depending on the intensity of the room’s lightning,

indoor irradiance varies from 3.5 to 20 W/m2.





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The efficiency of a solar energy harvesting device is defined as the percentage of the

available energy that is actually harvested. Conventional single crystal and polycrystalline

solar cells, such as those that are commonly used in calculators or wrist watches, have

efficiencies of around 10%-20% under direct sunlight [Green08]. However, their efficiency

declines with a decline in the available energy (they are less efficient with dimmer sources),

which is important to note due to considerable irradiance difference between direct sunlight

and indoor illumination. Conventional solar panels are also inflexible (rigid), which makes it

difficult to use for applications where they should be attached to non-rigid items such as

clothing and paper labels.

Figure 4. Flexible module of organic solar cells.

An emerging and less explored option is solar energy harvesting based on organic

semiconductors [Ma05]. With this technology, solar cells can be made flexible, as it is shown

in Figure 4. Moreover, organic semiconductor-based panels operate with constant

efficiencies over different brightness levels. However, their efficiency is typically 1%-1.5%

[Green08], which is much lower than the efficiency of conventional inorganic solar panels.

As mentioned above, the indoor solar irradiance is much lower than in an outdoor

environment. For example, a solar panel with an efficiency of < 10% under the indoor solar

irradiance of 10W/m2 is only 100 µW/cm

2 as compared to 10 mW/cm

2 under the outdoor

standard testing condition (STC). Therefore, indoor solar energy harvesting represents a

significant challenge to be used to power supply electronic circuits as a single source of

energy scavenging.

Furthermore, within the scope of SELECT project regarding to the storage of goods in a

warehouse, this energy harvesting source is considered as non-appropriate. In fact, the

lightning in such warehouse might be intermittent and hence additional means of energy

storage might be necessary within tags, what would increase their complexity and final cost.

Furthermore, some goods in the warehouse might be stacked one over the other, and

therefore PV based energy scavenging would be non-efficient at all in such scenarios. As a

consequence, this harvesting technology will not be considered as power supplier in

SELECT tags.

1.1.3.2.2. Thermal energy harvesting





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Another method of obtaining energy from the ambient is through the use of thermoelectric

generators, which scavenge energy from thermal gradients. Thermoelectric generators

(TEGs) use the Seebeck effect, which describes the current that is generated when the

junction of two dissimilar metals experience a temperature difference. This way, when an

electrical current is applied to the TEG, a thermal gradient is obtained (solid state heat pump

function), Conversely, if a thermal gradient is applied to the TEG, then an electric current is

generated and available to power supply electronic circuits.

As solar energy harvesting technology, the use of thermoelectric devices to scavenge energy

from the environment is not a new concept. However, the principal research effort have

been focused on the utilization of liquid heat exchangers for forced convection that

significantly improves heat flow and power generation, but on the other hand it requires

complex cooling loops and systems.

On the other hand, large Seebeck effects are found in doped poly-Silicon, which makes it a

promising choice for TEGs based on CMOS technology. With the recent advances in

nanotechnologies, MEMS devices are becoming a popular focus on the research of thermal

harvesters. In this case, thin film arrays of p-type and n-type junctions are arranged

electrically in series and thermally in parallel to form thermocouples, and therefore a

thermopile could be arranged in a tiny area. The key challenge of thin-film thermopiles is

that the internal thermal resistance is very small compared with the thermal contacts of the

surrounding assembly, so that the temperature difference between the two ends of a

thermocouple is small and so is the energy generated.

More sophisticated devices have been reported recently [Huesgen08], [Lee09] based on

wafer-bonded vacuum cavities on both sides of a suspended thermoelectric membrane,

which has become an effective approach to increase the performance of TEGs. A SEM

photograph of the cross-sectional view of a MEMS TEG is shown in Figure 5 [Xie10].

However, such devices generate some tens of µW at output voltages higher than 10 V in

most cases; as a consequence, low drain currents are available to supply electronic circuits

using these techniques, especially if low thermal gradients are available

Figure 5. SEM photograph of the cross-sectional view of a MEMS Thermoelectric Generator [Xie10]





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As a conclusion, it can be stated that most of the research of such harvesting devices is

focused on applications where significant thermal gradients are available for electrical

energy generation. Most common applications are related to industrial and biomedical

environments, where thermal gradients due to ambient temperature with regard to the

wasted heat of machines or human body temperature respectively are used to harvest

several tens of µW at reasonable low-form factor. However, as no significant thermal

gradients might be available within SELECT scenarios, this harvesting technology is not

considered for the tags power supply.

1.1.3.2.3. Vibration energy harvesting

The generation of energy from a mechanical vibration usually uses ambient vibration

around the energy scavenging device as an energy source and then converts it into available

power supply for the electronic circuits. Most harvesting devices are based in the

piezoelectric effect, first discovered by Jacques and Pierre Curie in 1880, by which certain

materials, when subjected to mechanical strain, suffered an electrical polarization that was

proportional to the applied strain.

The research in this field has been focused on the development of an accurate analytical

model to estimate the power output from piezoelectric transducers; the effects of

components such as mechanical and electrical loads, as well as electrical circuits, has

received also attention from the research community. As a consequence, the analysis and

analytical modelling of piezoelectric energy harvesting technology and analytical can be

found in the literature [Ralib10], [Boussetta10].

A cantilever beam with the piezoelectric patches attached in either a unimorph or a bimorph

form is the most popular configuration for energy harvesting devices [Lin10]. Other authors

utilized the shape of membranes under pressure loading [Ericka05] and plates with a

Helmholtz resonator under fluid/acoustic loading [Ungan09]. In the recent years, the

development of MEMS technology has lead to focus the research attention on micropower

generators, as microscale piezoelectric materials are suitable for microfabrication. For

instance, the microscale piezoelectric harvester developed by [Park10], shown in Figure 6,

generates a maximum AC voltage of 4.4 V (peak to peak) and a maximum continuous

electrical power of 1.1 µW under a resonant frequency of 528 Hz with an acceleration of

0.39g. However, most implementations are based in harmonic excitation at resonance

frequency, which implies low flexibility of devices as they are very much application

(resonant frequency) dependent. By using a stack configuration, broadband vibration energy

harvesting is proposed in [Adhikari09], a more practically available ambient source.





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Figure 6. MEMS energy harvester operating in the d33 mode [Park10]

Nevertheless, it is very difficult to compare different devices based on vibration energy

harvesting principle. The work [Khaligh10] summarizes some experimental and analytical

results on such devices present in the literature. The size of the devices varies significantly,

going from the micro-scale (0.9 mm2) to macro-scale (tens of cm

3); the energy generated

range is also relatively wide among these devices, ranging from 1 µW to some mW.

However, it is also concluded in [duToit05] that the comparison of different vibration

harvesting devices is a very difficult task due to the fact that they use different energy

conversion schemes, which vary in size and mass; they have different input frequency

spectra; and also the different applications they have designed for. These parameters are

not well documented in papers.

Microscale devices are not readily fabricated yet as commercial devices, as the calibration

process is still difficult due to the relatively poor properties of planar magnets, the

restrictions on the number of planar coil turns, and the too small vibration amplitudes. On

the other hand, macroscale devices are available on the market using high performance bulk

magnets and multiturn coils. However, they are still bulky and expensive [Piezo],

[Perpetuum] for ultra-low cost applications, such as tags. Furthermore, the use cases and

applications scoped by SELECT project [SELECT_D1.1] include the placement of devices in

static environments (e.g. storage of goods in a warehouse). With this consideration, it is

difficult that tags might be powered by vibration energy harvesting devices, and therefore

this technology will not be implemented within the design of the tag.

1.1.3.2.4. RF energy harvesting

Another means of energy scavenging for to low-power electronic devices is by wireless

energy transmission. In this case, power is generated elsewhere and delivered to the devices

by some form of electromagnetic waves or RF radiation (Figure 7). Regarding to the nature

of the RF radiation, there are two types of energy sources:

• Controlled RF sources

• Ambient RF sources





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Figure 7. Block diagram of RF energy harvesting principle

The technology that has received more attention in this regard is related to harvest energy

from controlled RF sources, also called “beamed” RF sources. This way, an emitter sends

microwaves across the atmosphere within a particular bandwidth and a maximum emission

power, so the receiver can convert such microwaves into available power supply for the

electronic circuits. This is the principle that well-known RFID systems based on passive tags

have implemented: the UHF RF continuous wave emitted by the reader is rectified by a

voltage multiplier and managed by a power management unit (voltage limitation, regulation,

etc.) and used to supply the electronic circuits of the RFID tag.

On the other hand, ambient RF sources are used to harvest energy from ambient

electromagnetic waves (noise) that are present in the ambient. In this case, the DC

scavenged power depends on the available RF power and conversion efficiency of the

rectifier. However, the complexity of such systems is higher as specific antennas and

rectifiers must be implemented for the RF frequencies that might be considered (i.e.

GSM900, GSM1800, WiFi 2.45 GHz, etc.). In addition, the power levels reported in the

literature are very low: [Bouchoicha10] reports an average power of 3.5 nW from GSM1800

“noise” signals at a 100 m distance. Although higher levels have been achieved by Intel

Research in WARP project [Sample07], the receiver implements a Yagi antenna, so it seems

that the size of the antenna is key to have efficiency enough to get significant energy to

power electronic devices.

For SELECT project, UHF RF signals will be used as energy harvesting source to power

supply the UHF RFID section of the tags. On the other hand, the capability of such energy

scavenging source for the UWB section will be explored within task T3.4 of WP3 (Analog

fron-end design) depending on the power budget estimation of the tag’s UWB section and

the final architecture selected for tag implementation.

1.1.3.2.5. Other energy harvesting technologies

Despite the fact that there are other energy harvesting sources to power supply low-power

electronic devices, i.e. kinetic energy, human heat, etc., they are out of the scope of SELECT

and they will not be considered in this work.

1.1.3.2.6. Conclusions about energy harvesting

Nowadays, energy harvesting technologies have become a hot research topic for powering

low-power electronic devices autonomously. This way, as stated above, electronic devices

powered by energy harvesters would increase their lifetime indefinitely without the use of

batteries. This is very practical in applications where devices might be located in non

accessible places and therefore the replacement of the battery would be even impossible.

This is the case of the Wireless Sensor Networks, where lifetimes up to 10 years or even

more are considered in most cases.

However, energy harvesting devices are usually bulky and relatively expensive, but still the

best approach for the applications mentioned before. The case of SELECT is different, due to





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the fact that one of the key benefits of the project implies low-size and low-cost tags, and

therefore energy harvesters would mean an excessive cost for a 2-years lifetime. In addition,

energy harvesting devices need special conditions to power the devices with the proper

efficiency:

• Solar devices operate more efficiently outdoors, and when solar cells are exposed

under the sun. In indoors environments, the efficiency drops dramatically, and this

source of energy might be even impractical if harvesters are in “shaded” areas, e.g.

when stacked one under each other.

• One of the main applications within SELECT is related to the storage of goods in

warehouses. In this environment, vibrations might not be produced, and therefore

that kind of energy harvesting technology is not practical for the project.

• For the same reasons as the vibration-based energy harvesters, thermal gradient-

based devices are not practical for SELECT, as no thermal gradient might be available

in the tag for energy scavenging.

• RF specific radiation has been used successfully for passive RFID systems in the UHF

band.

For these reasons, only RF radiation will be used within SELECT tags as a means of energy

harvesting for the electronic circuits. In principle, such energy source will be used to power

supply the tag's UHF section, although the possibility of supply the UWB section too (or at

least a part of it) will be explored in task T3.4 (Analog front-end design).

1.1.3.3. Voltage regulation

In RFID, the supply voltage is rectified from RF. In order to obtain the operating voltage of

the circuit to operate properly, electronic circuits that convert the rectified power source

into the required voltage are needed. Here, this voltage regulator is called dc-dc converter.

As shown in Figure 8, a dc-dc converter regulates the input voltage, Vin, into the desired

output voltage, Vout, as a voltage level converter.

Figure 8: DC-DC converter.

DC-DC converters are categorized into three types: buck converter, boost converter and

buck-boost converter [Man06].

• Buck converter: converts from high voltage to low voltage

• Boost converter: converts from low voltage to high voltage





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• Buck-boost converter: converts from a certain level to a required level (low or high)

In this paragraph, buck converter technique is explained. Buck converter is sometimes called

“down converter”. To design a buck converter, three types of regulator are available:

• linear regulator

• capacitive switching regulator

• inductive switching regulator

Down converter always targets a smaller size, higher efficiency, wider conversion range,

larger output load range, faster response time and smaller ripple voltage. Even though

implemented on a tag, the basic purpose is of course the same. The main objective is to

realize low-power consumption by considering the power consumption of dc-dc converter

itself. Thus, following sections mainly focus on circuit architecture, operation principle and

power efficiency.

Power efficiency is simply defined with the input power and the output power as expressed

in Eq. 2:

in

out

P

P=η [Eq. 2]

Generally, the power efficiency is expressed with η. Moreover, Pin is the input power and Pout

is the output power. The output power is always lower than the input power, thus the

power efficiency is expressed as a percentage and ranges from 0% to 100%. In the ideal

condition where there is no power loss on the conversion, power efficiency reaches 100%.

In the coming lines, three types of regulator are explained with typical circuit structures.

1.1.3.3.1. Linear Regulator

The linear regulator is often called “series regulator”. Figure 9 shows the first order model of

a linear regulator with a CMOS technology.

-+

Cout

vout

Vref

Vin

R2

R1

vfb

iout

icompError Amplifier iin





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Figure 9: First order model of linear regulator.

In this simple example, a PMOS transistor is used as a power gate transistor and is connected

to the input power node, Vin. In order to stabilize the output voltage, Vout, an output

capacitance is often inserted between the output node and the ground. The output voltage

is controlled through the feedback loop with two resistances, R1 and R2 and an error

amplifier. This amplifier determines the gate voltage level of the power gate transistor by

the amplified voltage difference between the feedback output voltage and the reference

voltage, Vref. This monitoring function makes the output voltage follow the reference voltage.

In Figure 9, the output load is expressed with Iout. A linear regulator does not always need

the output capacitance represented in Figure 9. Thus, this regulator is preferred in

integrated circuits, where area is a major concern.

10-4 10-3 10-2 10-1 1000

20

40

60

80

100

Eff

icie

ncy η

linear [%

]

Iout [A]

Vout = 1.2 V,

1.0 V,0.8 V

Pcomp : 1 mW : 10 mW

Figure 10. Power efficiency of linear regulator with various Pcomp

Figure 10 shows efficiency calculation results for different converter consumption (Pcomp).

The following conclusions may be extracted:

• Power efficiency of linear regulators is proportional to the voltage conversion ratio,

Vout/Vin. This means that lower output voltage compared to the input voltage always

leads to worse power efficiency.

• As the control power consumption of Pcomp, which is a constant value, becomes

dominant for low output currents, the power efficiency is low when the output

current is low.

• Resistive power loss for large output load current is ignored here. Therefore, in such

a case, power efficiency is only defined by the voltage conversion ratio.





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1.1.3.3.2. Switched Capacitor Circuits

Sometimes, this type of regulator circuit is called charge pump circuit. Figure 11 is one

example of a capacitive switching regulator that can change the output voltage with a

reconfigurable switch network states [Ramadass07].

Figure 11: An example of the power stage circuit in a capacitive switching regulator.

Two-phase and non-overlapping switching signal controls all the switches and determines

the output ratio. The operation states are described in Table 3.

Table 3. Operation states of switches

Turn-on timing Ratio

Phase 1 Phase 2 Always off

1/3 sw2, sw5, sw6 sw1, sw3, sw8, sw9 sw4, sw7

1/2 sw4, sw5, sw6, sw7 sw1, sw3, sw8, sw9 sw2

2/3 sw4, sw5, sw6, sw7 sw1, sw2, sw3 sw8, sw9

Now picking up the case of half-voltage conversion, the basic operation is explained here. In

the phase 1, switch 4, 5, 6 and 7 are turned on, and switch 1, 3, 8 and 9 are turned on in the

phase 2 as represented in Table 3. Thus, the operation state becomes as shown in Figure 12.





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Figure 12 : Operation state of half-voltage conversion.

By analyzing the charge transferred, we can derive the following relation:

inout VV2

1= [Eq. 3]

The circuit presented in Figure 12 converts the input voltage into a half voltage value of the

output voltage. It has to be noted that the input voltage only determines the output voltage

regardless of the capacitances. In the same manner, and as explained above, another ratio

can be obtained according to the switching operations summarized in Table 3.

1.1.3.3.3. Inductive Regulator

One example of an inductive switching regulator is shown in Figure 13 [Wei99]. This

structure has a feedback loop referring to the desired reference voltage, Vref.

Figure 13: An example of a simple inductive switching regulator.

A simple structure of a switching down regulator power stage fabricated with a CMOS

technology is shown in Figure 14. Iout represents the output load current.

L RL

C

iL

VL iC

vout

Inductor

vS

iout

Vinicomp

Switching

controller

Figure 14: Typical switching regulator power stage.





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Figure 15 shows efficiency calculation results for power consumption values (Pcomp).

Figure 15: Power efficiency of an inductive switching regulator with various Pcomp.

Based on this analysis, the following can be summarized:

• Power efficiency of switching regulators is independent from the input power supply

voltage Vin

• However, Pcomp depends on Vin if Vin is chosen to supply the control loop in the actual

implementation. However, this factor is ignored here.

• The power efficiency decreases as the output voltage decreases.

• As the control power consumption Pcomp, which is assumed as a constant value here,

becomes dominant for low output currents, the power efficiency is low when the

output current is low.

1.1.3.3.4. Voltage regulation comparison

Table 4 compares the different architectures of dc-dc converters we presented in previous

sections.

Table 4. Feature summary on three types of down converters

Type Required

discrete device

CMOS

compatibility

Power

efficiency

Maximum

output load

Area

Linear - YES YES YES

Capacitive C YES

Inductive C, L YES YES





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Considering the linear regulator, the biggest advantages are its small area occupation and

the needless of discrete devices. Thus, from the viewpoint of the CMOS design, this

regulator is easy to implement. However, the power efficiency is almost determined by the

ratio of the input voltage and the output voltage. Thus, when the voltage difference

between these two is large, the power efficiency becomes low.

Considering the capacitive switching regulator, the power efficiency is not so bad, but a few

capacitances have to be introduced to convert the voltage. However, according to the

previous implementation reports, the maximum output load was below 1 mA. And worse,

circuit schematic always determines the conversion ratio, thus it is hard to change and

adjust the output voltage on demand.

Finally, considering the inductive switching regulator, the power efficiency is good, but a

capacitance and an inductance have to be introduced to operate the regulator. The occupied

area depends on the implementation style. Its high power efficiency is still attractive and

suitable for the low-power application.

The final choice in the tag implementation will therefore depend on the required voltage

and power range.

1.1.3.4. Stand-By Operation and Power Gating

To fulfil both requirements of using transistor with low threshold voltage to obtain high-

speed operation and reducing stand-by current in the off state, it is highly desirable to

switch on/off some circuits of the tags during its operation. This paragraph details the basic

techniques used for this purpose. The explanation mainly concerns powering on/off digital

circuits but it can also apply to analog devices.

1.1.3.4.1. Multiple-Threshold CMOS (MTCMOS)

The first proposed solution [Mutoh95], [Makino99] has been MTCMOS whose basic concept

circuit is shown in Figure 16.





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Figure 16: Circuit concept of MTCMOS

Logic module can consist of low-threshold voltage transistors for the purpose of high-speed

operation. Their power terminals are connected to power sources through high-threshold

voltage transistors. Bulk nodes of the module are directly connected to the power supply.

In the active state, SLEEP signal is set to low, and then internal power rails represented with

Virtual VDD and Virtual GND function as real power lines. Therefore, the core logic module

operates normally at a high speed.

In the off state, SLEEP signal is set high. Virtual lines are floating. Large leakage current of the

module, which uses low threshold transistors, is relatively suppressed with the high

threshold of the sleep transistors. Therefore, the power consumption during the off state

can be drastically reduced by this sleep control.

According to the reports, MTCMOS requires two-side transistors: header transistor

connected to the power supply node and footer transistor connected to the ground level.

Power gating technique has been proposed instead of MTCMOS and this technique requires

only one-side transistor, header or footer. Comparing between MTCMOS and Power gating,

the later needs smaller area of cut-off transistor. For the suppression of the off state current,

recent SoCs prefer Power gating technique to MTCMOS due to the area occupation.

1.1.3.4.2. Super Cut Off CMOS (SC CMOS)

Scaling down the operating voltage of the transistor, the effective resistance of the sleep

transistor in MTCMOS increases drastically and another cut-off technique using low

threshold transistor , named SC CMOS, has been proposed toward further lower operating

voltage [Kawaguchi98].

Figure 17: Circuit concept of SC CMOS

Figure 17 represents the basic concept of SC CMOS. Low threshold transistor is employed to

cut off the leakage current in the off state. SLEEP signal is boosted through the charge pump

circuit and applied to the gate of the cut-off transistor. The applied bias voltage is a little bit

higher (0.4 V in the reported study) than the nominal operating voltage of the connected

module. A recent study has proposed the optimization of this boosted voltage [Valentian08].





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1.1.3.4.3. Bulk Bias Control

Bulk Bias Control is an interesting technique to prevent the use of big switches. It relies on

the modulation of the threshold voltage to control the leakage current of the transistors. In

order to modulate the threshold voltage, a couple of bias control technique has been

proposed. These techniques are categorized into two: back bias control and forward bias

control In general, back bias is called Reverse Body Bias (RBB) and this one contributes to

lower the leakage current. Therefore we will only describe this technique [Nose02].

In RBB, the bulk node bias of NMOS transistor is lower than the ground level, and the one of

the PMOS transistor is higher than the operating voltage. The effective threshold voltage is

higher than the zero-substrate bias threshold voltage. Thus, the leakage current is reduced

in the off state with RBB. This principle is briefly described in Figure 18.

Figure 18: Reverse body bias (RBB)

In order to obtain the bias voltage, a bias generator circuit is required, like charge pump or

external dc-dc converter. To calculate the whole power consumption in the off state, the

power consumption of the bias generator has to be taken into account.

With regard to the project, these techniques will be used to power manage the electronic

subsystems. However, the specific strategy cannot be set at this stage of the project.

1.1.3.5. Energy Storage

Without the ability to store energy, a device can operate only when directly powered by

environmental energy or a battery. For a RFID tag, energy storage components need to be

compact and efficient, and need to have very low self-discharge rates.

On the other hand, secondary (i.e. rechargeable) batteries are an excellent option for energy

storage, and numerous battery options are available. Thin film batteries are particularly

attractive for the tags, since they are environmentally friendly and can be made flexible.

However, a battery needs to be supplied with a voltage exceeding the internal chemical

potential (typically 1.5-3.7 V) in order to start storing provided energy. This implies that

charge generated at a low voltage, such as that possibly produced during low harvester





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excitation (for example, when ambient RF energy is scavenged), cannot be stored without

voltage up-conversion, which complicates the design and adds more consumption to the

power budget.

Capacitors can also be used for energy storage. Capacitors can receive any charge which

exceeds their stored voltage and be cycled many more times than batteries. The

disadvantage of using capacitors, however, is that as a capacitor gets more charged, it

becomes more difficult to add charge, and large electrolytic capacitors self-discharge over

hours or days. The energy density (how much energy can be stored per unit of volume) of

capacitors is also much lower. In addition, external devices would increase the cost of the

tags. However, they represent the best choice (and necessary) when RF energy is harvested,

e.g. UHF tags.

As RF energy scavenging will be used for the RFID section of the tags, energy storage

capacitance is necessary. As the most cost (and form-factor) effective approach is to

implement such capacitance on-chip, high density capacitors are necessary to be provided

by the CMOS technology used for IC fabrication. This characteristic will be analyzed in

section 4.

1.2. Considerations about the use of batteries

In the SELECT project, a battery will be used in order to supply some parts of the tag, such as

the UWB-based subsystems as well as the logic circuitry (digital subsystem and memory). As

low cost tags are targeted, it is necessary also to employ a low-cost but long-life battery. In

this section the different possibilities for the tag’s battery are analyzed.

1.2.1. Batteries main classification

Batteries can be classified in two main groups: primary and secondary batteries [Intertek].

Primary batteries can provide energy once they are assembled but they can be used only

once because the chemical reactions that supply the electrical currents are irreversible.

Secondary batteries are those in which the electrochemical reactions that generate the

electrical current are reversible. This reversion is done by a reverse current flowing through

the battery.

On the one hand, the main advantages of primary batteries are their low initial cost, their

low self-discharge rate (which usually is greater than 10 years) and their high energy density.

This makes this type of batteries suitable for low power applications, such as watches, IR

remote, etc., where very low power consumption is required in specific moments. The main

disadvantages are that they cannot be recharged once they are run out, the difficulty to

recycle them and finally that they are not suitable for high drain applications [Crompton00].

On the other hand, the main advantages of secondary batteries are that their long-time cost

is lower than the primary batteries. This is due to their recharging capability and the fact that

they can easily handle high drain applications. As a consequence, the secondary batteries

seem more attractive from the environmental point of view. However, their main





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disadvantages are that they need an initial recharge to operate and their self-discharge rate

is lower than this of the primary batteries.

With regard to the SELECT project, a cheap ultra low-power battery-assisted semi-passive

tag will be designed. The current demand of the tag will be low or moderate and it will be

inoperative for long time periods. For these reasons, a primary-type battery will be

implemented in the tag due to the following reasons:

• The cost of primary batteries is lower than the cost of secondary batteries.

• In secondary batteries, self-discharge would be even greater than the power

consumption of the tag. As a consequence, battery’s self-discharge time would be

the limiting factor regarding to the battery’s lifetime, and not the tag’s power

consumption itself.

• There is no need for recharging the tag’s battery: once it will run out of battery it can

be discarded and replaced by a new one (if necessary).

1.2.2. Primary batteries

As concluded in section 1.2.1, a primary-type battery is preferred for SELECT’s tags. In this

section, different types of primary batteries are analyzed and a further decision for the

project is taken as a conclusion.

1.2.2.1. Carbon Zinc batteries

In the carbon-zinc battery, the positive terminal is a carbon rod surrounded by a mixture of

manganese dioxide and carbon powder. The electrolyte used is a paste of zinc chloride and

ammonium chloride dissolved in water. The Carbon-zinc battery can be made in a thin-film

form factor with a thickness from 700 to 500 microns, which makes this battery very

attractive for its use in RFID applications. The main advantage of carbon-zinc is that it has

the lowest cost on the market.

PROPERTIES

• Operating Temperature -6 °C to 54 °C

• Volumetric Energy density 120-152 mWh/cm3

• Gravimetric Energy density 55-77 mWh/gr

• Discharge Rate Sloping

• Storage Life Up to 18 months

• Environmental impact low

• Nominal Voltage 1.5 V





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1.2.2.2. Zinc Chloride batteries

The zinc chloride cell is an improvement on the original zinc-carbon cell, using purer

chemicals and giving a longer life and steadier voltage output as it is used. Instead of an

electrolyte mixture containing much NH4Cl, it is largely only ZnCl2 paste.

PROPERTIES




• Discharge Rate Sloping.

• Storage Life Up to 24 months

• Environmental impact Low


1.2.2.3. Alkaline batteries

Alkaline batteries are the most common battery types. They consist of manganese dioxide,

zinc and zinc electrolyte. The alkaline battery gets its name because it has an alkaline

electrolyte of potassium hydroxide, instead of the acidic ammonium chloride or zinc chloride

electrolyte of the zinc-carbon batteries.

PROPERTIES




• Discharge Rate Sloping.

• Storage Life Loses 5% of performance per year.

• Environmental impact Low


1.2.2.4. Organic Radical Battery

Organic radical battery (ORB) is a new battery technology being developed by NEC. ORB's are

characterized by an extremely thin profile (up to 0.3 mm), flexibility, and very fast charge

time. First prototypes announced by [NEC] are still only 0.7 mm thin and are much more





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reliable than previous prototypes while delivering 1.4 times more output (5 mAh). The

technology is also being welcomed by environmentalists because ORB batteries do not

contain any of the heavy metals that pose the problem of proper disposal. Until the date,

they are no available on the market for commercial use.

1.2.2.5. Lithium batteries

Lithium batteries' voltage have medium to high discharge rate and are among the most

expensive on the market. Emitting huge quantities of energy and holding a high capacity of

current, a lithium battery’s energy discharge is low and works optimally at low temperatures.

There are several types of lithium batteries that will be analyzed in the next section.

1.2.2.6. Summary of Primary batteries

Table 5 summarizes a comparison of the different primary batteries analyzed above:

Table 5. Primary batteries PROS and CONS

Alkaline batteries (1.5 V) Carbon-Zinc batteries (1.5 V)

PROS CONS PROS CONS

- Good performance with

Temperature - Bulky - Very low cost - Medium discharge rate

- Long shelf life - Wide size-range available - Poor shell life

- High energy density - Performance

- High drain applications

Zinc-Chloride batteries (1.5 V) Lithium batteries (3 V)

PROS CONS PROS CONS

- Low-medium cost - Temperature dependence - High drain applications - Cost

- Wide size-range available - Medium shelf life - High energy density

- Medium energy density

- Good performance with

Temperature

- Low discharge rate

- Sizeability

Lithium is a lightweight metal that easily forms ions, so it is excellent for making batteries.

There are several types of lithium-based primary batteries, depending on its chemistry; thus,

a deeper study on this kind of batteries is presented within the following sections, due to the

advantages that this kind of batteries might provide for the SELECT project.

1.2.3. Lithium batteries

There are different types of Lithium batteries [Contour]. In the following section, the most

used are presented and analyzed in order to choose the battery which better fits within

SELECT project.





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1.2.3.1. Lithium/Manganese Dioxide

Lithium/Manganese Dioxide (Li/MnO2) batteries are found in a variety of shapes, with the

most common being the button cells and the cylindrical batteries. Li/MnO2 batteries are the

current market share leader, estimated by [Frost&Sullivan] to be at approximately 50% in

2010.

PROPERTIES




• Discharge Rate Flat

• Storage Life loses 0.5% per year

• Environmental impact Medium

• Nominal Voltage 3 V

1.2.3.2. Lithium/Sulfur Dioxide

The construction of the Lithium/Sulfur Dioxide (Li/SO2) cell is typically cylindrical. Li/SO2

batteries provide a competitive price/performance ratio and can operate at very low

temperatures. The use of a liquid cathode also gives this battery an advantage in certain

high-pulse applications.

PROPERTIES


• Volumetric energy density 350-450 mWh/cm3

• Gravimetric energy density 240-280 mWh/gr


• Storage Life 10 years

• Environmental impact High

• Nominal Voltage 3 V

1.2.3.3. Lithium/Thionyl Chloride

Lithium Thionyl Chloride (LiSOCl2) cells have the highest energy density of all Lithium types.

These cells are best suited for applications having low continuous-current and moderate





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pulse-current requirements. Li/SOCl2 batteries afford improvements over Lithium/Sulfur

Dioxide batteries in both operating temperature range and shelf life.

PROPERTIES





• Storage Life > 10 years

• Environmental impact High


1.2.3.4. Lithium/Polycarbon Monofluoride

Lithium/Polycarbon Monofluoride (Li/(CF)n) batteries have a similar volumetric energy

density and longer shelf life than Manganese Dioxide batteries, and are just as safe to

operate.

PROPERTIES


• Voumetric Energy density 500-1000 mWh/cm3




• Environmental impact Moderate


1.2.3.5. Advanced Lithium Carbon Fluoride Batteries

The advanced Lithium/Carbon Fluoride (Li/CFx) battery maintains the benefits of high energy

and power densities, wide operating temperature range and long shelf life found in Sulfur

Dioxide and Thionyl Chloride batteries, while employing a solid cathode (with no heavy

metals or other toxic materials) to eliminate the safety and environmental concerns





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PROPERTIES



• Gravimetric Energy density > 700 mWh/gr



• Environmental impact Moderate


1.2.3.6. Summary of Lithium batteries

Table 6 summarizes a comparison of the different Lithium batteries analyzed above, whereas

Figure 19 shows their volumetric density (expressed in Wh/l).

Table 6. Lithium batteries PROS and CONS

Li/MnO2 Li/SO2

PROS CONS PROS CONS

- Low Cost

- Safe operation - Limited operating temperature range

- Limited high operating temperature

- Suffers from passivation

(causing overheating and pressure

build-up)

- Generates toxic waste

- Low cost

- High pulse-power

capability

- Low operating

temperature

Li/SOCI2 Li/(CF)n—Li/CFx

PROS CONS PROS CONS

- High volumetric

energy density

- High pulse-power

capability

- Long service/shelf life

- Wide operating

temperature range

- Low gravimetric energy and power

densities

- Suffers from passivation

- Safety concerns during high sustained

discharge (causing pressure build-up)

- Generates toxic waste

- High energy and power

densities

- Very wide operating

temperature range

- Long service/shelf life

- Moderately higher cost but with

improved price/performance





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Figure 19 . Volumetric density of lithium batteries

1.2.4. Conclusions about the use of batteries

Errore. L'origine riferimento non è stata trovata. provides a summary comparison of the key

characteristics for all five types of primary batteries presented above. On the other hand,

their volumetric density (expressed in Wh/l) is shown in Figure 19.

Table 7 Primary batteries main parameters comparison

Non lithium batteries Lithium batteries

Zinc-

Carbon

Zinc-

Chloride Alkaline Li/MnO2 Li/SO2 Li/SOCl2 Li/(CF)n Li/CFx

Gravimetric

Energy Density

(Wh/kg)

55-77 70-100 20-150 150-250 240-280 250-400 200-300 >700

Volumetric

Energy Density

(Wh/l)

120-152 160-190 160-400 500-650 350-450 600-900 500-600 700-1000

Temperature

Range (°C) -6 to 54 -15 to 70 -20 to 50 -20 to 60 -55 to

70

-55 to

150 -20 to 60 -60 to 160

Discharge rate Sloping Sloping Sloping Flat Flat Flat Flat Flat

Typical Shelf

Life (Years) Up to 18

months

Up to 24

months

Loses 5%

per year. 5-10 10 15-20 15 15

Environmental

Impact Low Low Low Moderate High High Moderate Moderate

Nominal Volt. 1,5 1,5 1,5 3.3 V 3 V 3.6 V 3.2 V 3.1 V

Weight for 2

years with 50

uW (grams)

11,39 8,77 5,84 3,50 3,13 2,19 2,92 1,25

Volume for 2

years with 50

uW (cm3)

5,77 4,62 2,19 1,35 1,94 0,97 1,46 0,87





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Table 7 shows a comparison among the several types of batteries analyzed in this study. For

the tag that is going to be designed within SELECT project, a maximum power consumption

of 50 uW (DoW) and a minimum life of two years is expected. Due to its poor shelf-life

(below the expected life of the tag), the carbon batteries cannot be used. Thus, either

alkaline batteries or Lithium batteries should be used. For RFID applications the lithium

battery seems the more feasible type to be used for SELECT tags, due to the following

reasons:

• They show a good performance against temperature variations

• Their low discharge rate means longer battery life, limited by the power consumption

of the tag and not by the shelf life of the battery

• Their high energy density and sizeability allow implementing low-form factor

batteries for drain currents in the range of µA at a reasonable cost. For a battery

volume similar to a credit card’s, the expected battery life for lithium is greater than

4 years.

• Their output voltage (3 V) reduces the power management complexity for the access

to the logic memory, i.e. writing operations.

1.3. Materials for tag implementation

Presently, RFID tags are typically manufactured from a silicon chip (IC), a polymer substrate

and a metal (etched/wired) antenna which are held together by adhesives. None of the

typical components are environmentally friendly in terms of ability to decompose, while

many of the materials could lend themselves to recycling and re-use if they could be

effectively managed on a commercial scale currently not available. In this subsection, some

considerations about the tag’s substrate are analyzed. Although SELECT tag prototypes will

be implemented using rigid PCBs, different alternatives that will be further considered for

the system exploitation are here revisited. The printed circuit boards (PCB) are classified

into two types according to their substrates:

• Rigid printed circuit boards (RPC)

• Flexible printed circuit boards (FPC)

The rigid printed circuit boards are generally formed of a rigid dielectric layer having a

plurality of holes for receiving leads of electronic components and a predetermined pattern

of an electrical conductor for being soldered to the leads and interconnect the components

as desired. Today, the rigid printed circuit board is principally applied to the majority of

electronic devices, such as motherboard or a peripheral card of a computer, a mobile phone,

or a board of a consumer product. Flexible circuit structures have been of particular interest

in recent years, because flexible circuit structures have many advantages over rigid circuit

structures. The flexible printed circuit board has properties of lightness, soft, thinness,

smallness, ductility, flexibility and high wiring density and the shape of the flexible printed

circuit board can be changed according to space limitations. In many high volume situations,

flexible circuits also provide cost advantages associated with efficiency of the manufacturing

process employed.





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The following subsections analyze the most common substrates based in the above

classification: RCPs and FPCs.

1.3.1. RPC (Rigid printed circuit)

RPCs are inexpensive, and can be highly reliable. They are fast for high-volume production;

the production and soldering of RPCs can be done by totally automated equipment. The PCB

is composed mainly by three different components:

• Core material: is a rigid sheet of fiberglass resin material that has two sheets of

copper adhered to either side. Some of these dielectrics are: Polytetrafluoroethylene

(Teflon), FR-4, FR-1, CEM-1 or CEM-3

• Pre-Preg material is made of similar material as the core material but is in a soft,

pliable form and comes in standard-sized thin sheets.

• Copper foil is a thin sheet of copper that is placed on or between Pre-Preg materials

and bonds to the Pre-Preg with the adhesive that is part of the Pre-Preg.

1.3.2. FPC (Flexible printed circuit)

Flexible printed circuits is an emerging technology for assembling electronic circuits by

mounting electronic devices on flexible plastic substrates, such as paper or Liquid Crystal

Polymer. Additionally, FPCs can be screen printed silver circuits.

Each element of the flexible circuit construction must be able to consistently meet the

demands placed upon it for the product lifecycle. In addition, the material must play reliably

in concert with the other material elements of the flexible circuit construction to assure ease

of manufacture and reliability. Following are brief descriptions of the basic elements of

flexible circuit construction and their functions.

• Base material: The base material is the flexible polymer or paper film which provides

the foundation for the laminate. Under normal circumstances, the flex circuit base

material provides most primary physical and electrical properties of the flexible

circuit. In the case of adhesive-less circuit constructions, the base material provides

all of the characteristic properties. There are a number of different materials used as

base films including: polyester (PET), polyimide (PI), polyethylene Napthalate (PEN),

Polyetherimide (PEI), along with various Fluropolymers (FEP) and copolymers

Polyimide films are most prevalent owing to their blend of advantageous properties

electrical, mechanical, chemical and thermal.

• Bonding adhesive: Adhesives are used as the bonding medium for creating a

laminate. As with the base films, adhesives come in different thickness. Thickness

selection is typically a function of the application.

• Metal foil: A metal foil is most commonly used as the conductive element of a

flexible laminate. The metal foil is the material from which the circuit paths are

normally etched. A wide variety of metal foils of varying thickness are available from

which to choose and create a flex circuit, however copper foils, serve the vast

majority of all flexible circuit applications





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As the demand for low cost, flexible and power-efficient broadband wireless electronics

increases, the materials and integration techniques become more and more critical and face

more challenges.

The choice of paper or LCP (RPC substrates) as the substrate material presents multiple

advantages and has established the organic substrate as the most promising materials for

UHF RFID applications: their high biodegradability with respect to other ceramic substrates

such as FR-4, requiring only months to turn into organic matter in land-fills. Previous work

has demonstrated the successful development of fully inkjet-printed RFID modules on paper

even with integrated sensors on the paper substrate as well [Yang07].

The following subsections analyze the most common flexible substrates in line with the

SELECT scope. Although few other flexible polymer substrates exist, only paper and Liquid

Cristal Polymer (LCP) will be revisited in this deliverable.

1.3.2.1. Paper Substrate

There are many aspects of paper that make it an excellent candidate for an extremely low-

cost substrate for RFID and other RF applications. Paper; an organic-based substrate, is

widely available; the high demand and the mass production of paper make it the cheapest

material ever made. From a manufacturing point of view, paper is well suited for reel-to-reel

processing, thus mass fabricating RFID inlays on paper becomes more feasible. Paper also

has low surface profile and, with appropriate coating, it is suitable for fast printing processes

such as direct write methodologies instead of the traditional metal etching techniques. A

fast process, like inkjet printing, can be used efficiently to print electronics on/in paper

substrates. This also enables components such as: antennas, IC, memory, batteries and/or

sensors to be easily embedded in/on paper modules. In addition, paper can be made

hydrophobic and/or fire-retardant by adding certain textiles to it, which easily resolve any

moisture absorbing issues that fiber-based materials such as paper suffer from. Last, but not

least, paper is one of the most environmentally-friendly materials; therefore it represents a

desirable approach for implementing any electronic device, such as low-cost tags.

However, due to the wide availability of different types of paper that varies in density,

coating, thickness, and texture, dielectric properties (i.e. dielectric constant and dielectric

loss tangent) or dielectric RF characterization of paper substrates becomes an essential step

before any RF “on-paper” designs. The electrical characterization of paper needs to be

addressed depending on the operation frequency. Prior results have shown the feasibility of

the use of paper in the UHF band [LiYang07], [Yang07], but up to now there is not such

characterization for long range UWB devices. However, this technology might be used in a

chipless tag encoding data into the spectral signature in both magnitude and phase as

presented in [Preradovic09].

PROPERTIES

• Dielectric constant: 3.3 (@ 2 GHz)

• Loss tangent: 0.08 (@ 2 GHz)





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• Can be made hydrophobic

• Inkjet printing availability

• Cost: very low

• Multilayer capability

1.3.2.2. Liquid Crystal Polymer substrate

Liquid Crystal Polymer (LCP) possesses attractive qualities for its use as a substrate on which

implement electronic circuits. It represents a high performance and low-cost substrate and a

valuable choice as a packaging material for numerous applications: RFID/WSN modules,

antenna arrays, microwave filters, high Q-inductors, RFMEMS and other applications

extending throughout the mm-wave frequency spectrum. Furthermore, LCP has low loss, a

flexible (near hermetic) nature, thermal stability, low cost and controlled coefficient of

thermal expansion (CTE) in x-y direction, what makes it one of the best candidates as a

substrate for System on Package (SoP) approach.

LCP also possesses exceptional mechanical properties, not to mention that it is an

environmentally friendly material. A key capability for many applications in RF is the

assumed flexibility and light weight; e.g. antennas on LCP may be conformed into specific

shapes as required by the application needs. LCP is also a near hermetic, thermally stable,

and low water permeability material. This verifies the superiority of using this material for RF

and mm-wave integrated modules, SoP, or packaging applications.

PROPERTIES

• Dielectric constant: 2.9 (@ 10 GHz)

• Loss tangent: 0.0025 (@ 10 GHz)

• Water absorption < 0.04%

• Lamination < 282º C

• Multilayer capability

• Laser drilling (YAG, CO2)

• Low cost

1.3.2.3. RFID substrate trends

Nowadays, most of RFID transponders are made of thin substrates (such as PVC or PET), a

metallic antenna and a microchip. According to [Smartrac] the composition of a standard

Gen 2 EPC RFID tag is very similar that the one of a potato chip bag, though it contains 10

times or more aluminum than a RFID tag. With the massive production of RFID tags, the





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amount of waste generated by this technology is huge, also motivated by the short lifecycle

related to most applications.

The next generation RFID tags will be composed by biodegradable materials, except for the

antenna and chip, employing paper based thin-film substrates that could decompose in a

matter of days. This is very interesting for ticketing applications in which the lifespan of the

tag is only few hours or days. However, due to the longer lifespan of SELECT tags (up to two

years), this type of substrate does not represent a good alternative. In our case, although the

environmental impact of other non-biodegradable substrates is higher, the higher lifespan

implies lower amount in the waste generated.

1.3.3. Circuit Fabrication Techniques

As it has been mentioned above, a tag is very simple system, composed of a silicon chip (IC),

the antenna, and some additional (if the case) external components. All of these elements

are implemented on the substrate, which can be either rigid or flexible. Apart from the

antenna, all the interconnecting metal tracks are routed on the substrate. There are

different ways to fabricate metal paths on substrates:

• Subtractive etching. The earliest method to form an antenna on a rigid substrate is

the subtractive etching. In this process, a copper covered fiber glass is chemically

attacked or mechanically treated in order to remove the copper from the substrate

and draw the metal paths (and antenna). This process is better suited for prototyping

than for large scale productions, due to the fact that the removed copper, either

chemically or mechanically, is wasted, thus increasing the fabrication costs.

• Conductive inks. Conductive inks are typically thin metal particles of either silver or

copper suspended in a polymer vehicle. Conductive ink’s properties of flowing,

adhesion and cohesion are crucial with regard to the obtainable resolution. On the

other hand, metal thickness determines the conductivity of the printed antenna as

well as its resolution (i.e. how efficiently the RF energy can be captured and

backscattered from the RFID tag assembly). In this regard, a design trade-off occurs:

the higher is the particle density of the metallization, the better its conductivity, but

the lower the resolution of the antenna. On the contrary, the lower is the density,

the higher is the resolution, but the lower the conductivity of the antenna. Two types

of processes are foreseen:

o Screen printing. It is the simplest additive method for substrate printing. It is

also inexpensive and widely available, but it is not well suited for large scale

productions: it is relatively slow and not very durable. Another important

issue is the image resolution of the printing method: As the main goal of RFID

industry is tag miniaturization, high resolutions are desirable, not available

with this printing technology.

o Gravure, also called intaglio or dry offset, has been the preferred method for

reproducing high quality photography and art on a mass scale. Gravure

printing with conductive ink is capable of producing high resolutions, and is





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suited for large production runs. On the other hand, setup costs start at about

$2000, a very affordable value for the RFID industry.

• Vapor deposition. Vapor deposition refers to the process by which a material in a

vapor state is suspended in a vacuum and condensed on the substrate to form layers

of the material. The vaporized metal is deposited on the substrate via mechanical

bonding or magnetic attraction. The process is very similar to the IC fabrication

process, so very high resolutions can be achieved.





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2. TAG PRELIMINARY ARCHITECTURES

In the initial draft of the document, just some architectural considerations about the tag

architecture focusing in the power consumption were addressed. However, such

architecture has a great impact in the whole system architecture, and also in the system

performance. Indeed, the power consumption of the tag directly affects to the detection

range, and also the location accuracy.

This section presents three candidate architectures for the tag that has been discussed

among the project partners. The choice of the architecture has a great impact in the system

performance in terms of power consumption of the tag, the detection range, and also the

location accuracy. For this reason, the final decision of the tag architecture will be

established within tasks T3.4 and T3.5 in coordination with T2.2.

The representation of the architectures within the following sections is functional, with a

very high level of abstraction: Logic_1 and Logic_2 are referred to the digital logic of each

subsystem; however, they will be implemented in the same chip as a single building block,

even if they might be logically independent from each other. The same issue applies for the

Memory blocks, as explained in the following section.

2.1. Tag functionality description

The tags are the second core component of the SELECT system as defined in the Description

of Work [DoW]. The tags shall be attached to the objects to be identified and to be located.

Thus, tag and tagged object will be considered as one unified object. The tags are capable to

communicate with the readers – or with the central unit via the readers – in two widely

independent transmission modes

• the Ultra High Frequency (UHF) mode of standard EPC Class-1 Gen2 [EPC_GEN2], and

• UWB transmissions according to the regulation [FCC02], [IEC05].

Both modes will operate by pure signal backscattering, even though the UHF mode will

operate as passive tag powered up from RF signals, whereas the UWB mode will operate as a

semi-passive tag. Semi-passive therein means that the tag comprises a battery that is not

used to actively transmit or amplify a signal, but the tag requires the energy supply of the

battery for the internal control logic. A (totally) passive tag in the UWB mode is not

considered because the UWB pulses do not comprise enough energy to power on the tag.

The UWB mode is used for location purposes while the UHF mode is use for compatibility

purpose (e.g. to make possible the Identification outside the SELECT system). Therefore, the

UWB functionality may be considered as an extended add-on to the existing RFID

functionalities to allow tag localization and detection range extension. In principle, those

two subsystems are totally independent from each other; however, the possibility to use the

UHF signal to power on the UWB section (as a means of RF energy harvesting) will be

explored during the implementation phase of the Project within task T3.4: Analog front-end

design of WP3.

To avoid the duplication of functionality between the UHF RFID and the UWB, these two

sections share the internal memory structure:





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• A standard EPC memory is provided by the UHF section (Memory_1)

• A memory registry location is provided by the UWB section, mirroring the EPC

memory value of the UHF section (Memory_2)

This way, the EPC memory value can be used as Object ID information for both Identification

and Location functions. Moreover it will be possible to write the tag memory using the UHF

mode only, without the need to implement “write commands” in UWB mode. In addition the

UWB section has a second memory location to store the Tag Spreading Code, used to detect

each Tag in the UWB backscatter link.

In the UWB mode the communication between Reader and Tag will follow the method

described in [Dardari09], whereas the UHF RFID section will operate as state-of-the art RFID

systems, by back-scattering the AM-modulated incoming UHF CW as a PSK-modulated

backscattered signal. Although the presented architecture is a preliminary selection as a

starting point, the final architecture of the tag will be selected within T2.2 and T3.4.

2.2. UWB subsection considerations

Before going through the tag architectures, the UWB section of the tag must be defined in

accordance to the scope of the Project. Two alternatives are presented, both of them

suitable to be included within the tag architectures description in sections 2.3, 2.4 and 2.5.

2.2.1. Option 1: active UWB

The first option is based in an active UWB front-end architecture, as shown in Figure 20. The

signal enters the UWB front-end and is processed and downconverted by the RX front-end,

which is usually the most power consuming building block in this kind of transceivers

[Razavi05]. Then the signal is analog-to-digital converted and processed by the logic digital

core, which manages the read / write operations with the memory. The transmitter presents

lower complexity, as is composed by a pulse generation and the analog front-end, which

simply consists on an RF amplifier.

RX

front-endADC

TX

front-end

pulse

gen

Logic_2 Memory_2

UWB front-end

Figure 20. UWB tag section option 1: active UWB





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Although this architecture has proven its good performance in of-the-shelf commercial

devices, it is out of the scope of the project as it requires more complex (and costly) tags and

higher energy supply with respect to solution based on semi-passive backscatter

communication.

2.2.2. Option 2: semi-passive UWB

The second option is based in a passive backscatter UWB communication within a semi-

passive tag, as proposed by [Dardari10]. This architecture is much simpler and leaves all the

intelligence to the reader, and hence the power consumption of the tag might be reduced.

As depicted in Figure 21 and being the concept suggested in [Dardari10], the baseband logic

processor modulates the backscatter modulator according to the device ID stored in the

memory, and then the incoming UWB signal is backscattered and demodulated in the

reader.

Figure 21. UWB tag section option 2: semi-passive UWB

Although both options are suitable with the architectures presented in the following

sections, the second option is preferred due to its correspondence with the project’s

scope. Based on the system architecture proposed by [Dardari10], the tag’s antenna load is

modulated to perform 2-PAM for both identification and localization, as depicted in Figure

22.

Figure 22. Scheme of the tag (2-PAM case)





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This scheme presents significant advantages with regard to other UWB communication

schemes:

• Simple architecture for the tag, the complexity is concentrated at the reader side

• No RF front-end needed, energy needed only for the baseband logic circuitry (longer

life time)

• It is easily integrable with the UHF RFID section

• The architecture patent license [Dardari09] is hold by the SELECT consortium

2.3. First tag architecture (A_1)

The first candidate architecture for tag implementation is depicted in Figure 23. The two

subsystems (UHF and UWB) are totally independent from each other. UHF RFID component

is fully passive, by harvesting the required power supply from the RF electromagnetic signal

in the UHF band. The UWB section is continuously powered on. Depending on the

modulating frequency, such power consumption might be too high, as an analog-generated

clock signal shall be also provided to the digital baseband processor.

Figure 23. Tag architecture A_1

In this case, a diplexer has been used as tag to antenna interface only for a better

comprehension of the drawing. Other interfaces for dual UHF / UWB antennas will be

investigated within T3.3: On-tag antenna design.

2.4. Second tag architecture (A_2)

The second architecture (A_2) represents an improvement of A_1 with regard to the power

consumption. In this case, the UWB section is not always powered-on, but only the digital

logic in a stand-by mode of operation. A UHF signal is used in this case as a wake-up signal,

in charge of powering up the UWB section, as will be explained in sections 2.4.1 and 2.4.2.





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2.4.1. A_2 with UHF wake-up (A_2.1)

In this architecture, part of the RFID front-end is used as a wake-up receiver, as shown in the

simplified architecture shown in Figure 24. For example, if there is an unmodulated UHF CW

signal, the UHF RFID manages to convert such signal into power supply available for all RFID

circuits. However, such signal can be utilised as a wake-up signal once it is higher that a

preset threshold.

This way, the tag would be most of the time in a sleep mode, with no power consumption at

all. Once a UHF interrogating signal is detected, a wake-up signal is generated by the RFID

front-end, powering up the tag battery. Then the battery switches-on the baseband logic

circuitry, which is in charge of connecting both the logic memory and the UWB front-end.

Since the energy required for signalling is less than the energy required to supply power to

the tag, it is expected that the wake-up range (distance) should not be a limiting factor. This

aspect will be investigated in T2.2.

The power-off of the system could be performed in different ways:

• Once the UHF signal is lower than the preset threshold again, a power-down signal is

generated by the RFID front-end.

• The battery is switched down after a preset time.

Figure 24. Tag architecture A_2.1

The main drawback of this architecture is that, as an UHF CW is used to automatically

generate the wake-up signal, and hence no information is processed within the wake-up

process. This way, false wake-ups might be produced among the population of tags when

other UHF signals are present in the environment with power enough to generate wake-up

signals.

It is also impossible with this architecture to perform selective wake-ups among a population

of tags, as all tags receiving the UHF signal with power enough to exceed the preset

threshold would be woken-up. For example, SELECT tags might be woken-up in the presence

of an RFID reader interrogating other population of tags in the vicinity. However, this aspect





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should not represent a critical issue because tag selection is performed by the reader

through the analysis of the UWB backscattered signal.

It must also be noticed that in this case, both sections (RFID and UWB) are not independent

from each other, as an UHF signal is needed for the UWB wake-up. Therefore, at least some

kind of simple UHF readers, or better, UHF CW transmitters, must be included in the system

architecture. It has to be remarked that in T2.2 the possibility to use the wake-up signal to

provide code phase synchronization is under investigation. The purpose is to drastically

reduce the time required to acquire the spreading code and hence to meet the project

requirements in terms of latency and number of tags.

2.4.2. A_2 with RFID wake-up (A_2.2)

In order to avoid the main limitations described in section 2.4.1 for the architecture A_2.1,

the architecture A_2.2 is considered and depicted in Figure 25. In this case, a modulated UHF

CW is provided by the RFID reader. This signal is demodulated and processed by the RFID

processor, and once it is checked as a positive wake-up signal, it is used to power-on the tag

battery, and the same process described in section 2.4.1 for the A_2.1 architecture is

followed. In Figure 25 a red arrow coming from the Logic_1 block to the wake-up block

appears in addition to the A_2.1 architecture (Figure 24), representing the verification

process in order to distinguish between true or false wake-ups.

Figure 25. Tag architecture A_2.2

Although the power consumption of the tag in this case is reduced with regard to the A_2.1

architecture as no false wake-ups are produced, the overall system architecture is more

complex in this case. As a modulated wake-up signal must be provided by the RFID reader to

power on the UWB section of the tag, RFID readers must be included in the SELECT system

just for wake-up purposes.





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2.5. Third tag architecture (A_3)

Finally, a third architecture has been considered for the tag. As depicted in Figure 26, the

A_3 architecture also exploits the wake-up principle to save energy, but in this case the UWB

section incorporates an ultra-low-power wake-up receiver. Therefore, once again, both

sections (UHF and UWB) are independent from each other. Once a wake-up signal is

received by the ultra-low-power receiver and verified by the Logic_2 block (which is always

powered on, as well as the wake-up receiver), both the UWB front-end and memory are

activated.

UWB

backscatter

modulator

Logic_1

Logic_2

Memory_1

Memory_2

BATTERY

Ultra-low-power

wake-up receiver

RFID

front-end

UHF /UWB

antenna

Figure 26. Tag architecture A_3

However, this architecture adds more complexity to the system, because of the fact that the

wake-up protocol (from reader to tag) should be carefully defined. As both the logic circuitry

and wake-up receiver of the UWB section shall be always on, their inclusion in the tag

architecture does not seem to mean a significant reduction of the power consumption

regarding to the A_1 architecture. In addition, further complexity in the overall system is

introduced in both the tag (ultra-low-power receiver) and reader (wake-up protocol to be

defined). It is also expected that in this case the wake-up range is less that that achievable in

architecture A_2_1 due to the stronger power emission limitations in the UWB band.

2.6. Preliminary decision about tag architecture

With the above considerations, it might be concluded that the better candidate for the tag

implementation from a “green” point of view (i.e. lower power consumption) is the

architecture A_2.2. With this architecture, the tag is always off (no power consumption at

all) and the UWB section is only activated when a positive (and selective) wake-up signal is

produced.





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However, one thing is clear: the use of a battery is necessary as no energy can be harvested

from UWB electromagnetic waves. On the other hand, a minimum tag lifetime (i.e. battery

lifetime) of 2 years must be guaranteed (see System Requirements in D1.2). For these

reasons, it has been agreed among the partners of the Project to select, as a starting point,

the A_1 architecture as the candidate for the SELECT tags.

The definitive selection of the tag architecture will take place within the early beginning of

both T3.4 and T3.5 and after performance evaluations under investigation in T.2.2, by taking

into consideration the following issues:

• First of all, a rough estimation about the available average power shall be provided,

taking into account a candidate battery and a lifetime of 2 years, in continuous

operation.

• Secondly, a power budget of the UWB section shall be calculated. For this purpose, a

close cooperation with WP2 is necessary.

• Code synchronization constraints

• If A_1 can cope with the above issues, then this architecture will be finally

implemented in the tag.

• If not, both A_2_1 and A2_2 are left as backup candidates.





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3. IC TECHNOLOGY CHOICE

To achieve a cost-efficient solutions optimized for low energy operation, compatibility, and

availability, a standard CMOS technology will be utilized to implement the tag. The

technology node and foundry have been selected based on a careful evaluation considering

other critical aspects like device leakage, bandwidth, cost, and physical size. Proximity and

economic criterions have been analyzed to select any foundry with an MPW (Multi-Project

Wafer) service available. The comparison between different technology vendors has taken

into account the following items:

• Availability of RF-options, Schottky diodes or zero-threshold transistors for the analog

circuits

• Low power digital circuitry (for a complete SoC solution)

• EEPROM available as standard cell

• High density capacitors for the power management unit

3.1. Criterions

The criterions for selecting the IC technology include several aspects related to the

specifications and needs in the different phases of the project, but also to the foreseen

commercial utilization of the project results after project termination. The IC technology

choice will be made according to a decision flow including a number of steps and selections

ending up with a specific foundry/technology/node. For each step associated criterions will

be evaluated and weighted according to its importance and impact on the project progress

and post project commercialization of results. The different groups of criterions and their

estimated importance are described subsections below.

3.1.1. Technical criterions

The technical criterions will have a direct impact on the fulfilment of the specifications of the

RFID tag. The selected tag architecture, energy source, TX/RX frequency etc. will inherently

define certain technical criterions that must be met in order to meet the defined goals. If a

candidate technology fail to comply with critical technical criterions it will not be evaluated

against the other criterions. The following technical criterions defined for the SELECT tag are:

• Performance/bandwidth: The inclusion of UWB technology targeting ETSI

compliance puts strict demands on the maximum achievable speed/performance of

the IC technology. The critical limit will depend on circuit topologies and the selected

UWB-band (3.1 GHz – 5.6 GHz or 6.0 GHz – 8.5 GHz), but for flexibility RF and logic

operation up to 10GHz should be supported.

• RF options: RF options like dedicated active devices, inductors, capacitors etc. must

be available in order to implement UHF/UWB front-end components and power

harvesting circuitry in the tag.





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• Schottky diodes or “Zero threshold” transistors: In order to implement an efficient

voltage multiplier / charge pump in the power harvesting module, Schottky diodes or

zero threshold transistors must be available or possible to approximate using other

devices.

• Low-power digital circuitry: The tag will include a digital control logic module

handling running the protocol and controlling the operation of the tag. Even when

the tag is placed in “sleep-mode”, parts of the control logic must be active. The digital

modules must therefore be optimized with respect to energy efficient operation low

static leakage.

• EEPROM: The instruction set of the tag must be stored even when the tag is not

powered. In addition it should be possible to change the instruction set or tag

configuration “in-circuit”. An EEPROM or working replacement must therefore be

available as a standard cell.

• High density capacitors: To maintain a small size of the tag physical layout and

achieve good performance high density capacitors with sufficient quality must be

available.

3.1.2. Design flow criterions

Regarding to the design flow criterions, the following issues apply for the tag:

• PDK/FDK: A process/foundry development kit with full Front-to-Back (FB) support

must be present. The project will include both custom design of analog/RF blocks and

automated synthesis of digital core cells. Support for sign-off verification with tools

held by WP3 partners must also be available.

• Standard cell libraries: To allow for full sign-off verification and post-layout synthesis

of frequency and power critical blocks, I/O and low-power digital core cells must be

available with full layout view either from the foundry or via a third party supplier

free of charge or to a very limited cost.

3.1.3. Economical criterions

The following economical criterions apply to the tag implementation:

• Prototyping cost: The cost related to circuit prototyping through an MPW service

must be considered to make sure the number of foreseen prototypes can be

fabricated within the budget limits.

• Full mask-set cost (COT): A successful implementation of prototypes within the

project will most likely lead to a commercial utilization after project termination. To

avoid risk and save time-to-market the same technology used in the project should

be used in a commercial product. The full mask-set cost and volume pricing of wafers

must be considered and evaluated to be within acceptable limits with respect to

average selling price in high volumes.





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3.1.4. Availability/Ease of access criterions

Apart from the economical criterions, those related to the availability and the ease-of-access

to the technology must be satisfied:

• MPW service: A Multi-Project Wafer (MPW) service must be available for the

selected process, both for low cost research prototyping (~10-100 samples) and

medium cost commercial prototyping (~100-2000 samples).

• MPW service frequency: The number of available tape-outs per year for a given

process should be reasonable high (2 or more) and evaluated against the risk of

critical delays or excess costs if a targeted tape-out date is not met.

• Second source availability: For redundancy a second source provider of a similar

technology offering the same node should be available. For most standard CMOS

technologies this should not be a problem, but for more sophisticated technologies

this is an issue.

• Local foundry / Broker representation: Most foundries do not allow direct access for

low-volume non-commercial customers. In addition cultural and language barriers

might pose a challenge. For those reasons a regional representative or broker should

be available in Europe. It is also important that this entity has technical expertise and

support personnel. The most commonly used reps/brokers are briefly presented in

the next section.

3.1.5. Existing knowledge/IP criterions

For a more fluent design, the following criterions regarding previous knowledge apply:

• SELECT Partner knowledge: To save time and reduce risk, at least one of the WP3

contributors should have previous experience with the selected technology.

• Existing IP/models: Silicon proven IP blocks that might be partially or fully utilized in

the project will be valuable. Especially with respect to critical analog or RF

(UHF/UWB) front-end components, this will be of great benefit. Developed and

calibrated simulation models will also represent a value for the project.

3.1.6. Environmental / Ethical criterions

Finally, the following environmental and ethical criterions must be satisfied:

• Energy and environment friendly production: The selected foundry/process must

live up to international standards of energy and environmental friendly production

and offer RoHS compliance of the packaged samples.

• Ethical standards: The selected foundry/process must comply with international

ethical standards in terms of a good working environment for the employees and not

using child labour.





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• Energy preserving technology: Give that critical technical specifications are met a

low-power low-leakage technology should be selected. Due to the possible very high

number of tags distributed worldwide each tag should be optimized for preserving

energy.

3.2. Decision steps

The number of available IC technologies is very large, so it is important to first make a coarse

evaluation of criterions where the outcome is more or less given based on an overall

evaluation. The goal of the coarse evaluation is to end up with a very limited number of

candidate technologies which will be compared carefully against all relevant criterions using

a spreadsheet tool including variable weighting.

3.2.1. Semiconductor technology

A number of different semiconductor technologies are available in the market. Most

commonly used are CMOS, SiGe and GaAs. If the demands for high speed and output power

are not dominating the selection, CMOS is usually selected due to its versatility, availability

and low cost. Since the focus in SELECT is on low cost, low-power, small size and the

foreseen operation frequencies are relatively reasonable, only CMOS processes will be

considered for the tag implementation.

3.2.2. Technology node

The selection of a more advanced technology node is a trade-off between increased

processing speeds, reduced power consumption, reduced physical size and long-term

availability on one side and increased cost, reduced analog performance (headroom) and

increased design complexity on the other side. The SELECT tag has a number of technology

driving characteristics like high speed front-end components, demand for small size and low

energy consumption in the digital processing logic and circuitry for energy scavenging.

Among those the UWB front-end will be the speed driving factor. Depending on the

architecture, operation frequency and implementation method chosen, the most interesting

technology nodes will be 130 nm, 90 nm or 65 nm. Among them the 90nm technology is

considered to be a good trade-off between performance and cost. For certain architectures

a 130nm technology would be sufficient, but to allow for flexibility throughout the project

period the 90nm technology node is preferred. Although the volume pricing for this

technology still is quite high compared to older nodes, the price is expected to be reduced as

a result of the general technology development.





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3.2.3. Foundry / MPW provider

There are several foundries offering 90nm CMOS available, but in order to have a local

representative or broker offering technical support and a MPW service, the potential

candidates are reduced to the following:

• IBM – MPW service through Mosis.

• TSMC – MPW service through Europractice and Mosis.

• UMC – MPW service through Europractice.

Among these only TSMC and UMC are available at a minimum cost through the Europractice

mini@sic program for research and academic purposes. The prototyping cost of mini@sic

runs is typically 20% - 25% of the cost associated with regular MPW runs (i.e. 75% to 80%

discount). EU is supporting this program through FP7. A possible drawback with mini@sic

prototyping is that the design size is fixed to 1875 µm x 1875 µm, which may influence on

bond wire length and inductance and aspect ratio of the design. If this poses a problem,

mini@sic might be chosen for the early prototype(s) and a regular MPW for the final

demonstrator. Based on the potential of reduced prototyping cost and local presence in

Europe Europractice will be the preferred MPW provider.

3.2.4. Technology version

Most available 90 nm CMOS technologies come in different versions optimized for different

applications and use. In general low-power/reduced speed, nominal power/nominal speed

and high power/high speed versions are offered. Within each version there are also different

active devices mainly deviating by oxide thickness to allow for flexibility. In general RFID tags

would benefit from using the low-power version, but some specific demands in the SELECT

project might favour a general purpose variant. The outcome of this comparison is not

obvious and the different versions will therefore be compared against all criterions set by

the project.

3.2.5. Specific process /options

For each technology node and version several options may be selected or removed. For

production runs the number of options selected will have significantly impact on the cost.

For prototype runs however, the options are often fixed to satisfy most customers meaning

that the majority of selectable options are included. A list of typical options included in

MPW-shuttles is included in the comparison presented in section 4.3.

3.3. MPW providers

As mentioned in section 3.2.3, Europractice is preferred as MPW provider for SELECT Project.

However, other different alternatives are analyzed in this section.





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3.3.1. CMP

CMP is a service organization in ICs and MEMS for prototyping and low volume production.

Circuits are fabricated for Universities, Research Laboratories and Industrial companies.

Advanced industrial technologies are available in CMOS, BiCMOS, SiGe BiCMOS, P-HEMT E/D

GaAs, etc. CMP distributes and supports several CAD software tools for both Industrial

Companies and Universities. Currently CMP does not offer any 90 nm CMOS process and

has therefore not been considered as a MPW provider within the SELECT project.

3.3.2. Europractice

Europractice was launched by the European Commission (DGIII) in October 1995 to help

companies improve their competitive position in world markets by adopting ASIC, Multi-Chip

Module (MCM) or Microsystems solutions in the products they manufacture. The program

helps to reduce the perceived risks and costs associated with these technologies by offering

potential users a range of services, including initial advice and ongoing support, reduced

entry costs and a clear route to chip manufacture and product supply.

Europractice can also provide users with the training and CAD software required to design

and develop their ASIC, MCM or Microsystems solution. The EUROPRACTICE IC service has

been started in October 1995 and is offered by a consortium of:

• IMEC (Belgium)

o Coordinator

o Academic Support

o Industrial Support

o MPW & Small Volume

• STFC (United Kingdom)

o CAD Support

o Academic Support

• Fraunhofer IIS (Germany)

o Industrial Support

o MPW & Small Volume

The service consists of two main offerings:

• ASIC prototype and small volume turnkey offering for industry and academia offered

by partners IMEC and Fraunhofer IIS

• CAD tools for academia only offered by partner STFC

Europractice offers 90nm CMOS processes from both TSMC and UMC technologies.





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3.3.3. Mosis

MOSIS is a low-cost prototyping and small-volume production service for VLSI circuit

development. Since 1981, MOSIS has fabricated more than 50,000 circuit designs for

commercial firms, government agencies, and research and educational institutions around

the world. MOSIS provides designers with a single interface to the constantly changing

technologies of the semiconductor industry. Mask generation, wafer fabrication, and device

packaging are contracted to leading industry vendors. Mosis is located in US but have

European representative offices and offers 90nm CMOS processes from IBM and TSMC.

3.4. Foundries

3.4.1. IBM

IBM specialty foundry technologies are powering a new generation of mobile devices and

smarter products. Choose from a comprehensive portfolio of analog mixed-signal (AMS)

offerings that includes advanced high-voltage CMOS (HV CMOS), RF CMOS, RF Micro

ElectroMechanical Systems (MEMs), RF SOI and SiGe BiCMOS technologies.

IBM is offering their 90nm CMOS process in different variants through MOSIS.

3.4.2. ST

STMicroelectronics is one of the world’s largest semiconductor companies with net revenues

of US$ 8.51 billion in 2009 and US$7.51 billion in the first nine months of 2010. Offering one

of the industry’s broadest product portfolios, ST serves customers across the spectrum of

electronics applications with innovative semiconductor solutions by leveraging its vast array

of technologies, design expertise and combination of intellectual property portfolio,

strategic partnerships and manufacturing strength.

The Company has particular strengths in Multimedia, Power, Connectivity and Sensing

technologies and its sales, including wireless business conducted via ST-Ericsson, the 50/50

Joint Venture with Ericsson, are well balanced among the industry’s major sectors: Telecom

(31%), Automotive (14%), Consumer (13%), Computer (13%), Industrial (7%) and Distribution

(22%).

ST has a strong focus on delivering solutions that reduce energy consumption at the point of

use in domestic and industrial applications; all aspects of security and data protection; and a

growing presence in the emerging advanced healthcare market. To provide its customers

with an independent, secure and cost-effective manufacturing machine, ST operates a

worldwide network of front-end (wafer fabrication) and back-end (assembly and test and

packaging) plants. ST’s principal wafer fabs are presently located in Agrate Brianza and

Catania (Italy), Crolles, Rousset and Tours (France), and Singapore. The wafer fabs are

complemented by world-class assembly-and-test facilities located in China, Malaysia, Malta,





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Morocco and Singapore. ST has a 90nm CMOS process, but are currently not offering any

MPW-service. They are therefore not included in the candidate technologies.

3.4.3. TSMC

Established in 1987, TSMC is the world's first dedicated semiconductor foundry. As the

founder and a leader of the Dedicated IC Foundry segment, TSMC has built its reputation by

offering advanced and "More-than-Moore" wafer production processes and unparalleled

manufacturing efficiency. From its inception, TSMC has consistently offered the foundry

segment's leading technologies and TSMC COMPATIBLE® design services.

TSMC has consistently experienced strong growth by building solid partnerships with its

customers, large and small. IC suppliers from around the world trust TSMC with their

manufacturing needs, thanks to its unique integration of cutting-edge process technologies,

pioneering design services, manufacturing productivity and product quality.

The company's total managed capacity is expected to reach over 11.3 million eight-inch

equivalent wafers in 2010. TSMC operates two advanced 12-inch wafer fabs, four eight-inch

wafer fabs, and one six-inch wafer fab in Taiwan. One additional 12-in Fab is under

construction and is expected to go on line in 2011. TSMC also manages two eight-inch fabs

at wholly owned subsidiaries: WaferTech in the United States and TSMC China Company

Limited. TSMC also obtains eight-inch wafer capacity from other companies in which the

Company has an equity interest.

To better manage its long-term strategic growth, TSMC is investing in lighting and solar

energy related-industries. With differentiated technology offerings and unique value

propositions, TSMC will aggressively pursue new opportunities in these fields.

3.4.4. UMC

UMC is a leading global semiconductor foundry that provides advanced technology and

manufacturing services for applications spanning every major sector of the IC industry.

Founded in 1980 as Taiwan's first semiconductor company, UMC is the world's foundry

technology leader, consistently first-to-market on advanced processes and possessing the

highest number of semiconductor patents in the industry. UMC's customer-driven foundry

solutions enable chip designers to leverage the strength of the company's leading-edge

processes, which include production-proven 65nm, 45/40nm, mixed signal/RFCMOS, and a

wide range of specialty technologies. The company employs approximately 12,000 people

worldwide and has an extensive network of service offices in Taiwan, Japan, Singapore,

Europe, and the United States to meet the needs of its global clientele.





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4. CMOS 90 nm TECHNOLOGY ASSESSMENT

The voltage multiplier is a critical element in any RFID Front End architecture, as its efficiency

plays a key role with regard to the conversion of the RF incoming signal in available power

supply for the front end. Such efficiency is directly related to the threshold of the voltage

multiplier diodes [Karthaus03]. Therefore, a previous step before starting the design of the

analog front end is to identify the characteristics of the needed components offered by the

technology.

The area of the voltage multiplier is one of the biggest restrictions in the design; accordingly

the minimum number of components should be used in the chip. Moreover, the passive

elements like resistors and capacitors occupy a large die area, so the number of passive

elements or at least its area should be minimized.

Due to the critical area limitation to reduce implementation costs, a study of the different

available elements in the technology library is going to be done within this subsection.

Particularly the I-V characteristics of different diodes and transistors and the impedances of

different capacitors are going to be checked. The objective is to obtain the best

performance of diodes, transistors and capacitors with the minimum area as possible. A

detailed study has been made using the UMC 90nm SP/General purpose technology. In

general the conclusions and results will be very similar to what to expect from another

foundry/process given that the technology node and process version are the same. For that

reason simulations and analyses on the alternative technologies from TSMC have only been

performed for the components/cases that were found to be the optimal choices for UMC.

4.1. UMC technology analysis

This subsection presents a detailed assessment of the UMC 90 nm General Purpose

technology.

4.1.1. Diode selection

The output voltage of the multiplier circuit depends on the forward (threshold) voltage of its

diodes. When the threshold voltage of the diodes is lower, the output voltage of the

multiplier circuit is higher

[Eq. 4]

where N is the number of circuit stages. Consequently, low threshold voltage components

are desired. UMC 90 nm technology library offers different types of diodes and transistors.

Therefore, it is interesting to study the different threshold voltages (Vth) for different diode

currents and also to observe the curve. Besides, in the annexes of the project

the whole table of the different threshold voltages (Vth) for different diode currents is

presented.

The simulated circuits are shown in the following figure:





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Figure 27. Diode and transistor schematics used for its characterization

A DC analysis has been done in order to know which diode or transistor performs better for

the voltage multiplier. Due to this particular analysis the threshold voltage (Vth) and the

serial resistance (by observing the Vdc vs Idiode curve) can be obtained. All the different diodes

and transistors have been analyzed with their default sizes, given by the UMC 90 nm library

(only the four available triple well transistors have not been studied due to their complexity).

As it can be detected in the curves, there are no Schottky diodes in this particular technology.

All diodes belonging to this technology have a high turn on voltage, they need at least 0.6 V

as input voltage to operate properly.

Table 8 shows the different diodes offered by the technology that have been simulated:

Table 8. Available diodes in UMC 90 nm and their descriptions

Diode type Description

DION Twin well diode (N+ to PWell)

DIOP Twin well diode (P+ to NWell)

DIONW Twin well diode (NWell to PSub)

DIODN Triple well diode (N+ to Buried PWell)

DIODP Triple well diode (Buried PWell to Deep NWell)

DIODNW Triple well diode (Deep NWell to PSub)





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Figure 28. The I-V characteristics of diodes in UMC 90 nm (default sizes)

Figure 28 shows that there are not Schottky diodes in this particular technology (the

minimum threshold voltage is around 0.6 V. As it can be observed in the graph, the lower

forward voltage and lower serial resistance diodes are the triple well diodes, specially the N

to PSub diodes (DIODN and DIODNW). The main difference between triple well and twin well

is the substrate isolation, triple well components are more isolated, so the performance is

better for these components. On the other hand, the mobility of the majority carriers is

higher in N regions, so DIODN and DIODNW have a better performance than DIODP.

shows the different transistors offered by the technology that have been simulated. The N

and P prefixes are used for either n-type or p-type transistors respectively.

Table 9. Available transistors in UMC 90 nm and their descriptions

Transistor type Description

10_SP Standard Performance (1.0 V)

10_SPHVT Standard Performance High Threshold (1.0 V)

10_SPLVT Standard Performance Low Threshold (1.0 V)

10_SPNVT Standard Performance Normal Threshold (1.0 V)

10_SPRF Standard Performance RF (1.0 V)

12_LL Low Leakage (1.2 V)

12_LLHVT Low Leakage High Threshold (1.2 V)

12_LLLVT Low Leakage Low Threshold (1.2 V)





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Transistor type Description

12_LLNVT Low Leakage Normal Threshold (1.2 V)

12_LLLVTRF Low Leakage Low Threshold RF (1.2 V)

12_LLRF Low Leakage RF (1.2 V)

25 IO device (2.5 V)

25_NVT IO device Normal Threshold (2.5 V)

25_RF IO device RF (2.5 V)

33_GOX52 -

The following figures show the performance of transistors operating as diodes. As will be

demonstrated, the available RF transistors have relatively a high forward voltage (with their

default sizes), so a deeper study is needed. Specifically, the lower forward voltage RF

transistors in this technology are the N_10_SPRF (n-type) and the P_10_SPRF (p-type). It has

to be mentioned that the four available triple well transistors have not been analyzed due to

their complexity, but they are desirable for certain RF circuits like LNA, VCO and varactors.





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Figure 29. The I-V characteristics of diode-connected transistors in UMC 90 nm (default sizes)





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Figure 30. The I-V characteristics (Zoom) of diode-connected transistors in UMC 90 nm (default sizes)





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Figure 31. The I-V characteristics of diode-connected RF transistors in UMC 90 nm (default sizes)

Figure 32. The I-V characteristics (Zoom) of diode-connected RF transistors in UMC 90 nm (default sizes)





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Figure 33. for different currents of diode-connected RF transistors in UMC 90 nm (default sizes)

As the P_10_SPRF transistor has been proved to be the most suitable candidate for the front

end implementation in the voltage multiplication stage, a deeper study of its I-V

characteristics (changing its width and length) has been carried out. By changing its width

and length a low threshold voltage transistor has been obtained, and also a lower serial

resistance (better I-V characteristics) has been achieved. Furthermore, a comparative study

between the N_10_SPRF transistor and the P_10_SPRF transistor has been performed. Both

RF transistors present the following characteristics:

• Minimum gate length: 80 nm

• Maximum gate length: 360 nm

• Minimum gate width: 500 nm

• Maximum gate width: 8 µm

• Minimum number of fingers: 2

• Maximum number of fingers: 32





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Before starting to modify the transistor length, width and number of fingers, it is important

to anticipate the logical behavior of a transistor which undergoes this modification. To

understand the influence of the variations it is critical to know the physical structure of a

transistor.

Figure 34. Cross section of an idealized n-channel MOS transistor and the corresponding symbol [Enz95]

Figure 35. 3D Cross section of an idealized NMOS transistor

As it can be observed in the figures, an increase of the channel length causes also a rise of

the channel resistance. Due to this increase of the channel resistance, a larger threshold

voltage to provoke current in the channel is needed. On the other hand, an increase of the

channel width (and or an increase of the number of fingers) will cause a decrease of the

channel resistance and also a decrease of the needed forward voltage. This reasoning is

supported by the practical analysis showed within the next figures.





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Figure 36. Vth for different currents of diode-connected N_10_SPRF transistor varying its length

(W=500nm&F=2)

Figure 37. Vth for different currents of diode-connected P_10_SPRF transistor varying its length

(W=500nm&F=2)

The threshold voltage increases proportionally with the transistor length. This increment

becomes more significant for higher currents, so the lowest transistor length is desired.





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Figure 38. Vth for different currents of diode-connected N_10_SPRF transistor varying its width

(L=80nm&F=2)

Figure 39. Vth for different currents of diode-connected P_10_SPRF transistor varying its width (L=80nm&F=2)

The forward voltage of the transistor decreases when its width increases. Particularly the

most substantial reductions take place for high currents through the transistor.





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Figure 40. Vth for different currents of diode-connected N_10_SPRF transistor varying its number of fingers

(W=8um&L=80nm)

Figure 41. Vth for different currents of diode-connected N_10_SPRF transistor varying its number of fingers

(W=8um&L=80nm)

A variation of the number of fingers is simply a variation of the width, so the forward voltage

of the transistor decreases when its number of fingers increases.





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Figure 42. Vth for different currents of diode-connected N_10_SPRF and P_10_SPRF transistors

(W=8um&L=80nm&F=32)

Figure 43. I (A) vs Vdc (V) of diode-connected N_10_SPRF and P_10_SPRF transistors

As conclusion it can be observed that the P_10_SPRF has lower forward voltage for low

currents but it has also a higher dynamic resistance (less current through PMOS transistor

for higher values of input voltage). This is due to the higher channel resistance of the PMOS

(remember that in a NMOS transistor the predominant carriers are the electrons). In

addition, the variation of the forward voltages of the transistors with their lengths, widths

and number of fingers has been studied. As it has been demonstrated, the threshold voltage

increases when the length of the channel increases. Otherwise when the width (or the





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number of fingers) of the transistor increases, the forward voltage decreases. These

variations are logical in transistors.

Therefore, and despite the lack of Schottky diodes in the selected technology, P_10_SPRF

represents a suitable device to be implemented in the analog front-end within the voltage

multiplication stage due its low threshold voltage performance.

4.1.2. Capacitor selection

In microelectronics, small sizes are always desired to reduce the cost (and form factor) of the

circuits. Particularly, in this project, low series resistance values are desirable to obtain a

better power conversion efficiency (PCE) of the voltage multiplier. Therefore, high quality

factors are desirable for the capacitors in the front end, and hence a preliminary study has

been carried out to those capacitors offered by the technology.

The technology library allows the use of different capacitors, but basically they are divided

into two main types: MIMCAPS (Metal Insulator Metal capacitors) and MOMCAPS (Metal

Oxide Metal capacitors). There are also NMOS capacitors; such capacitors have higher

density, i.e. they can achieve higher capacitances than MIM or MOM capacitors for same

area. However, they have a non linear characteristic and have a much lower quality factor,

and therefore have not been included in the study.

For all the analyzed capacitors, its capacitance, size and resistance values have been

compared. It is also important to emphasize that for this particular study only RF capacitors

have been used as they are key components within the RF stages of the analog front end.

4.1.2.1. Type of capacitors

Table 10 shows the different capacitors in UMC 90 nm and its simulated characteristics:

Table 10. Comparison of different capacitors in UMC 90 nm (default sizes)

Capacitor (default size) C [fF] W [µm] L [µm] R [Ω] X [Ω] Q (@868 MHz)

MIMCAPS_20F_MM 50 5 5 0,03 -3672 128977,87

MIMCAPS_20F_RFKF (A) 50 5 5 6,94 -3672 529,41

MIMCAPS_20FNW_RFKF (B) 50 5 5 30,52 -1346 44,10

MOMCAPS_Array_VP3_RFVCL (C) 37 5 13 466,00 -2142 4,60

MOMCAPS_Array_VP4_RFVCL (D) 27 5 13 554,20 -2453 4,43

MOMCAPS_AS_MMKF 50 2,38 10,00 0,03 -3690 128975,88

MOMCAPS_ASMESH_MMKF 50 1,70 10,00 0,00 -150 129026,70

MOMCAPS_SY_MMKF 41 1,96 10,00 0,03 -4212 128965,09

MOMCAPS_SYMESH_MMKF 42 1,40 10,00 0,00 -170 129081,25





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The MOM (Metal-Oxide-Metal) capacitor is an inter-digitated multi-finger capacitor formed

by multiple metal layers (M1 to M6) to have a higher capacitance density, i.e. higher

capacitance per area. The MIM (Metal-Insulator-Metal) capacitor is a parallel-plate capacitor

formed by two planes of metal (M6 and M7) separated by a very thin dielectric. In

comparison with MOM capacitors, MIM capacitors need an extra mask and photo-steps. As

a result, bigger area is needed for MOMs for the same capacitance value (as it can be

observed in Table 10).

In order to have a quick view of the different types of RF capacitors and their different

resistance, the quality factor of the capacitors is presented in the next figure:

Figure 44. Quality factor for different RF capacitors in UMC 90 nm (default sizes) at 868 MHz

As it can be seen in both Table 10 and Figure 44, the best RF capacitor in terms of quality

factor is the MIMCAPS_20F_RFKF due to its low resistance. Therefore, MIMCAPS_20F_RFKF

are going to be used to analyze the influence of the size.

4.1.2.2. Size influence

The values of the output voltage, the PCE (Power Conversion Efficiency) and the input

impedance of the front end depend on the sizes of the capacitors of the voltage multiplier

[Karthaus03]. As another preliminary analysis, the variation of the impedance (and therefore

capacitance) and quality factor of the capacitor depending on its size will be studied.

It must be taken into account that the ratio between width and length is bounded in the

MIMCAPS by the technology models. Particularly, the ratio must satisfy the following

expression





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In addition, the capacitor has the following characteristics:

• Minimum width: 5 µm

• Maximum width: 100 µm

• Minimum length: 5 µm

• Maximum length: 100 µm

Table 11. Comparison of different MIMCAPS_20F_RFKF at 868 MHz

Capacitor MIMCAPS_20F_RFKF

C [fF] W [µm] L [µm] R [Ω] X [Ω] Q (@868 MHz)

(A) 50 5 5 6,94 -3672 529,41

(B) 200 10 10 3,47 -925 266,96

(C) 500 16 16 2,76 -362,3 131,27

(D) 1000 23 23 2,53 -175,6 69,52

(E) 2000 32 32 2,42 -90,72 37,47

(F) 5000 50 50 2,35 -37,09 15,76

Figure 45. Quality factor for different MIMACPS_20F_RFKF at 868 MHz

As it can be observed in Table 11, the impedance (Z = R + jX) decreases when the capacitance

value increases. Also the imaginary part decreases faster than the real part of the impedance,

so the quality factor of the capacitor decreases when the capacitance value increases.





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4.2. TSMC 90 nm technology analysis

The UMC and TSMC 90nm technologies are in general very similar in terms of technical

performance, available devices and process options. Due to very strict NDA’s very limited

information may be disclosed. As a result this subsection is based on the results from the

previous subsection focusing on the devices found to be optimal in the UMC technology. In

addition some measured results showing the capabilities in terms of performance are

included.

4.2.1. Diode selection

The UMC technology analysis concluded that the PMOS RF transistor was the optimum

choice as a replacement for the Schottky diode not available in this technology. Based on the

test bench illustrated in Figure 27, the corresponding PMOS RF transistor in the TSMC 90nm

process was simulated for both the general purpose (G) and the low power (LP) process

variants. By comparing the results in Figure 46 with the corresponding results from the UMC

SP90 technology (Figure 28), they are very similar, and would serve the same purpose as a

replacement for the Schottky diode.

Figure 46. I (A) vs Vdc (V) of diode-connected N and P RF transistors in CRN90G





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Figure 47. I (A) vs Vdc (V) of diode-connected N and P RF transistors in CRN90LP

The same analysis was performed for the TSMC CRN90LP process. As can be seen from

Figure 47, the threshold voltages in the LP process variant are higher for both the PMOS and

the NMOS transistors. The LP process is therefore not that suited to obtain good

replacements for Schottky diodes. The different may be compensated for by increasing the

transistor widths, but at the cost of increased area. This result fits well with the similar

analysis from the UMC LL process.

4.2.2. Capacitor selection

The same range of different capacitors presented for the UMC technology is also available in

the corresponding TSMC technology. Based on the conclusions from the previous

subsection, the corresponding MIMCAP capacitor was simulated and analyzed for the TSMC

process. A summary of the results are included in the Table 12 below. As can be observed

the quality factor is very similar to that of the UMC technology.

Table 12. TSMC capacitor Q-value

Capacitor (default size) C [fF] W [µm] L [µm] R [Ω] X [Ω] Q (@868 MHz)

MIMCAP_UM_1.5fF 41.9 5 5 6.415 4486.5 699.38

4.2.3. UWB front-end components

The most demanding components in terms of processing speed and performance are the

UWB front-end modules. Bandwidths approaching 10GHz may be required, and the 90nm





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technology selected must offer the required speed. At such high frequencies, the simulator

models are not very precise and even very small parasitic components may change the

actual performance of the circuits. It is not uncommon to observe significant differences

between simulated and measured results. The SELECT partners have previous experience

and silicon proven IP confirming that the 90nm CMOS technology offers the required

processing speed. Figure 48 and Figure 49 below shows the time- and frequency domain

representation of the measured output signal from a UWB pulse generator centred at 5GHz

still with significant energy at 10GHz.

Figure 48. Measured output signal from a 5GHz UWB pulse generator implemented in 90nm CMOS

Figure 49. Measured frequency spectrum of a 5GHz UWB pulse generator implemented in 90nm CMOS





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To support the expectations that the 90nm CMOS technology may also be used to

implement UWB front-end components in the high-band from 8.0 GHz to 8.5 GHz the

measured results from a previously implemented high-band pulse generator are illustrated

in Figure 50 and Figure 51.

Figure 50. Measured output signal from a 6.0 GHz 8.5 GHz UWB pulse generator implemented in 90nm CMOS

Figure 51. Measured frequency spectrum of a 6.0 GHz to 8.5 GHz UWB pulse generator implemented in 90nm

CMOS





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4.3. Detailed technology comparison

Based on the criterions and decision steps presented above, a detailed comparison of the

candidate 90nm technologies from UMC and TSMC have been made. Due to strict NDA’s

only information that is publically available is presented in this document. Still the

underlying examination and analysis have included also information that cannot be disclosed.

The overall conclusion in terms of technical criterions is that the candidate technologies are

very similar. The only difference of importance is that the TSMC technology seems to offer

somewhat higher speed which may be useful for the UWB front-end. Both technologies

satisfy the critical criterions (Triple well, RF-options, Schottky replacement, low power digital

circuitry). As a result both candidates may be selected from a technical point of view.

When it comes to more logistics related criterions the differences are more significant. The

availability of the TSMC technology is better (12 runs/year vs. 3 runs per year for UMC) and

the number of samples delivered with each prototype run is higher. For the low-cost

mini@sic option TSMC guarantees 100 samples while UMC guarantees 45 samples. TSMC

also offers a larger range of foundry IP blocks.

Errore. L'origine riferimento non è stata trovata. below summarizes the most important

criterions considered. Both the general purpose and low power process versions are

included for both candidates and as can be observed the low power versions offer lower

speed. Since the UWB low-band from 3.1 GHz to 4.8 GHz has been selected for the project

prototypes this should however not pose any problem. Another issue is the lack of optimal

low-threshold diode replacements for the low-power version. This may however be

compensated by increasing the device width at the cost of an area penalty, and should thus

be possible to mitigate. For an RFID application the low power version would be the natural

choice. The process is optimized for low-energy applications and has a reduced device

leakage. Furthermore the availability is expected to be better, at least in the long term.

By comparing the parameters listed in Table 6, the TSMC technology performs somewhat

better and also has a better availability and a higher number of samples provided. The

higher number of samples is useful especially when setting up demonstrators possibly at

several locations where the number of nodes can be high. It is also important to take into

account that some samples might not be functional. The 45 samples offered from UMC

might therefore be marginal. The number of prototyping runs offered from TSMC per year is

also significantly higher than for UMC, which is beneficial to avoid delay if a tape-out

deadline should not be met for different reasons. The conclusion is therefore to rank TSMC

above UMC. Furthermore the low-power process variant is selected due to the energy saving

capabilities and possibly better long-term availability.





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Table 13. Detailed comparison between UMC and TSMC 90nm CMOS technologies





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Based on previous experiences from dealing with foundries, there is always a chance that

the foundry denies access to IP-libraries and other support critical for the project activities.

In order to allow for distribution of IC-modules (Even for partner IP) between the partners

active in WP3 an NDA between the partners, Europractice and the foundry must be

approved and signed. In some cases this might be difficult and time consuming. Furthermore

to reduce the risk in the project a second source must be available. As a result processes

should be initiated to get access to both foundries/technologies at an early stage in the

project.

A table that summarizes the conclusion of the technology selection is included below.

Table 14. Technology selection ranking

Rank Technology Supplier Foundry Node Version

1 CMOS Europractice TSMC 90nm LP

2 CMOS Europractice TSMC 90nm GP

3 CMOS Europractice UMC 90nm LL

4 CMOS Europractice UMC 90nm SP





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5. CONCLUSIONS AND FUTURE WORK

The conclusions extracted from all the issues analyzed within this deliverable are

summarized in section 5.1. The next steps derived from this work to cope with the project

work flow are also summarized in section 5.2.

5.1. CONCLUSIONS

5.1.1. Low power issues

Regarding to the low power issues analyzed through section 1.1, the following conclusions

have extracted:

• Some low-power issues and techniques have been analyzed in this document, due to

the fact that they are a key aspect for SELECT project tag’s “green” approach: the lower

the tag’s power consumption, the higher the tag’s lifetime. Therefore, less waste is

generated due to a lower tag turnaround from market introduction up to device

disposal.

• The reduction of the supply voltage has proven to represent a good approach to reduce

overall power consumption. Due to the fact that different subcircuits might require

different VDD levels, multi-VDD is the optimum technique to cope with the supply

requirements of all the circuits within the tag and will be used in the electronic design of

tag subsystems.

• From a “greener” approach, several state-of-the-art technologies related to energy

harvesting capabilities have been analyzed as a means of autonomous power supply for

the tag. Due to the environment where tags will operate within SELECT’s scope, it has

been concluded that RF UHF radiation is the most reliable means of energy scavenging

source for the tag. Solar, vibration and thermal energy sources have been discarded as

no significant energy is available within the project’s scenario.

• For the correct performance of the electronic circuits, some means of voltage regulation

is required. In addition, some means of level shifting from the voltage available from the

battery (or RF-scavenged) is required to adequate the voltage supplies required by the

different circuits. Different regulation techniques have been analyzed in this document.

It can be concluded that the final choice in the tag implementation will depend on the

required voltage and power range. These parameters will be addressed in the future, and

thus a decision in this regard cannot be set in this moment.

• In order to use transistors with low threshold voltage to obtain high-speed operation and

to reduce stand-by current in the off state, it has been concluded that some means to

switch on/off different circuits of the tag during its operation are needed. After

analyzing some state-of-the-art approaches, it is concluded that the specific strategy

cannot be set at this stage of the project, as the tag’s subsystems and operation modes

are not defined yet.

• As RF energy scavenging will be used for the UHF section of the tags, it is derived that

energy storage capacitance is necessary. As the most cost (and form-factor) effective





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approach is to implement such capacitance on-chip, high density capacitors are

necessary to be provided by the CMOS technology used for IC fabrication.

5.1.2. Use of batteries

Although they might be seen as no-environmentally friendly devices, batteries are necessary

to semi-passively power supply part of the tag’s subsystems. After reviewing the

considerations of the use of batteries faced in section 1.2, the following conclusions have

been derived:

• As low-cost ultra low-power battery-assisted semi-passive tags will be designed, a

decision about the type of battery is necessary: primary (non-rechargeable) vs.

secondary (rechargeable). As the current demand of the tag will be low or moderate and

it will be inoperative for long time periods, a primary-type battery will be implemented

in the tag. In addition, primary batteries are cheaper and their self-discharge time is

lower than this for their secondary counterparts.

• Organic batteries have appeared to be the best choice with regard to an

environmentally friendly point of view. However, they are not present in the market yet.

Therefore, they cannot be used (at the moment) for the tags.

• Carbon-Zinc batteries also represent suitable candidates for the tag, as they are cheap

and environmentally friendly. However, they present a short self-discharge time (lower

than the 2 year lifespan preferred for SELECT tags), and thus they cannot be used too for

the tags.

• Despite the fact that the previous technologies are rejected for the tag at this stage of

the project and they will not be used for the prototypes, they might suppose a more

reliable and mature technologies in a near future. Therefore, some additional

considerations about their use are necessary in the last phase of the project, when the

issues related to the exploitation of the project outcomes will be analyzed.

• At least for the tags prototypes, it has been concluded that the Lithium battery

represents the best choice, due to the following reasons:

o They show a good performance against temperature variations

o Their low discharge rate means longer battery life, limited by the power

consumption of the tag and not by the shelf life of the battery

o Their high energy density and sizeability allow implementing low-form factor

batteries for drain currents in the range of µA at a reasonable cost. For a

battery volume similar to a credit card’s, the expected battery life for lithium

is greater than 4 years.

o Their output voltage (3 V) reduces the power management complexity for the

access to the logic memory, i.e. writing operations.

5.1.3. Tag architecture

The tag architecture is key aspect related to the operation range, as it directly affects its

power consumption. It is also a crucial issue as it defines the overall system architecture.

Two different sections must coexist within the tag: the UHF section for tag ID and memory





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accessing, and the UWB section for tag localization and range extension. This document has

reported in section 2 the discussion faced by the consortium members in the Second Project

Meeting held in Ljubljana, on January 2011. The conclusions are summarized below:

• The use of the battery is necessary to power the UWB section, not to actively amplify

the transmitted signal, but for power supply the electronic control circuits necessary to

perform passive UWB backscattering.

• As a preliminary decision, the architecture A_1 has been selected for the tag

implementation, where both subsystems (UHF and UWB) are independent from each

other, although they share the antenna, and the UWB section is powered by the battery.

• It has been agreed to establish a power budget of the UWB subsection, in order to

foresee if a 2 years lifespan with A_1 architecture (that implies continuous battery

operation) is feasible. If so, A_1 will be finally implemented within the tag design stage. If

not, A_2 will be explored. Other constraints in terms of tag synchronization and code

acquisition time, under investigation in T2.2, might affect the final choice.

5.1.4. Tag substrate

A tag is composed by a silicon IC chip, a metal antenna and a substrate. Although many

different substrates are available in the literature, only those appearing to be the most

suitable for the scope of the project have been analyzed in section 1.3. The following

conclusions have been drawn from such analysis:

• Biodegradable substrates represent a very interesting approach for ticketing

applications in which the lifespan of the tag is only few hours or days. However, due to

the longer lifespan of SELECT tags (up to two years), this type of substrate does not

represent a good alternative. In our case, although the environmental impact of other

non-biodegradable substrates is higher, the higher lifespan implies lower amount in the

waste generated.

• On the other hand, flexible substrates have been appeared as solid candidates for a

future exploitation of the tags. Such substrates present multiple advantages with regard

to rigid substrates: their high biodegradability with respect to other ceramic substrates

such as FR-4, as well as their sizeability, what make their use very attractive for a wide

range of applications, e.g. textile, biomedical, etc. However, they are still without

performance characterization within the UWB frequency band; for this reason, they

will not be used for the tag prototypes.

• Due to the fact that rigid substrates (e.g. FR-4) are well characterized among a wide

bandwidth, the prototypes will be fabricated on PCB (i.e. rigid substrate).

5.1.5. IC technology

To achieve a cost-efficient solutions optimized for low energy operation, compatibility, and

availability, a standard CMOS technology will be utilized to implement the tag. After the

deep study carried out within section 3, the preliminary candidates have been deeply

analyzed through section 4. The conclusions are listed below:





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• The 90nm technology is considered to be a good trade-off between performance and

cost. For certain architectures a 130nm technology would be sufficient, but to allow for

flexibility throughout the project period the 90nm technology node is preferred.

Therefore, CMOS 90 nm is the technology node selected for IC fabrication.

• A Multi-Project Wafer (MPW) service must be available for the selected process, both for

low cost research prototyping (~10-100 samples) and medium cost commercial

prototyping (~100-2000 samples). Based on the potential of reduced prototyping cost

and local presence in Europe Europractice will be the preferred MPW provider.

• Due to the available foundries provided by Europractice, it has been concluded that

either UMC or TSMC will be used for the IC fabrication. A study of these technologies’

performance has proven to be necessary in order to analyze the feasibility of both

processes to cope with the project’s needs, specially low-threshold devices, availability

of digital IP cores, EEPROM memory cells (or similar) and high density capacitances. Both

processes have shown satisfactory results in this regard.

• The overall conclusion in terms of technical criterions is that the candidate technologies

are very similar. The only difference of importance is that the TSMC technology seems to

offer somewhat higher speed which may be useful for the UWB front-end. Both

technologies satisfy the critical criterions (Triple well, RF-options, Schottky replacement,

low power digital circuitry). As a result both candidates may be selected from a technical

point of view. Nevertheless, it has been decided in the technology analysis that the

selected technology for IC fabrication is TSMC CMOS 90 nm LP provided by

EUROPRACTICE.

5.2. NEXT STEPS

The next steps with regard to the work reported in this deliverable are very much related to

the open issues that have been kept for further decision, and have been summarized in the

conclusions, in section 5.1.

• In order to allow for distribution of IC-modules (Even for partner IP) between the

partners active in WP3, an NDA between the partners, Europractice and the foundry

must be approved and signed. In some cases this might be difficult and time consuming.

Furthermore to reduce the risk in the project a second source must be available. As a

result processes should be initiated to get access to both foundries/technologies at an

early stage in the project.

• With regard to the final decision of the tag architecture, the next activities are related to

verify if the pre-selected architecture (A_1) is suitable for the project needs. To do so, a

power budget of the UWB section as well as performance simulations must be carried

out. Architecture A_2 will be investigated if A_1 does not satisfy the requirements. ,

considering that it is continuously powered on by the battery. If 2 year lifespan is feasible,

then A_1 will be implemented. If not, A_2 will be explored.

• Once the architecture is decided, the partners involved in the design of the analog and

digital front-ends (NOV and CEIT) will celebrate an internal meeting to discuss minor

details about the coexistence of UHF and UWB sections.





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• Once established minor details about the selected architecture for the tag, all the

requirements for each subsystem and building block will be derived, and system

simulations will be performed, as a prior stage to the final circuit implementation.





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REFERENCES

TABLES

Table 1. Comparison of energy sources [Roundy03] ............................................................................ 18

Table 2. Energy harvesting capabilities by [Paradiso05] ....................................................................... 19

Table 3. Operation states of switches ................................................................................................... 28

Table 4. Feature summary on three types of down converters............................................................ 30

Table 5. Primary batteries PROS and CONS .......................................................................................... 37

Table 6. Lithium batteries PROS and CONS........................................................................................... 40

Table 7 Primary batteries main parameters comparison...................................................................... 41

Table 8. Available diodes in UMC 90 nm and their descriptions ......................................................... 65

Table 9. Available transistors in UMC 90 nm and their descriptions .................................................... 66

Table 10. Comparison of different capacitors in UMC 90 nm (default sizes) ....................................... 77

Table 12. TSMC capacitor Q-value ........................................................................................................ 81

Table 13. Detailed comparison between UMC and TSMC 90nm CMOS technologies.......................... 85

Table 14. Technology selection ranking ................................................................................................ 86





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FIGURES

Figure 1. Reduction of the size of MOS transistors in the last years (ITRS Roadmap) .......................... 13

Figure 2. Dynamic energy and leakage power vs. supply voltage [Chen10] ......................................... 13

Figure 3. Multi-VDD technique overview .............................................................................................. 17

Figure 4. Flexible module of organic solar cells. ................................................................................... 20

Figure 5. SEM photograph of the cross-sectional view of a MEMS Thermoelectric Generator [Xie10]21

Figure 6. MEMS energy harvester operating in the d33 mode [Park10]................................................ 23

Figure 7. Block diagram of RF energy harvesting principle ................................................................... 24

Figure 8: DC-DC converter. ................................................................................................................... 25

Figure 9: First order model of linear regulator...................................................................................... 27

Figure 10. Power efficiency of linear regulator with various Pcomp ....................................................... 27

Figure 11: An example of the power stage circuit in a capacitive switching regulator........................ 28

Figure 12 : Operation state of half-voltage conversion........................................................................ 29

Figure 13: An example of a simple inductive switching regulator. ....................................................... 29

Figure 14: Typical switching regulator power stage............................................................................. 29

Figure 16: Circuit concept of MTCMOS ................................................................................................. 32

Figure 17: Circuit concepto f SC CMOS.................................................................................................. 32

Figure 18: Reverse body bias (RBB)....................................................................................................... 33

Figure 19 . Volumetric density of lithium batteries .............................................................................. 41

Figure 20. UWB tag section option 1: active UWB................................................................................ 49

Figure 21. UWB tag section option 2: semi-passive UWB..................................................................... 50

Figure 22. Scheme of the tag (2-PAM case) .......................................................................................... 50

Figure 23. Tag architecture A_1 ............................................................................................................ 51

Figure 24. Tag architecture A_2.1 ......................................................................................................... 52

Figure 25. Tag architecture A_2.2 ......................................................................................................... 53

Figure 26. Tag architecture A_3 ............................................................................................................ 54

Figure 27. Diode and transistor schematics used for its characterization ............................................ 65

Figure 28. The I-V characteristics of diodes in UMC 90 nm (default sizes) ........................................... 66

Figure 29. The I-V characteristics of diode-connected transistors in UMC 90 nm (default sizes) ........ 68

Figure 30. The I-V characteristics (Zoom) of diode-connected transistors in UMC 90 nm (default sizes)

............................................................................................................................................................... 69

Figure 31. The I-V characteristics of diode-connected RF transistors in UMC 90 nm (default sizes) ... 70

Figure 32. The I-V characteristics (Zoom) of diode-connected RF transistors in UMC 90 nm (default

sizes) ...................................................................................................................................................... 70





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Figure 33. for different currents of diode-connected RF transistors in UMC 90 nm (default sizes)

............................................................................................................................................................... 71

Figure 34. Cross section of an idealized n-channel MOS transistor and the corresponding symbol

[Enz95]................................................................................................................................................... 72

Figure 35. 3D Cross section of an idealized NMOS transistor ............................................................... 72

Figure 36. Vth for different currents of diode-connected N_10_SPRF transistor varying its length

(W=500nm&F=2) ................................................................................................................................... 73

Figure 37. Vth for different currents of diode-connected P_10_SPRF transistor varying its length

(W=500nm&F=2) ................................................................................................................................... 73

Figure 38. Vth for different currents of diode-connected N_10_SPRF transistor varying its width

(L=80nm&F=2)....................................................................................................................................... 74

Figure 39. Vth for different currents of diode-connected P_10_SPRF transistor varying its width

(L=80nm&F=2)....................................................................................................................................... 74

Figure 40. Vth for different currents of diode-connected N_10_SPRF transistor varying its number of

fingers (W=8um&L=80nm).................................................................................................................... 75

Figure 41. Vth for different currents of diode-connected N_10_SPRF transistor varying its number of

fingers (W=8um&L=80nm).................................................................................................................... 75

Figure 42. Vth for different currents of diode-connected N_10_SPRF and P_10_SPRF transistors

(W=8um&L=80nm&F=32) ..................................................................................................................... 76

Figure 43. I (A) vs Vdc (V) of diode-connected N_10_SPRF and P_10_SPRF transistors....................... 76

Figure 44. Quality factor for different RF capacitors in UMC 90 nm (default sizes) at 868 MHz......... 78

Figure 45. Quality factor for different MIMACPS_20F_RFKF at 868 MHz............................................. 79

Figure 46. I (A) vs Vdc (V) of diode-connected N and P RF transistors in CRN90G ............................... 80

Figure 47. I (A) vs Vdc (V) of diode-connected N and P RF transistors in CRN90LP .............................. 81

Figure 48. Measured output signal from a 5GHz UWB pulse generator implemented in 90nm CMOS82

Figure 49. Measured frequency spectrum of a 5GHz UWB pulse generator implemented in 90nm

CMOS..................................................................................................................................................... 82

Figure 50. Measured output signal from a 6.0 GHz 8.5 GHz UWB pulse generator implemented in

90nm CMOS........................................................................................................................................... 83

Figure 51. Measured frequency spectrum of a 6.0 GHz to 8.5 GHz UWB pulse generator implemented

in 90nm CMOS....................................................................................................................................... 83





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