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Date: 1/25/2018

Revision: 1.3

Cyclone 10 GX Dynamic Reconfiguration with ATX

PLL Switching Reference Design 17.1 User Guide

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Table of Contents Introduction.................................................................................................................................................... 3

Requirements ................................................................................................................................................ 3

Theory of Operation ...................................................................................................................................... 4

How to Setup the Hardware for Link Test ..................................................................................................... 5

How to Reconstruct and Running the Reference Design ............................................................................. 5

Conclusion................................................................................................................................................... 13

References .................................................................................................................................................. 13

Revision History .......................................................................................................................................... 13

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Introduction

The objective of this design example is to demonstrate the implementation of Cyclone 10 GX Native PHY ATX PLL switching, channel reconfiguration with embedded streamer as well as recalibration. The two ATX PLLs are used to support two different data rates which could not be achieved with TX local divider. The purpose of this design example is to assist users to have quick start with the Cyclone 10 GX transceiver dynamic reconfiguration. The design starts with transceiver channel running at 2Gbps data rate and then reconfigure to 1.5Gbps using ATX PLL switching and channel reconfiguration. After reconfiguration is completed, a channel recalibration followed by reset is performed. Incremental data is sent from the TX and loopback to the RX for monitoring. In-System Sources and Probes (ISSP) is used to provide real time control to the transceiver while SignalTap II Logic Analyzer is used for status and data monitoring. The dynamic reconfiguration and recalibration commands are performed through System Console.

Requirements The reference design requires the following hardware and software to run the test:

• Quartus® Prime Software Version: 17.1 Pro Edition

• Cyclone 10 GX Development Kit https://www.altera.com/products/boards_and_kits/dev-kits/altera/cyclone-10-gx-development-kit.html

• FPGA Mezzanine Card (FMC) loopback card

Figure 1. Cyclone 10 GX Development Kit

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Theory of Operation

Figure 2. Block diagram of modules in the reference design

Figure 2 shows the high-level modules in the reference design as well as the interfaces among the

modules. The C10GX transceiver Native PHY is used to configure and implement the hard transceiver

channels. The Reset Controller is used to perform the reset to the transceiver channel and ATX PLL. In-

System Sources and Probes allow real time user control on the design ie reset, bit slip etc. System

Console is used to interface with the Native PHY to execute the commands for transceiver dynamic

reconfiguration and recalibration. Incremental counter value is fed to the TX and loopback to RX through

FMC loopback card. The design comes with frequency counters which are used to monitor the tx_clkout

and rx_clkout frequencies to verify if the data rate change is done successfully. Signal Tap is used to

monitor the status signals as well as the frequency counter values.

After power up, by default the transceiver channel will be running at 2Gbps. With the PCS-PMA interface

width = 10bits, the expected tx_clkout and rx_clkout frequencies are 200MHz. The transceiver rate

change is done by switching the ATX PLL that the Native PHY is listening to. After reconfiguring the

transceiver channel to 1.5Gbps, the expected tx_clkout and rx_clkout frequencies are 150MHz.

The following shows the high-level steps to perform the transceiver dynamic reconfiguration with ATX

PLL switching:

• Assert reset to the Native PHY

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• Request access to AVMM bus of targeted channel

• Perform ATX PLL switching

• Perform a channel reconfiguration by switching the profile using embedded streamer

• Perform channel recalibration

• Release the reset of the Native PHY

For further details on ATX PLL switching dynamic reconfiguration, you may refer to the Intel Cyclone 10

GX Transceiver PHY User Guide -> "Switching Transmitter PLL" section.

For further details on transceiver channel reconfiguration, you may refer to the Intel Cyclone 10 GX

Transceiver PHY User Guide -> “CDR/CMU PLL Recalibration” and “PMA Recalibration” sections.

How to Setup the Hardware for Link Test Follow these steps to setup the hardware to run the reference design:

1. Connect the FMC loopback card to the FMC port on the Cyclone 10 GX Development Kit

2. Use the default switching settings of the development kit

3. Connect the Micro USB cable to the USB Blaster connector on the development kit

4. Connect the power adapter shipped with the development board to power supply jack

5. Turn On the power for the Cyclone 10 GX Development Kit. The hardware system is now ready

for programming

How to Reconstruct and Running the Reference Design Follow these steps to reconstruct, compile and run the design:

1. Follow the instruction in the Design Store to prepare the design template and load the design

into your Quartus software

2. Please note that the design downloaded from Design Store does not enable the Signal Tap Logic

Analyzer in Quartus project. To include the Signal Tap file into Quartus project, navigate to the

Assignments menu and select Settings.

3. Click on the Signal Tap Logic Analyzer under Category, and then check the Enable Signal Tap

Logic Analyzer checkbox.

4. Browse the stp1.stp file in the project directory and hit OK button

5. Perform full compilation with the design

6. Do the following to reduce the JTAG frequency to 16M to avoid JTAG connection issue

a. Launch NIOS II command shell from Windows Quartus Pro v17.1 startup menu b. Follow the commands in Figure 3 to configure the JTAG frequency

7. Only execute this step if your C10 GX Development Kit Board belongs to first prototype build

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with board serial number within 0000001-0000030 else skip to the next step. For first prototype

board, by default after power up the development kit board, the programmable clock generator

(Si5332) used for the transceiver channel in this design is disabled. Do the following to enable

and configure the output clock frequencies correctly

a. Download and unzip “Kit Collateral.zip” design package from below link

https://www.altera.com/products/boards_and_kits/dev-kits/altera/cyclone-10-gx-

development-kit.html

b. Launch Quartus software first then run the ClockController.exe from

cyclone-10-gx-kit-collateral\examples\board_test_system

c. By default, the Clock Controller GUI should look like Figure 4

d. Click the “Import” button in Clock Controller GUI and select the “U64-Registers.txt” in

cyclone-10-gx-kit-collateral\examples\board_test_system folder to configure the output clock

frequencies

e. After successful configuration, the Clock Controller GUI should look like Figure 5

f. Close the Clock Controller application

g. Note that you would need to reconfigure the Si5332 using step 4(b) -> 4(f) each time the

Development Kit Board is power-cycled

8. Program the SOF file generated into the Cyclone 10 GX Development Kit

9. After the programming is completed, open the Spf1.spf ISSP instance and establish connection

to the C10 GX device as shown in Figure 6

10. The ISSP allows you to perform real-time control on the transceiver

11. Open the stp1.stp Signal Tap file and establish connection to the C10 GX device

12. Then click on Run Analysis button. Since the default power up transceiver data rate is 2Gbps,

you should see the tx_clkout and rx_clkout frequencies = 200MHz as shown in Figure 7. The

freqout_counter of frequency_checker[0] represents the tx_clkout frequency while the

freqout_counter of frequency_checker[1] represents the rx_clkout frequency

13. Go to Spf1.spf and set source[0] to 1 to keep the transceiver channel in reset mode

14. Open the reconfig.tcl file in the project directory and do the following changes to line 61:

a. Change “set new_reg_value 0x81” to “set new_reg_value 0xa1”

b. Note that the new_reg_value in the TCL was pre-determined. You may refer to the

“Logical PLL Encoding” in the Cyclone 10 GX Transceiver User Guide for further details.

15. Open the System Console in Quartus as shown in the Figure 8

16. After connection established to the C10 GX device, type “source reconfig.tcl” to source the TCL

file for dynamic reconfiguration as shown in Figure 9

17. Then type “reconfig_to_1p5g” to start the dynamic reconfiguration of transceiver data rate to

1.5Gbps as shown in Figure 10

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18. After the dynamic reconfiguration is completed, you should see messages as shown in Figure 11

19. Go to Spf1.spf and set source[0] to 0 to release the transceiver channel from reset mode

20. Go back to stp1.stp and click on Run Analysis button again. You should see the tx_clkout and

rx_clkout frequencies = 150MHz as shown in Figure 12. This shows that the dynamic

reconfiguration of the transceiver data rate to 1.5Gbps using ATX PLL switching is successful

Figure 3. Commands to Reduce the JTAG Frequency to 16M

Figure 4. Default Clock Controller GUI for Si5332

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Figure 5. Clock Controller GUI for Si5332 after Successful Configuration

Figure 6. In-System Sources and Probes Editor

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Figure 7. tx_clkout and rx_clkout Frequencies for 2Gbps Data Rate

Figure 8. Launching the System Console

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Figure 9. Sourcing the TCL for Dynamic Reconfiguration

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Figure 10. Command to Reconfigure the Transceiver Channel to 1.5Gbps

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Figure 11. Dynamic Reconfiguration is Completed

Figure 12. tx_clkout and rx_clkout Frequencies for 1.5Gbps Data Rate

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Conclusion The design example provides a reference on how to perform dynamic transceiver rate change with ATX PLL switching, channel reconfiguration with embedded streamer as well as recalibration.

References • Intel Cyclone 10 GX Transceiver PHY User Guide

https://www.altera.com/documentation/hki1486507600636.html

Revision History Date Version Changes

January 25, 2018 1.3 Updated step to enable Si5332

December 22, 2017 1.2 Added note for logic PLL encoding

December 20, 2017 1.1 Added step to update the PLL mux selection value

December 15, 2017 1.0 Initial Release