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CV3: I/O, Central Reference
Ray XuMay 3, 2018
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Outline
• I/O Pinout Iteration As Of Today• Status of Central Reference
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I/O Pinout As Of Today
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I/O Pinout As Of Today
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I/O Pinout As Of Today
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• Currently: 1 VDDA pin per channel per block • Request:
– Take two pins on left-hand side for purpose of +100mV/+1.1V external decoupling (standard practice for commercial high-res ADCs)
– Compromise: take away VDD_XSW domain, shift pins up (down)
Status of Central Reference
• Overall goal of “Central Reference”– Takes either BGP or off-chip bias current– Gives chip-wide bias current + reference voltages
• BGP modifications– Forced startup circuit– Current reference output replica (for chip-wide biasing)– Cannot get 1.1V because of no PMOS headroom as
designed
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Status of Central Reference
• On its own power domain for best noise immunity• Two ways to get 1.1V on-chip
– Run the current reference thru a resistor
(Most simple, no PSRR)– Use an op amp to amplify BGP 100mV
(More involved, explained next)
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Status of Central Reference
• “Low-VCM, high VOUT” amp with resistive common-source output stage used to derive 1.1V. Prelim results:
– Total sum noise @ 1.1V: 200uVrms w/ 100pF load– PSRR:
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Status of Central Reference
• Two op amps were designed (available for use):– Low-VCM input, high VOUT output– High-VCM input, low VOUT output– Output stage: resistive common-source (to reach rail),
or Chen-kai’s ref buffer topology– Gain-boosted folded cascode, single-ended output– >80db OL gain, >500MHz UGBW, < 2mA VDD– Self-compensated using output stage: 70-80 deg PM
can be achieved
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Status of Central Reference
• Full design and characterization to be reported soon!
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Backup Slides: BGP Characterization
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BGP Characterization: Tran
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VDD
BGP2(Notice this has Bode plot peaking)
BGP1 @ 100mV
Cload = 1pFNo tran noiseConservative accuracy
BGP1 @ 200mV
BGP1 @ 300mV
BGP Characterization: PSRR
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Final state from tran sim used for AC PSRR sim
BGP1 @ 100mV
BGP1 @ 300mV
BGP2(Notice peak >0dB)
