Custom Computing Custom Computing Machines for the Set Machines for the Set

Covering ProblemCovering ProblemPaper Written By: Christian Plessl and

Marco PlatznerSwiss Federal Institute of Technology, 2002

Presentation By Greg Jackson

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OverviewOverviewIntroduction to the ProblemCurrent SolutionsProposed Reconfigurable

ArchitectureImplementation ExperimentationResults

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The ProblemThe ProblemBoolean Satisfiability (SAT)

◦A discrete decision problem whereby variables are found such that a boolean expression in Conjunctive Normal Form(CNF) is evaluated true.

CNF?◦Given Expression – (A and B) or C◦CNF Equivalent – (A or C) and (A or

B)

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The ProblemThe ProblemThe Set Covering Problem is a Minimum

Cost SAT Problem“Given a set U of elements and a set S of

subsets ti of U, i = 1... |S|, find the smallest subset T, that contains all elements of U”

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The ProblemThe ProblemOften in

Expressed in Matrix Form

The Matrix A is a subset of columns with at least one entry for all the variables (A, B, C, D)

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The ProblemThe ProblemThe Set Covering problem is often

associated with the Synthesis of Reconfigurable Designs

Logic Optimization that occurs during synthesis is a Set Covering Problem ◦e.g. Two-level logic minimization,

state minimization

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Current SolutionsCurrent SolutionsSoftware - Mini & Espresso

◦Utilizes a technique called Branch and Bound

◦Heuristic Methods Variable Order, Order of Value Assignments

etc.

Branch and Bound◦The software creates search trees and

iterates over all values, trimming the trees as possible solutions are ruled out

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Branch and BoundBranch and BoundA – Matrix Defining

the Set Covering Problem

V – Current Variable Assignment

B – Current Low Cost Solution

Heuristics can be applied to Algorithm◦ Variable Order◦ Value Assignments

Algorithm can be Bounded by Cost

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Why Did They Do It?Why Did They Do It?Faster

◦Speedups in the order of several magnitudes to solve more problems

Evaluation of Heuristics◦Need fast solvers to evaluate the

performance of heuristics and approximations

Development of New Heuristics◦New methods = New Heuristics

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Proposed ArchitectureProposed ArchitectureBasic Accelerator -

Four Blocks◦ An Array of finite

state machines (FSMs)

◦ Checker Modules◦ Cost Counter◦ Controller

Architecture utilizes 3-valued Logic◦ {1,0,X}

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Proposed ArchitectureProposed ArchitectureFSM

◦ Implementation of the Branch and Bound in Hardware

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Search HeuristicsSearch HeuristicsTwo Things Affecting Efficiency

◦Variable Order Index Order – Variables are placed in order

of their index Frequency Order – Variables that appear

frequently are placed at the top of the array

◦Assignment Order 0 – 1 – FSM assigns a 0 first to the CNF 1 – 0 – FSM assigns a 1 first to the CNF Random

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Cost BoundCost BoundLimit on the amount of

assignments

This limits the length of the search

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Hardware ReductionsHardware Reductions3 Ways

◦ Don’s Cares◦ Essentials◦ Dominated

ColumnsThis Creates a

New State Machine

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ImplementationImplementationImplemented 4

Architectures◦ CE – Basic◦ CEDC – Don’t Cares◦ CEDCES – Essentials◦ CEDCESDCOL – All 3

forms of Hardware reduction

Used Xilinx Virtex XCV1000 and simulated the system using ModelSim

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ExperimentsExperimentsUsed two sources for test problems

◦Two-level logic minimization◦Steiner triple system

Selected 21 problems from Espresso distribution for testing

Test Problems Have 4-62 Variables and 4-70 clauses (i.e. A or B)

Would then compare the accelerator to the software implementation

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Results – Raw SpeedupResults – Raw SpeedupCompared the runtimes to that of the SoftwareDid not take into account delays i.e. Code

generation, synthesis, etc.Using the CEDCESDCOL accelerator, achieved

orders of magnitude speed upAverage Speedup – 4 orders of magnitude over

the Software

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Results – Relative Results – Relative SpeedupSpeedupCompared the architectures to each other in

terms of speed upFor the graph, used best performance

heuristicsThe CEDCESDCOL architecture was the fastest

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Results – Heuristic Results – Heuristic PerformancePerformanceUsed the four different

architectures and determined which heuristics worked best for each

Example: CEDCES◦Variable Order – Frequency Variable

Order◦Variable Assignment – Random

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ConclusionsConclusionsSpeedups were promising but...

◦The tested problems were too small and can be solved in seconds in software (5ms – 1.3s)

◦The synthesis time of the designs were in the order of minutes

◦Reducing the hardware made the accelerators slower with larger problems when compared to the software.

Suggest a Hardware/Software Accelerator◦Speed up of Hardware + Sophistication of

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Final ThoughtsFinal ThoughtsExtensive Paper

It was a Continuation of a Previous Paper

Useful application

Hardware Reductions not Explained Well

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