CU Springs Confirma 01-31-11

7/29/2019 CU Springs Confirma 01-31-11

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Confirma

The Next Era of Rapid Prototyping


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Verification Is Not Getting Any Easier

The Dominant Cause ForSilicon Re-spins

Functional errors

Bug count increasing

exponentially with design size

Need to test with live stimulus

IC/ASIC Designs Failing First Silicon by Type of Flaw

2%

6%

11%

15%

17%

18%

18%

19%

21%

22%

32%

33%

60%

0% 15% 30% 45% 60% 75%

RET: OPC/PSM Induced

Other Flaw

Firmware

Yield or Reliability

IR Drops

Timing Path Too Fast

Mixed-Signal Interface

Crosstalk-Induced Delays

Power Consumption

Clocking

Tuning Analog Circuit

Timing Path Too Slow

Logic or Functional

Percent of Designs Failing First Silicon

Software Content IsIncreasing Dramatically

Sufficient performance is key

Verification

Software

0

10

20

30

40

50

60

70

0.35m 0.25m 0.18m 0.13m 90nm 65nm

ChipDesignCost($M)

Process Node

(Transistor Count )

Prototype Ar chitectur e Vali dati on Physical Ver ifi cation Softw ar e

(2M) (5M) (20M) (40M) (80M) (120M)

Source: IBS,2008

(2M) (5M) (20M) (40M) (80M) (120M)

Source: IBS,2008

Our biggest challenge in SoCdevelopmentis software.

Software cost is over 60% of the totalcost of system design.


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Software-Differentiated Hardware Era

Phone differentiation used to be about radios and antennas andthings like that. We think, going forward, the phone of the future will

be differentiated by software.Steve Jobs

CEO, Applehttp://online.wsj.com/article/SB121842341491928977.html

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

180nm 130nm 90nm 65nm 45nm 32nm 22nm

Software and Hardware Development Cost Trends

Hardware

Software

Source: IBS, 2008


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System Performance

Performance MattersEnabling System Validation And Software Development

Boot OS in DAYS Boot OS in HOURS Boot OS inSECONDS

GSM Standard Reference Frequency

13 MHz

MPEG-2 System Time Clock

27 MHz

USB2.0

30 MHz

Rapid Prototyping

Emulation

Acceleration

1 cps 100 cps 1,000,000 cps 50,000,000 cps10,000,000 cps


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RTL Verification

ImplementationEffort

Performance (Hz)

| Simulation | Acceleration | Emulation | Prototype |

1 100 1K 10K 100K 500K 1M 5M 10M 100M

Simulation

Simulation

Acceleration

Emulation-Transaction based

-In-circuit

RapidPrototyping

Test Silicon

Chip Verification

HW/SW Verification

SW Development

Innovator

VCS

Confirma Product Positioning

High-performance

ASIC Prototyping

System

Highest Performance In-circuit validation with live

stimulus

Software development

Flexibility and Ease of Use More automated chip validation

Transaction based verification

Flow integration


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ConfirmaDefining The Next Era In Rapid Prototyping

Traditional Prototype Traditional Emulator

ConfirmaComplete Prototyping

- Manual- Difficult debug

- Big- Expensive- Slow

+ Compact+ Affordable+ Fast

+ Automated+ Easy debug


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Prototyping Made Easy

System Solutions Single point for hardware and

software support

Tightly Integrated ConfirmaPlatform

High Performance Flexible Hardware

Configurable

Over 30 daughter boards

Reuse for multiple projects

Over 500 companiesworldwide

Over 2000 boards shipped

High-performance ASIC Prototyping System


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We Offer Real World IOCommon boards support both HAPS and CHIPit

ADC / DAC

DVI

DVBGigabit

Ethernet

PCIe

DDR2

USB 2.0

SATA

ARM

Core Tile

At-speed Connections to Real-world Interfaces Enable Realistic Validation

PCI-X


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HAPS-60 Family

HAPS-64Up to 18M gates

CAPACITY

HAPS-62Up to 9M gates

HAPS-61Up to 4.5M gates


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C

External

Internal

G

Connector Connector Connector Connector Connector Connector

Connector Connector Connector Connector

Connector Connector Connector Connector

Connector Connector Connector Connector Connector Connector

Connector Connector

Connector Connector

T T

T T

Connector

Connector

Connector Connector

ConnectorConnector

Connector

Connector

Connector

FPGA FPGA

FPGAFPGA

Fixed

inter-FPGA connections

I/Os or

inter-FPGA connections

Local clocks

Global clocksC

Global I/OsG

Test signalsT

Our aim with HAPS is to offer a high performance hardware platform for ASIC prototyping with

maximal flexibility. The flexibility is reached by a modular concept which also keeps the cost at

a minimum; you don't pay for "unnecessary" hardware.

A HAPS system consists of at least a motherboard. The motherboard is a pure logic container

with the biggest FPGAs in the biggest packages.

High quality 120-pin connectors for I/Os and inter-FPGA buses are placed in a regular

50x70 mm matrix.

Each FPGA is connected to a group of connectors.The remaining signals connect the FPGAs together.Each connector has dedicated pins, one for power and one or more for clock.The remaining dedicated clock inputs on the FPGA devices are connected to global clocks. The

low skew clocks are distributed by clock buffers, placed in the middle of the board.

A few global signals are available for functions like reset and enable.Each FPGA has a pair of signals intended for test procedures.Wider buses between the FPGAs are easily created by low cost inter-connect boards.A 4-way bus is created by another simple inter-connect board.Non-adjacent connectors can be connected together with high speed coax cables.Ordinary daughter boards, like memory boards and interface boards can be placed on any

connector.

The size of a daughter board is strictly specified. There are no "wasted" connectors on the

motherboard.

HAPS Concept


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HSTDM ( High Speed TDM)

Mux

+

reg

reg

signals

counter

De

Mux

+

OSERD

ES

ISERDE

S

100 Mhz clk

counter

reg

reg

signals

LVD

S

I/o

prm

Delay

LVD

S

LVDS

DCM200 Mhz clk 400 Mhz clk BUF

R

LVDS

400 Mhz clk100 Mhz clk

BUFIO

Source FPGA Destination FPGA


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The Solution To Rents Rule

Number of pins = t * (Design Size) ^ p ASIC 1.2 M gates 253 pins

2 FPGAs 610K gates/FPGA 322 pins

Each FPGA on a HAPS 6X board has a 4.5 Mgate capacity No partitioning needed (For thiscase)!

< 2800 flexible I/Os available on HAPS 64

boards for either ASIC I/O or interconnect. High Speed Pin Multiplexing using Xilinx

ISERDES/OSERDES available if you need it!


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HAPS Configuration An example


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Universal Multi-Resource Bus (UMRbus)Functionalities & Use Modes

What It Is High-performance, low-latency

communication bus

Connections to every FPGA,memories, registers, etc.

Customer Benefits Remote prototype management Application-level programming Co-simulation Transaction-based verificationF

AST

UMRBus


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Co-simulation

Confirma Prototyping Hardware

Host

Co-SimulationHDL-Bridge

viaPLI InterfaceEvent / Clock

Cycle Based

High Performance HDL SimulatorVCS

CO-SIMULATION

HAPS Features Supports VCS (and other simulators) Off-line debug with VCS Interactive debug with Identify Pro Built on UMRBus

Customer Benefits Easy transition from simulation to

prototype

Re-use existing regression tests Validate prototype implementation Continue verification in hardware


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Transaction-based Verification

* Appropriate testbench required

Host

Testbench/ApplicationC/C++, System C, SystemVerilog

TransactionBased

VerificationSCE-MI 2.0

TransactionLevel

Interface

TBV

Confirma Prototyping Hardware

HAPS Features Industry-standard SCE-MI 2.0 support Uses transaction-based testbenches

(C/C++/VCS/Innovator)

VMM-HAL support Built on UMRBus

Customer Benefits Up to 10,000x faster than simulation* Interface to live devices Re-use existing regression tests Accurate modeling Leverage prototype hardware earlier


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Solutions Overview

Provideindustry

leadingFPGAImplementation,

High LevelDesign, andHardwareAssisted

Verificationsolutions

FPGA

Implementation

High-Level

Synthesis

ConfirmaTM

ASIC/ASSP

Verification

Platform

Synplify Pro

Advanced FPGA Synthesis

Synplify PremierGraph-Based Physical Synthesis

Identify

RTL Debugger

Synplify DSPDSP Implementation for FPGAs and ASICs

Certify

Multi-FPGA ASIC Prototyping

Synplify PremierSingle-FPGA ASIC Prototyping

Identify ProWith TotalRecallTM Full Visibility Technolgoy

HAPSTMHigh-Performance ASIC Prototyping SystemTM

CHIPit ManagerImplementation & Co-verification for CHIPit Hardware Products

CHIPit Platinum & Iridium EditionAutomated Prototyping Systems


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Certify Multi-FPGA Partitioning

RTL View

Connectivity Matrix

Partition View

Partition Info ViewPartition Tree View

Partition UI

Impact Analysis


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Identify Instrumentor

Automatically displayssignals and branches

Control sampling &

triggering on each

node

State Machine

Triggering

Provides area estimate

of debug resources

Automate with TCL

scripts


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Identify Debugger

Dynamically setstrigger values

Displays captureddata symbolically

Tabbed view ofmultiple clockregions

Multiple debuggersper scan chainsupported

Full TCL scripting


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Accelerating HardwarePrototype Development

Chuck Cruse

Prototype/Emulation Team Lead


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LSI Prototyping System HAPS 34

PCIE Interface

PowerPC

Peripherals

SAS/SATA 1.5G

DDR Memory

8-Way

Bus


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Real World exercise of RTL

Hardware/Software integration vehicle

Detection and debug of subtle system-levelReal Time problems

Specification verification amongst various

compatible products

Customer demo

Hardware Prototypes Provide


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Must hit a narrow window of opportunity

Delays in the development of the prototype

reduce effectiveness

Visibility of internal signals, while improving,

remains a challenge

Quick turnaround of incremental changesimproving, but could be better

Issues for the Hardware Prototype


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In the past, FPGA-specific RTL has beensimulated in order to demonstrate basic

functionality before downloading bitstreams into

the lab.

For the future, the hope is that this approach

could be expanded to include Virtual Platforms

Moving Up the Food-Chain


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Design Example


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Future Feasibility Study


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Additional Product Development Goals

Retain the benefits of software simulation Cycle-accuracy will suffer, but the hardware prototype will catch

these issues

Begin hardware/software integration very early in the

development process

Hardware/software effort will be more transparent whencrossing over from the virtual world to the hardwareprototype

Hardware prototypes always resulted in a step function effort Step function effort should reduce when the virtual platform is

incorporated


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End-Of-Day Benefits

Reduced spins of the design

Much faster chip-evaluation when silicon arrives

Software ready to go Integration/System-Engineering team already up to

speed on the device

Effective widening of the pre-silicon testing

window


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HAPS 52 Debug Demo


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Predictable Success

Documents

CU Springs Confirma 01-31-11