CSE477 L24 RAM Cores.1 Irwin&Vijay, PSU, 2002

CSE477VLSI Digital Circuits

Fall 2002

Lecture 24: RAM Cores

Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477

[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

CSE477 L24 RAM Cores.2 Irwin&Vijay, PSU, 2002

Review: Basic Building Blocks

Datapath Execution units

- Adder, multiplier, divider, shifter, etc.

Register file and pipeline registers Multiplexers, decoders

Control Finite state machines (PLA, ROM, random logic)

Interconnect Switches, arbiters, buses

Memory Caches (SRAMs), TLBs, DRAMs, buffers

CSE477 L24 RAM Cores.3 Irwin&Vijay, PSU, 2002

Review: Read-Write Memories (RAMs) Static – SRAM

data is stored as long as supply is applied large cells (6 fets/cell) – so fewer bits/chip fast – so used where speed is important (e.g., caches) differential outputs (output BL and !BL) use sense amps for performance compatible with CMOS technology

Dynamic – DRAM periodic refresh required small cells (1 to 3 fets/cell) – so more bits/chip slower – so used for main memories single ended output (output BL only) need sense amps for correct operation not typically compatible with CMOS technology

CSE477 L24 RAM Cores.4 Irwin&Vijay, PSU, 2002

Review: 4x4 SRAM Memory

A0

Row

Dec

oder

!BLWL[0]

A1

A2

Column Decoder

sense amplifiers

write circuitry

BL

WL[1]

WL[2]

WL[3]

bit line precharge2 bit words

clocking and control

enable

read precharge

BL[i] BL[I+1]

CSE477 L24 RAM Cores.5 Irwin&Vijay, PSU, 2002

6-transistor SRAM Cell

!BL BL

WL

M1

M2

M3

M4

M5M6Q

!Q

CSE477 L24 RAM Cores.6 Irwin&Vijay, PSU, 2002

SRAM Cell Analysis (Read)

!BL=1 BL=1

WL=1

M1

M4

M5M6

Q=1!Q=0

CbitCbit

Read-disturb (read-upset): must carefully limit the allowed voltage rise on !Q to a value that prevents the read-upset condition from occurring while simultaneously maintaining acceptable circuit speed and area constraints

CSE477 L24 RAM Cores.7 Irwin&Vijay, PSU, 2002

SRAM Cell Analysis (Read)

!BL=1 BL=1

WL=1

M1

M4

M5M6

Q=1!Q=0

CbitCbit

Cell Ratio (CR) = (WM1/LM1)/(WM5/LM5)

V!Q = [(Vdd - VTn)(1 + CR (CR(1 + CR))]/(1 + CR)

CSE477 L24 RAM Cores.8 Irwin&Vijay, PSU, 2002

Read Voltages Ratios

0

0.2

0.4

0.6

0.8

1

1.2

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4

Cell Ratio (CR)

Vo

ltag

e R

ise

on

!Q

Vdd = 2.5VVTn = 0.5V

CSE477 L24 RAM Cores.9 Irwin&Vijay, PSU, 2002

SRAM Cell Analysis (Write)

!BL=1 BL=0

WL=1

M1

M4

M5M6

Q=1!Q=0

Pullup Ratio (PR) = (WM4/LM4)/(WM6/LM6)

VQ = (Vdd - VTn) ((Vdd – VTn)2 – (p/n)(PR)((Vdd – VTn - VTp)2)

CSE477 L24 RAM Cores.10 Irwin&Vijay, PSU, 2002

Write Voltages Ratios

0

0.2

0.4

0.6

0.8

1

0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4

Pullup Ratio (PR)

Wri

te V

olt

age

(VQ

)

Vdd = 2.5V|VTp| = 0.5V

p/n = 0.5

CSE477 L24 RAM Cores.11 Irwin&Vijay, PSU, 2002

Cell Sizing

Keeping cell size minimized is critical for large caches

Minimum sized pull down fets (M1 and M3) Requires minimum width and longer than minimum channel

length pass transistors (M5 and M6) to ensure proper CR But sizing of the pass transistors increases capacitive load on

the word lines and limits the current discharged on the bit lines both of which can adversely affect the speed of the read cycle

Minimum width and length pass transistors Boost the width of the pull downs (M1 and M3) Reduces the loading on the word lines and increases the

storage capacitance in the cell – both are good! – but cell size may be slightly larger

CSE477 L24 RAM Cores.12 Irwin&Vijay, PSU, 2002

6T-SRAM Layout

VDD

GND

QQ

WL

BLBL

M1 M3

M4M2

M5 M6

CSE477 L24 RAM Cores.13 Irwin&Vijay, PSU, 2002

Multiple Read/Write Port Cell

WL2

BL2!BL2

M7 M8

!BL1 BL1

WL1

M1

M2

M3

M4M5 M6Q!Q

CSE477 L24 RAM Cores.14 Irwin&Vijay, PSU, 2002

4x4 DRAM Memory

A0

Row

Dec

oder

BLWL[0]

A1

A2

Column Decoder

sense amplifiers

write circuitry

WL[1]

WL[2]

WL[3]

bit line precharge2 bit words

BL[0] BL[1] BL[2] BL[3]clocking,

control, and refresh

enable

read precharge

CSE477 L24 RAM Cores.15 Irwin&Vijay, PSU, 2002

3-Transistor DRAM Cell

M1 M2

M3

X

BL1 BL2

WWL

RWL

X Vdd-Vt

BL1Vdd

WWL write

RWL read

BL2 Vdd-Vt V

No constraints on device sizes (ratioless)Reads are non-destructiveValue stored at node X when writing a “1” is VWWL - Vtn

Cs

CSE477 L24 RAM Cores.16 Irwin&Vijay, PSU, 2002

3T-DRAM Layout

BL2 BL1 GND

RWL

WWL

M3

M2

M1

CSE477 L24 RAM Cores.17 Irwin&Vijay, PSU, 2002

1-Transistor DRAM Cell

M1 X

BL

WL

X Vdd-Vt

WLwrite“1”

BL Vdd

Write: Cs is charged (or discharged) by asserting WL and BLRead: Charge redistribution occurs between CBL and Cs

Cs

read“1”

Vdd/2 sensing

Read is destructive, so must refresh after read

CBL

CSE477 L24 RAM Cores.18 Irwin&Vijay, PSU, 2002

1-T DRAM Cell

(a) Cross-section

(b) Layout

Diffusedbit line

Polysiliconplate

M1 wordline

Capacitor

Polysilicongate

Metal word line

SiO2

n+ Field Oxide

Inversion layerinduced by plate bias

n+

poly

poly

Used Polysilicon-Diffusion Capacitance

Expensive in Area

CSE477 L24 RAM Cores.19 Irwin&Vijay, PSU, 2002

DRAM Cell Observations

DRAM memory cells are single ended (complicates the design of the sense amp)

1T cell requires a sense amp for each bit line due to charge redistribution read

1T cell read is destructive; refresh must follow to restore data

1T cell requires an extra capacitor that must be explicitly included in the design

A threshold voltage is lost when writing a 1 (can be circumvented by bootstrapping the word lines to a higher value than Vdd)

CSE477 L24 RAM Cores.20 Irwin&Vijay, PSU, 2002

Next Lecture and Reminders Next lecture

Peripheral memory circuits- Reading assignment – Rabaey, et al, 12.3

Reminders Project final reports due December 5th Final grading negotiations/correction (except for the final

exam) must be concluded by December 10th Final exam scheduled

- Monday, December 16th from 10:10 to noon in 118 and 121 Thomas