CSCE 668DISTRIBUTED ALGORITHMS AND SYSTEMS

Fall 2011Prof. Jennifer WelchCSCE 668

Set 8: More Mutex with Read/Write Variables 1

Number of R/W Variables

CSCE 668Set 8: More Mutex with Read/Write Variables

2

Bakery algorithm used 2n shared read/write variables.

Tournament tree algorithm used 3n shared read/write variables.

Can we do (asymptotically) better, in terms of fewer variables?

No!

Lower Bound on Number of Variables

CSCE 668Set 8: More Mutex with Read/Write Variables

3

Theorem (4.19): Any no-deadlock mutual exclusion algorithm using read/write variables must use at least n shared variables.

Proof Strategy: Show by induction on n there must be at least n variables.For each n, there is a configuration in which n variables are covered: means some processor is about to write to it.

Appearing Quiescent

CSCE 668Set 8: More Mutex with Read/Write Variables

4

Two configurations C and D are P-similar if each processor in P has same state in C as in D and each shared variable has same value in C as in D.

A configuration is quiescent if all processors are in remainder section.

To make the induction go through, the configuration whose existence we prove must appear quiescent to a set of processors: C is P-quiescent if there is a quiescent

configuration D such that C and D are P-similar

Warm-Up Lemma

CSCE 668Set 8: More Mutex with Read/Write Variables

5

Before a processor can enter its CS, it must write to an uncovered variable.

Lemma (4.17): If C is pi-quiescent, then there is a pi-only schedule such that

pi is in CS in (C) and

during exec(C,), pi writes to a variable that is not covered in C.

Proof of Warm-Up Lemma (a)

CSCE 668Set 8: More Mutex with Read/Write Variables

6

Since C is pi-quiescent, it looks the same to pi as some quiescent D.

By ND, some pi-only schedule exists starting at D in which pi enters CS.

When starts at C, pi also enters CS.

pi in CS by NDD

quiescent

Cpi-quiescent

pi in CS

Proof of Warm-up Lemma (b)

CSCE 668Set 8: More Mutex with Read/Write Variables

7

Suppose in contradiction when is executed starting at C, pi writes to the set of variables W but all the variables in W are covered in C.

Let P be the set of processors covering the variables in W.

1C Eone step by eachproc in P; over-writes W

Q2successivelyinvoke ND tocause all procsto be in remainder;pi takes no step

some pj (not pi)takes steps alone;by ND eventuallypj enters CS

Proof of Warm-up Lemma (b)

CSCE 668Set 8: More Mutex with Read/Write Variables

8

1C Eoverwrites W

Q2successivelyinvoke ND

pj-only pj in CS

1 E'overwrites W

Q'2successivelyinvoke ND

pj-only pj in CS,

pi in CS

Only difference in shared memory between C and C' are the writes by pi, but

those values are overwritten in 1 so the info is lost.

C'

pi-only,writes to W

pi inCS

Main Result

CSCE 668Set 8: More Mutex with Read/Write Variables

9

Lemma (4.18): For all k between 1 and n, for all quiescent C, there exists D s.t.

D is reachable from C by steps of p0,…,pk-1 only

p0,…,pk-1 cover k distinct variables in D

D is {pk,…,pn-1}-quiescent.

implies desired result when k = n

Proof of Main Result - Basis

CSCE 668Set 8: More Mutex with Read/Write Variables

10

By induction on k.Basis: k = 1. Must show for all quiescent

C, there exists D s.t. D is reachable from C by steps of p0 only

p0 covers a variable in D D looks quiescent to the other procs.

By warm-up lemma (a), if p0 takes steps alone, it eventually writes to some var.

Desired D is just before p0 's first write.

Proof of Main Result - Induction

CSCE 668Set 8: More Mutex with Read/Write Variables

11

Assume for k, show for k+1.

C C1any qui.config.

only p0 topk-1 take steps

p0 to pk-1

cover W;pk to pn-1 qui.

0

pk-only

pk coversx not in W

p0 to pk-1 overwrite W,become quiescent

D1'pk in entrylooks qui.to rest

Proof of Main Result - Induction

CSCE 668Set 8: More Mutex with Read/Write Variables

12

C C1any qui.config.

only p0 topk-1 take steps

p0 to pk-1

cover W;pk to pn-1 qui.

0

pk-only

pk coversx not in W

p0 to pk-1 o'write W,become quiescent

D1'pk in entrylooks qui.to rest

D1qui.

C2

p0 to pk-1

onlyp0 to pk-1

cover W;pk to pn-1 qui.

C2'

p0 to pk

cover Wand x;pk+1 to pn-1 qui.

but why is the same setof k vars covered again?

Proof of Main Result - Fix

CSCE 668Set 8: More Mutex with Read/Write Variables

13

The result of applying to D1 might result in a different set of k variables, W', being covered instead of W.

If W' includes x, we have not succeeded in covering an additional variable.

To fix this problem, repeatedly apply inductive hypothesis to get

C1,D1,C2,D2,C3,D3,… Since number of variables is finite, there exist i

and j such that in Ci and Cj the same set of k variables is covered.

Then apply same argument as before, replacing C1 and C2 with Ci and Cj.

Fast Mutual Exclusion

CSCE 668Set 8: More Mutex with Read/Write Variables

14

The read/write mutex algorithms we've seen so far require a processor to access f(n) variables in the entry section even if no contention.

It would be nice to have a fast algorithm: if no competition, a processor enters CS in O(1) steps.

Even better would be an adaptive algorithm: performance depends on number of currently competing processors, not total number.

Fast Mutual Exclusion

CSCE 668Set 8: More Mutex with Read/Write Variables

15

Note that multi-writer shared variables are required to be fast.

Combine two mechanisms: provide fast entry when no contention provide no deadlock with there is

contention

Contention Detector Overview

CSCE 668Set 8: More Mutex with Read/Write Variables

16

A doorway mechanism captures a set of processors that are concurrently accessing the detector

Use a race to choose a unique one of the captured processors to "win"

Contention Detector

CSCE 668Set 8: More Mutex with Read/Write Variables

17

Uses two shared variables, door and race.Initially door = "open", race = -1.

1 race := id2 if door = "closed" then return "lose"3 else4 door := "closed"5 if race = id then return "win"6 else return "lose"

Analysis of Contention Detector

CSCE 668Set 8: More Mutex with Read/Write Variables

18

Claim: At most one processor wins the contention detector.

Why? Let K be set of procs. that read "open" from door in Line 2.

Let pj be proc. that writes to race most recently before door is first set to "closed".

No node pi other than pj can win: If pi is not in K, it loses in Line 2. If pi is in K, it writes race before pj does but

checks again (Line 5) after pj 's write and loses.

Analysis of Contention Detector

CSCE 668Set 8: More Mutex with Read/Write Variables

19

Claim: If pi executes the contention detector alone, then pi wins.

Why? Trace through the code when there is no

concurrency.

Ensuring No Deadlock

CSCE 668Set 8: More Mutex with Read/Write Variables

20

If there is concurrency, it is possible that no processor wins the contention detector.

To ensure progress: nodes that lose the contention detector

participate in an n-processor ME alg. The winner of the n-processor alg. competes

with the (potential) winner of the contention detector using a 2-processor ME alg.

Winner of 2-processor alg. can enter CS

Ensuring No Deadlock

CSCE 668Set 8: More Mutex with Read/Write Variables

21

contentiondetector

n-proc. mutex

2-proc. mutex

critical section

lose

win

play role of p0 play role of p1

Discussion of Fast Mutex

CSCE 668Set 8: More Mutex with Read/Write Variables

22

Be careful about the exit section: contention detector needs to be reset properly

This is a modular presentation: doesn't specify particular n-proc and 2-proc subroutine mutex algorithms

Not adaptive: even if only 2 procs are contending, execute the potentially expensive n-proc algorithm