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CS222: Processor Design
Dr. A. Sahu
Dept of Comp. Sc. & Engg.Dept of Comp. Sc. & Engg.
Indian Institute of Technology Guwahati
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Outline• Previous Class:
– Floating points: Add Sub Mul Div Rounding– Floating points: Add, Sub, Mul,Div, Rounding
• Processor Design: Introduction– building blocks– building blocks
• A simple implementation: Single Cycle– Data path and controlData path and control
• Performance considerations• Multi‐cycle designMulti cycle design
– Data path and control• Micro‐programmed controlp g• Exception handling
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FP numbers with base = 2FP numbers with base 2
( 1)S x F x 2E(‐1)S x F x 2ES = SignF = Fraction (fixed point number)usually called Mantissa or Significand
E = Exponent (positive or negative integer)
• How to divide a word into S, F and E?• How to represent S, F and E?
Value Range for FValue Range for F
Single precision numbersSingle precision numbers
1 ≤ F ≤ 2 ‐ 2‐23 or 1 ≤ F < 2
Double precision numbersDouble precision numbers
1 ≤ F ≤ 2 ‐ 2‐52 or 1 ≤ F < 2
These are “normalized”These are normalized .
Value Range for EValue Range for E
Single precision numbersSingle precision numbers
‐126 ≤ E ≤ 127 (all 0’s and all 1’s have special meanings)
Double precision numbersDouble precision numbers
‐1022 ≤ E ≤ 1023 ( ll 0’ d ll 1’ h i l i )(all 0’s and all 1’s have special meanings)
Overflow and underflowOverflow and underflow
largest positive/negative number (SP) = g p / g ( )±(2 ‐ 2‐23) x 2127 ≅ ± 2 x 1038
smallest positive/negative number (SP) = p / g ( )± 1 x 2‐126 ≅ ± 2 x 10 ‐38
Largest positive/negative number (DP) = ±(2 ‐ 2‐52) x 21023 ≅ ± 2 x 10308( )
Smallest positive/negative number (DP) = ± 1 x 2‐1022 ≅ ± 2 x 10 ‐308
Expressible NumbersExpressible Numbers
Distribution of Values
• 6‐bit IEEE‐like format3 bi– e = 3 exponent bits
– f = 2 fraction bits
– Bias is 3
• Notice how the distribution gets denser toward zero. -15 -10 -5 0 5 10 15
Denormalized Normalized InfinityDenormalized Normalized Infinity
Distribution of Values( l i )(close‐up view)
• 6‐bit IEEE‐like format6 bit IEEE like format– e = 3 exponent bits– f = 2 fraction bitsBi i 3– Bias is 3
-1 -0.5 0 0.5 1Denormalized Normalized Infinity
Floating point operations: ADDFloating point operations: ADD• Add/subtract A = A1 ± A2
[(‐1)S1 x F1 x 2E1]± [(‐1)S2 x F2 x 2E2]suppose E1 > E2, then we can write it aspp ,
[(‐1)S1 x F1 x 2E1]± [(‐1)S2 x F2’ x 2E1]where F2’ = F2 / 2E1‐E2where F2 = F2 / 2 ,
Th lt iThe result is
(‐1)S1 x (F1 ± F2’) x 2E1
It may need to be normalized
Floating point operationsFloating point operations
• MultiplyMultiply
[(‐1)S1 x F1 x 2E1] x [(‐1)S2 x F2 x 2E2]= (‐1)S1⊕S2 x (F1xF2) x 2E1+E2
Since 1 ≤ (F1xF2) < 4,( ) ,the result may need to be normalized
Float MultiplicationFloat MultiplicationS ig n E x p o n e n t S ig n if i c a n d S ig n E x p o n e n t S ig n if i c a n d
S m a l l A L U
E x p o n e n t�d i f fe r e n c e
C o m p a r e �e x p o n e n t s ��
0 10 1 0 1
C o n t r o l S h if t r ig h t S h i f t s m a l le r �n u m b e r r ig h t ��
B ig A L U
0 10 1
A d d
S h i f t l e f t o r r ig h t
R o u n d in g h a r d w a r e
In c r e m e n t o r �d e c r e m e n t N o r m a liz e
R o u n d
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S ig n E x p o n e n t S ig n if ic a n d
Floating point operationsFloating point operations
• DivideDivide
[(‐1)S1 x F1 x 2E1]÷ [(‐1)S2 x F2 x 2E2]
= (‐1)S1⊕S2 x (F1 ÷ F2) x 2E1‐E2
Since 5 < (F1 ÷ F2) < 2Since .5 < (F1 ÷ F2) < 2,
the result may need to be normalized
(assume F2 ≠ 0)
Testing Associatively with FPTesting Associatively with FP
• X= ‐1 5x1038 Y=1 5x1038 z=1 0X= 1.5x10 , Y=1.5x10 , z=1.0
• X+(Y+Z) = ‐1.5x1038 + (1.5x1038 + 1.0)
038 038= ‐1.5x1038 + 1.5x1038
=0
• (X+Y)+Z = (‐1.5x1038 + 1.5x1038 ) + 1.0
= 0 0 + 1 0 0.0 + 1.0
=1
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AccuracyAccuracy
• Precision is lost when some bits are shifted toPrecision is lost when some bits are shifted to right of the rightmost bit or are thrown
• Three extra bits are used internally• Three extra bits are used internally ‐
G (guard), R (round) and S (sticky)– G and R are simply the next two bits after LSB
– S = 1 iff any bit to right of R is non‐zero
1101011010110001011011011101011010110001011011011 GRS1101011010110001011011011101011010110001011011011. GRS
Rounding using G, R and SRounding using G, R and S
• if G=1 & R=1 add 1 to LSB• if G=1 & R=1, add 1 to LSB• if G=0 & R=0 or 1, no changeg• if G=1 & R=0, look at S
– if S=1, add 1 to LSB– if S=0, round to the nearest “even”if S 0, round to the nearest even
i.e., add 1 to LSB if LSB = 1
FP instructions in MIPSFP instructions in MIPS• 32 floating point registers $f0 . . $f31Si l i i i h i• Single precision arithmetic– add.s, sub.s, mul.s, div.s, abs.s, neg.s
• Double precision arithmetic (similar)
• Conditional branch– bc1t, bc1f, c.lt.s, c.lt.d (lt|le|gt|ge|eq|ne)
• Conversion– cvt.d.s, cvt.d.w, cvt.s.d, cvt.s.w, cvt.w.d, cvt.w.s
Processor DesignProcessor Design• Introduction
– building blocks
• A simple implementation– data path and control
• Performance considerations• Multi‐cycle design
– data path and control
• Micro‐programmed control• Exception handlingp g
Simple Processor DesignSimple Processor Design
• MIPS subset for implementationMIPS subset for implementation
• Design overview
i i i i d h d l• Division into data path and control
• Building blocks ‐ combinational and sequential
• Clock and timings
• Components required for MIPS subsetComponents required for MIPS subset
MIPS subset for implementationMIPS subset for implementation
• Arithmetic ‐ logic instructionsg
–add, sub, and, or, slt• Memory reference instructions• Memory reference instructions
–lw, swC t l fl i t ti• Control flow instructions
–beq, jIncremental changes in the design to include other instructions will be discussed later
Generic ImplementationGeneric Implementation
• Use the program counter (PC) to supply p g ( ) pp yinstruction address
• Get the instruction from memoryy
• Read registers
• Use the instruction to decide exactly what to• Use the instruction to decide exactly what to do
Design overviewDesign overview
InstructionMemory
Data
PC
Memory
Address
Instruction Register FILE
AddressReg#
Reg#Data
Memory ALU
Address FILEReg#
Reg#
Data
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Division into Data path and ControlDivision into Data path and Control
DATA PATH
controlsignals
statussignals
CONTROLLER
signals signals
Building block typesBuilding block types
Two types of functional units:Two types of functional units:• Elements that operate on data values (combinational)(combinational)– Output is function of current input– No memoryy
• Elements that contain state (sequential)– Output is function of current and previous inputsOutput is function of current and previous inputs– State = memory
Combinational circuit examplesCombinational circuit examples
• Gates: and or nand nor xor inverter• Gates: and, or, nand, nor, xor, inverter• Multiplexerp
• Decoder• Adder, subtractor, comparator
• ALU• ALU• Array multipliers
Sequential circuit examplesSequential circuit examples
• Flip flops• Flip‐flops• CountersCounters
• Registers• Register files• Memories
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