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CS-EE 481 Spring 2005 1 University of Portland School of Engineering Project Golden Mantle CMOS 8-Bit Analog-to-Digital Converter Team Travis T Tompkins Aaron K Krizek Scott O Ostrow Advisor Dr. Joe Hoffbeck Dr. Peter Osterberg Industry Representative Mr. Howard Voorheis

CS-EE 481 Spring 2005 1 University of Portland School of Engineering Project Golden Mantle CMOS 8-Bit Analog-to-Digital Converter Team T Travis Tompkins

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CS-EE 481 Spring 2005

1

University of Portland School of Engineering

Project Golden MantleCMOS 8-Bit Analog-to-Digital

Converter

TeamTravis TTompkins

Aaron KKrizek

Scott OOstrow

AdvisorDr. Joe Hoffbeck

Dr. Peter Osterberg

Industry RepresentativeMr. Howard Voorheis

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University of Portland School of Engineering

Overview

• Introduction • Accomplishments• Plans• Issues/Concerns• Demo• Conclusions

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University of Portland School of Engineering

Introduction• 8-Bit Analog-to-Digital Converter

“Tracking” ADC

Architecture

CS-EE 481 Spring 2005

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University of Portland School of Engineering

Introduction continued

• Continuous time signal “coded” into stream of binary numbers

• Key component in communication systems- Cell Phones, Satellite Transmission, Digital Signal Processing

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University of Portland School of Engineering

Accomplishments

• Theory of Operations and Approval Meeting

• Layout determined

• Solved CMOS/Macro Model cross connection problem

• Core Components of Macro Model tested

• Tracked AC and DC signals

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University of Portland School of Engineering

Pictures

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University of Portland School of Engineering

MOSIS CHIPBonding pads: 40

Layout size: 2200 x 2200 microns;

Area: 4.836 sq mm

Packaging: DIP40

Maximum die size: 7366 x 7366

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University of Portland School of Engineering

Bill of MaterialsPart Description Supplier Part Number Manufacturer Quantity Unit Cost Total Cost

IC 8-bit DAC 16-DIP Digikey TLC7524IN Analog Devices 2 $3.53 $7.06

IC Quad Op Amp 14-DIP Digikey 296-1391-5-ND Texas Instruments 4 $0.45 $1.80

IC AMP MONO SAMPLE & HOLD 8-DIP Digikey LF398N-ND National Semiconductor 2 $2.08 $4.16

IC 8-bit Bi-directional Counter 24-DIP Digikey 74F269SPC-ND Fairchild Semiconductor 2 $1.98 $3.96

IC 8-bit Read Back Latch 24-Dip Digikey 296-1507-5-ND Texas Instruments 2 $8.00 $16.00

IC Precision High-Speed Comparator 8-DIP Digikey AD790JN-ND Analog Devices 3 $8.16 $24.48

Oscillator Full Size 1Mhz Digikey CTX139-ND CTS Frequency Controls 2 $2.78 $5.56

Resistors, Carbon Film, 1/4W, 5% Digikey RS125-ND Yageo 1 $14.95 $14.95

Wire Wrap Board U of P - Salvage 1 $0.00 $0.00

Metal Case Enclosure Digikey HM617-ND 1 $13.43 $13.43

Audio Jack Mono 2.5mm Panel Mount Digikey CP-2505-ND CUI Inc 2 $0.93 $1.86

Potentiometer, 200K, 1/2 Watt Digikey 490-2078-ND Murata Electronics, N.A. 2 $0.89 $1.78Potentiometer, 100K, 1/2 Watt Digikey 490-2072-ND Murata Electronics, N.A. 2 $0.89 $1.78Potentiometer, 50K, 1/2 Watt Digikey 490-2065-ND Murata Electronics, N.A. 2 $0.89 $1.78Potentiometer, 25K, 1/2 Watt Digikey 490-2083-ND Murata Electronics, N.A. 2 $0.89 $1.78Banana Plug Patch Cord, 3ft, Red/Black Fry's Elec B-36-02 Pomona Electronics 1 $7.49 $7.49Mini-Super Brite LEDs, 25 Qty, 3V Fry's Elec B4303F1 Linrose 1 $6.69 $6.69

Parts Costs $114.56Shipping $5.00

Total $119.56

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University of Portland School of Engineering

Plans

• Individual Component Testing

• Prototype Integration

• Begin Wire-Wrap Phase

• Develop Logic to Prevent Looping in Macro Model

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University of Portland School of Engineering

Milestone TableNumber Description Original Previous Present

1 Product Pre-Approval 09/08/04 09/08/04 09/08/04

2 Functional Spec Approval v1.0(Approval Meeting)

10/08/04 10/08/04 10/11/04

3 Project Plan Approval v1.0(Approval Meeting)

11/05/04 11/08/04 11/08/04

6 *.tpr File Completion 11/24/04 11/24/04 11/24/04

7 Off-chip Components Ordered 12/03/04 12/03/04 12/03/04

8 Design Release(Approval Meeting)

12/06/04 12/06/04 12/15/04

9 TOP’s Approval v1.0(Approval Meeting)

02/11/05 02/11/05 02/11/05

10 Chip Received From MOSIS 03/15/05* 03/15/05* 03/15/05*

11 Prototype Release 04/08/05 04/08/05 04/08/05

12 Founder’s Day Presentation 04/12/05 04/12/05 04/12/05

13 Final Report 04/22/05 04/22/05 04/22/05

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University of Portland School of Engineering

Concerns/Issues

• Timing Violations

• Wire Wrap Techniques

• Arrival of CMOS chip

• Logic to prevent looping in Macro Model

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University of Portland School of Engineering

Detail: Timing Violation

Solution

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University of Portland School of Engineering

Demo

• Tracking Demo

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University of Portland School of Engineering

Conclusions

• Introduction

• Accomplishments

• Plans

• Issues/Concerns

• Demo