CS 7960-4 Lecture 24

Exceeding the Dataflow Limit via Value Prediction

M.H. Lipasti, J.P. ShenProceedings of MICRO-29

December 1996

Dependences

Value Locality

Avg. accuracy 49%

Avg. accuracy 61%

Value Predictor

CT Design

VP Microarchitecture

• Value prediction happens at dispatch

• Results are immediately bypassed to dependents, but predicted instrs also go thru the pipeline

• Dependents remain in issueq until verification

• Predicted and verified results have to be broadcast to the issue queue

Verifier

• Similarities with pre-execution – a speculative thread and a verifier thread

• Dependent instructions can produce results instantaneously, but verifier executes in sequence

• Verification takes a cycle – can slow the verification thread and slows the squashing process

• Verification increases contention for resources and issue queue occupancy

Dependent Instructions

Completed: t+1Verified: t+9

Completed: t+4Verified: t+10

Completed: t+1Verified: t+10

Completed: t+8

Completed: t+9Completed: t+9

Completed: t+1V-completed: t+8Verified: t+9

Completed: t+4Verified: t+10V-completed: t+13

Completed: t+1Verified: t+10

No prediction

Correct prediction

Incorrect prediction

Configurations

Results

• Bullet

Infinite Processor Model

• Bullet

Limitations: branch prediction, fetch, store bandwidth, verifier thread

Efficient Use of Transistors

• Bullet

Future Work

• Better predictions, hit rates, strides

• Value prediction for critical instructions/high confidence predictions

• Speculation along multiple paths in the value space

• Value prediction for stores

Power Implications

• Increased activity increased power consumption

• Higher performance potentially lower energy (reduced clock distribution energy)

Next Class’ Paper

• “Energy Efficient Co-Adaptive Instruction Fetch and Issue”, A. Buyuktosunoglu, T. Karkhanis, D. H. Albonesi, P. Bose, Proceedings of ISCA-30, June, 2003

Title

• Bullet