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cs 61C L21 muldiv.1 Patterson Spring 99 ©UCB
CS61C Finishing the Datapath:
Subtract, Multiple, Divide
Lecture 21
April 14, 1999
Dave Patterson (http.cs.berkeley.edu/~patterson)
www-inst.eecs.berkeley.edu/~cs61c/schedule.html
cs 61C L21 muldiv.2 Patterson Spring 99 ©UCB
Outline°Review Datapath, ALU
° Including subtract in a 32-bit ALU
°Review Binary Multiplication
°Administrivia, “What’s this Stuff Good For”
°Multiplier
°Review Binary Division
°Divider
°Conclusion
cs 61C L21 muldiv.3 Patterson Spring 99 ©UCB
Review 1/5: Steps in Executing MIPS Subset
1) Fetch Instruction and Increment PC
2) Read 1 or 2 Registers
3) Mem-ref: Calculate Address Arith-log: Perform Operation Branch: Compare if operands ==
4) Load: Read Data from Memory Store: Write Data to Memory Arith-og: Write Result to Register Branch: if operands ==, Change PC
5) Load: Write Data to Register
cs 61C L21 muldiv.4 Patterson Spring 99 ©UCB
Review 2/5 : A Datapath for MIPS
DataCache
PC Registers ALU
Data In Data Out
InstructionCache
AddressData Out
Address Data OutData In
Step 1 Step 2 Step 3 (Step 4)
(Step 4,5)
cs 61C L21 muldiv.5 Patterson Spring 99 ©UCB
Review 3/5: Hardware Building Blocks
CASymbol
AND Gate
CAB
OR Gate
AB
C
SymbolA B C0 0 00 1 01 0 01 1 1
DefinitionA B C0 0 00 1 11 0 11 1 1
DefinitionSymbol
Inverter
A C0 11 00 0
Definition
C
SymbolMultiplexor
D C0 A1 B0 0
Definition
A
B
0
1
D
cs 61C L21 muldiv.6 Patterson Spring 99 ©UCB
Review 4/5: Add 1-bit Adder to 1-bit ALU
°Now connect 32 1-bit ALUs together
Op
Op C0 A and B1 A or B
2 A + B + CarryIn
DefinitionCarryIn
CarryOut
AB
C
0
1
2+
cs 61C L21 muldiv.7 Patterson Spring 99 ©UCB
Review 5/5: 32-bit ALU°Connect CarryOuti to CarryIni+1
°Connect 32 1-bit ALUs together
°Connect Op to all 32 bits of ALU
A0
B0C0
0
1
2+
A1
B1C1
0
1
2+
A31
B31C31
0
1
2+
...
CarryIn Op
°Does 32-bit And, Or, Add
°What about subtract?
cs 61C L21 muldiv.8 Patterson Spring 99 ©UCB
2’s comp. shortcut: Negation (Lecture 7)° Invert every 0 to 1 and every 1 to 0, then add 1 to the result•Sum of number and its inverted rep. (“one’s complement”) must be 111...111two
• 111...111two= -1ten
• Let x mean the inverted representation of x
• Then x + x = -1 x + x + 1 = 0 x + 1 = -x
°Example: -4 to +4 to -4x : 1111 1111 1111 1111 1111 1111 1111 1100two
x : 0000 0000 0000 0000 0000 0000 0000 0011two
+1: 0000 0000 0000 0000 0000 0000 0000 0100two
() : 1111 1111 1111 1111 1111 1111 1111 1011two
+1: 1111 1111 1111 1111 1111 1111 1111 1100two
cs 61C L21 muldiv.9 Patterson Spring 99 ©UCB
How Do Subtract?°Suppose added input to 1-bit ALU that gave the one’s complement of B
°What happens if set CarryIn0 to 1 in 32-bit ALU?• 32-bit Sum = A + B + 1
°Then if select one’s complement of B (B), Sum isA + B + 1 = A + (B + 1) = A + (-B) = A - B
° If modify 1-bit ALU, can do Subtract as well as And, Or, Add
cs 61C L21 muldiv.10 Patterson Spring 99 ©UCB
1-bit ALU with Subtract Support
Op
Definition
CarryIn
CarryOut
A
B C
0
1
2+0
1
Binvert
Binvert Op C0 0 A and B1 0 A and B0 1 A or B1 1 A or B0 1 A + B + CarryIn1 1 A + B + CarryIn
cs 61C L21 muldiv.11 Patterson Spring 99 ©UCB
32-bit ALU
...
CarryIn Op
A0
B0 C0
0
1
2+01
A1
B1 C1
0
1
2+01
A31
B31 C31
0
1
2+01
Binvert
°32-bit ALU made from AND gates, OR gates, Inverters, Multiplexors
°Performs 32-bit AND, OR,Add,Sub (2’s complement)
°Op, Binvert, CarryIn are control lines; control datapath
...
cs 61C L21 muldiv.12 Patterson Spring 99 ©UCB
MULTIPLY: From Lecture 9°Paper and pencil example:
Multiplicand 1000Multiplier 1001
1000 0000 0000
1000 Product 01001000
•m bits x n bits = m+n bit product
°MIPS: mul, mulu puts product in pair of new registers hi, lo; copy by mfhi, mflo • 32-bit integer result in lo
cs 61C L21 muldiv.13 Patterson Spring 99 ©UCB
MULTIPLY
°Binary multiplication is easy:•0 place 0 ( 0 x multiplicand)
•1 place a copy ( 1 x multiplicand)
•Shift the multiplicand left before adding to product
°3 versions of multiply hardware & algorithm: •Successive refinement to get to real version
•Go into first version in detail, give idea of others
cs 61C L21 muldiv.14 Patterson Spring 99 ©UCB
Product
Shift-add multiplier (version 1) 64-bit Multiplicand reg, 64-bit ALU,
64-bit Product reg, 32-bit Multiplier reg
Multiplier
Multiplicand
64-bit ALU
Shift Left
Shift Right
Write
32 bits
64 bits
64 bits
Multiplier = datapath + control
Control
100010011000
0000 0000
1000 01001000
cs 61C L21 muldiv.15 Patterson Spring 99 ©UCB
1. TestMultiplier0
31nd repetition?
3. Shift the M’plier register right 1 bit
2. Shift the M’cand register left 1 bit
1a. Add multiplicand to product & place the result in Product register
Shift-Add Multiply Algorithm V. 1
Product M’plierM’cand
0000 0000 0011 0000 00100000 0010 0001 0000 01000000 0110 0000 0000 10000000 0110 0000 0001 0000 0000 0110 Done
Yes: 32 repetitions
No: < 32 repetitions
Multiplier0 = 0Multiplier0 = 1
cs 61C L21 muldiv.16 Patterson Spring 99 ©UCB
Administrivia°Project 5: Due today
°Next Readings: 3.12, 4.9•Optional: Appendix D “An Alternative to RISC: the Intel 80x86,” Computer Architecture, A Quantitative Approach, 2/e
•Optional: RISC Survey (including HP ISA) ftp://mkp.com/COD2e/Web_Extensions/survey.htm
°9th homework: Due Friday (Ex. 7.35, 4.24)
°10th homework: Due Wednesday 4/21 7PM•Exercises 4.43, 3.17 (assume each instruction takes 1 clock cycle, performance = no. instructions executed * clock cycle time, ignore CPI comment)
cs 61C L21 muldiv.17 Patterson Spring 99 ©UCB
Administrivia: Rest of 61CF 4/16 Intel x86, HP instruction sets; 3.12, 4.9
W 4/21 Performance; Reading sections 2.1-2.5F 4/23 Review: Procedures, Variable Args(Due: x86/HP ISA lab, homework 10)
W 4/28 Processor Pipelining; section 6.1F 4/30 Review: Caches/TLB/VM; section 7.5(Due: Project 6-sprintf in MIPS, homework 11)
M 5/3 Deadline to correct your grade record
W 5/5 Review: Interrupts/PollingF 5/7 61C Summary / Your Cal heritage
Sun 5/9 Final Review starting 2PM (1 Pimintel)
W 5/12 Final (5PM 1 Pimintel); mds@cory
cs 61C L21 muldiv.18 Patterson Spring 99 ©UCB
“What’s This Stuff Good For?”
Will computers help us utilize untapped physical potential as well as intellectual potential?
Aquanex system Swimmers looking for an edge over the competition can now use tiny half-ounce sensors that give them instant feedback on their power and their stroke rate, length and velocity, shown as real-time performance graphs generated by the PC. Unlike most, this swimmer generates more arm power in his butterfly than in his freestyle. "If he learns to apply that strength to his freestyle, he'll almost certainly decrease
his time." One Digital Day, 1998www.intel.com/onedigitalday
cs 61C L21 muldiv.19 Patterson Spring 99 ©UCB
Observations on Shift-Add Multiply V.1
°1/2 bits in multiplicand always 0=> 64-bit adder is wasted
°0’s inserted in left of multiplicand as shifted=> least significant bits of product never changed once formed
°Instead of shifting multiplicand to left, shift product to right?
cs 61C L21 muldiv.20 Patterson Spring 99 ©UCB
Multiplier
Product
Shift-add Multiplier Version 2 (v. slide 14)
°32-bit Multiplicand reg, 32-bit ALU, 64-bit Product reg, 32-bit Multiplier reg
Multiplicand
32-bit ALU
Shift Right
Write
Control
32 bits
32 bits
64 bits
Multiplier = datapath + control
Shift Right
cs 61C L21 muldiv.21 Patterson Spring 99 ©UCB
Product
Shift-Add Multiplier Version 3°Product reg. wastes space that exactly
matches size of Multiplier reg combine Multiplier reg and Product reg “0-bit” Multiplier reg
(M’plier)
Multiplicand
32-bit ALU
Write
Control
0 bits
32 bits
64 bits
Multiplier = datapath + control
Shift Right
cs 61C L21 muldiv.22 Patterson Spring 99 ©UCB
Divide: From Lecture 9 1001 Quotient
Divisor 1000 1001010 Dividend –1000 10 101 1010 –1000 10 Remainder
(or Modulo result)
Dividend = Quotient x Divisor + Remainder
°See how big a number can be subtracted, creating quotient bit on each step
•Binary 1 * divisor or 0 * divisor
cs 61C L21 muldiv.23 Patterson Spring 99 ©UCB
Remainder
DIVIDE HARDWARE Version 1
64-bit Divisor reg, 64-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg
Divisor
64-bit ALU
Shift Right
Shift Left
Write Control
32 bits
64 bits
64 bits
1001 1000 1001010
–100010
101 1010 –1000
10
°Put Dividend into Remainder to start, collect Quotient 1 bit at a time
Quotient
cs 61C L21 muldiv.24 Patterson Spring 99 ©UCB
Test Remainder
No: < n+1 repetitions
2b. Restore the original value by adding the Divisor register to the Remainder register, and place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0
Divide Algorithm V. 1
Remainder < 0Remainder ≥ 0
1. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register.
2a. Shift the Quotient register to the left setting the new rightmost bit to 1
3. Shift the Divisor register right1 bit
Done
Yes: n+1 repetitions (n = 4 here)
Start: Place Dividend in Remainder
n+1repetition?
cs 61C L21 muldiv.25 Patterson Spring 99 ©UCB
Example Divide Algorithm V. 1°Takes n+1 steps for n-bit Quotient & Rem.
Remainder Quotient Divisor (-Divisor)0000 0111 0000 0010 0000 (1110 0000)
1 1110 0111 2b 00003 0000 0111 0001 0000 (1111 0000)
1 1111 0111 2b 00003 0000 0111 0000 1000 (1111 1000)
1 1111 1111 2b 00003 0000 0111 0000 0100 (1111 1100)
cs 61C L21 muldiv.26 Patterson Spring 99 ©UCB
Example Divide Algorithm V. 1 (cont’d) Remainder Quotient Divisor (-Divisor)0000 0111 0000 0000 0100 (1111 1100)
1 0000 0011 2a 00013 0000 0011 0000 0010 (1111 1110)
1 0000 0001 2a 00113 0000 0001 0000 0001 (1111 1111)
° Original division of 0111two (7) by 0010two (2) gives a quotient of 0011two (3)
plus a remainder of 0001two (1)
cs 61C L21 muldiv.27 Patterson Spring 99 ©UCB
Observations on Divide Version 1
°1/2 bits in divisor always 0=> 1/2 of 64-bit adder is wasted => 1/2 of divisor is wasted
° Instead of shifting Divisor to right, shift Remainder to left?
cs 61C L21 muldiv.28 Patterson Spring 99 ©UCB
Remainder
DIVIDE HARDWARE Version 2 (v. slide 28)
°32-bit Divisor reg, 32-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg
Divisor
32-bit ALUShift Left
WriteControl
32 bits
64 bits Shift Left
Quotient
cs 61C L21 muldiv.29 Patterson Spring 99 ©UCB
(Quot.)Remainder
DIVIDE HARDWARE Version 3
°Eliminate Quotient register by combining with Remainder as shifted left 32-bit “0-bit” Quotient reg
Divisor
32-bit ALU
WriteControl
0-bits
32 bits
64 bits Shift Left
cs 61C L21 muldiv.30 Patterson Spring 99 ©UCB
Multiplicand/Divisor
Product/Remainder
Product/Quotient
Multiply, Divide Algorithms Explain MIPS
°mul puts product in pair of regs hi, lo; • 32-bit integer result in lo
°MIPS: div, divu puts Remainer into hi, puts Quotient into lo
32-bit ALU
WriteControl
32 bits
64 bitsShift
Hi Lo
cs 61C L21 muldiv.31 Patterson Spring 99 ©UCB
A Revised Datapath for MIPS
DataCache
PC Registers ALUInstruction
Cache
Step 1 Step 2
Steps 3-19
(Step 4)
(Step 4, 5)
X,/ Hi, Lo
registers
Step 3
cs 61C L21 muldiv.32 Patterson Spring 99 ©UCB
“And in Conclusion..” 1/1°Subtract included to ALU by adding one’s
complement of B
°Multiple by shift and add
°Divide by shift and subtract, then restore by add if didn’t fit
°Can Multiply, Divide simply by adding 64-bit shift register to ALU
°MIPS allows multiply, divide in parallel with ALU operations
°Next: Intel and HP Instruction Set Architectures