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    CS 6135 VLSI Physical Design Automation

    Fall 2003

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    Course Information

    • Class time: R789

    • Location: EECS 224

    • Instructor: Ting-Chi Wang (���) EECS 643, (03) 5742963

    tcwang@cs.nthu.edu.tw

    • Office hours: M56R5 or by appointment

    • Web site: www.cs.nthu.edu.tw/~tcwang/cs6135.html

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    Course Information (Cont’d)

    • Material: technical papers selected from major EDA (Electronic Design Automation) conference proceedings and journals

    • Grading Policy: Homework: 40%

    One test: 30%

    One project: 30%

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    Project

    • Pick a research-oriented problem (either an existing one or a pioneering one) in the physical design area. Develop and implement your own algorithm(s); do comparative studies with other existing methods (if there are any).

    • Schedule – 1-page proposal due: November 20, 2003 – project presentation: to be determined – report due: January 5, 2004

    • You are always welcome to discuss with me about your project during office hours or by appointment.

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    Physical Design

    • Physical design is the process of converting a circuit netlist into a geometric description (i.e., determining where to put components and how to connect them).

    • The description is used to manufacture a chip. • Objectives: area, performance, and power, etc.

    • Constraints: components may not be too close, and wires cannot cross, etc.

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    Computer-Aided Design (CAD)

    • Physical design is very complicated:

    – Millions of components

    – Multiple objectives

    – Multiple constraints

    • Chip designers need help from CAD tools.

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    Course Objectives

    • Understanding the problems arising in the physical design of VLSI circuits.

    • Understanding various CAD algorithms for automating the physical design process.

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    Course Topics

    • Introduction

    • Partitioning

    • Floorplanning & Placement

    • Routing

    • Other topics

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    Target Audience

    Students who want to be:

    • VLSI CAD Engineers & Researchers

    – Development and Implementation of CAD tools

    • VLSI Designers

    – Designing VLSI chips using CAD tools

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    Expected Background

    • Digital Systems

    • Algorithms (or Data Structures)

    • Programming Languages such as C or C++

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    Related Conferences/Journals • Major Conferences:

    - IEEE/ACM Int’ l Conference on Computer-Aided Design (ICCAD) - ACM/IEEE Design Automation Conference (DAC) - ACM Int’ l Symposium on Physical Design (ISPD) - Asia and South Pacific Design Automation Conference (ASP-DAC) - Design, Automation and Test in Europe (DATE) - IEEE Int’ l Symposium on Circuits and Systems (ISCAS) - ACM Int’ l Symposium on Field Programming Gate Arrays (FPGA) - Others: IEEE Int’ l Conference on Computer Design (ICCD); IEEE Custom Integrated Circuits Conference (CICC); IEEE Int’ l ASIC/SOC Conference

    • Major Journals: - IEEE Transactions on Computer-Aided Design (TCAD) - ACM Transactions on Design Automation of Electronic Systems (TODAES) - IEEE Transactions on VLSI Systems (TVLSI) - INTEGRATION: The VLSI Journal - IEEE Transactions on Circuits and Systems (TCS) - IEEE Transactions on Computers (TC)

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    Related Books

    • N. Sherwani, Algorithms for VLSI Physical Design Automation, 3rd Edition, Kluwer Academic Publishers, 1999.

    • S. M. Sait and H. Youssef, VLSI Physical Design Automation: Theory and Practice, McGraw-Hill, 1995.

    • M. Sarrafzadeh and C. K. Wong, An Introduction to VLSI Physical Design, McGraw-Hill, 1996.

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    Milestones for IC Industry • 1947: Bardeen, Brattain & Shockley invented the transistor, foundation of the IC

    industry. • 1952: SONY introduced the first transistor-based radio. • 1958: Kilby invented integrated circuits (ICs). • 1965: Moore’s law. • 1968: Noyceand Moore founded Intel. • 1971: Intel announced 4-bit 4004 microprocessors (2300 transistors). • 1976/81: Apple/IBM PC. • 1985: Intel began focusing on microprocessor products. • 1987: TSMC was founded. • 1991: ARM introduced its first embeddable RISC IP core. • 1996: Samsung introduced 1G DRAM. • 1998: IBM Austin Res. Lab announced 1GHz experimental microprocessor. • 1999/earlier: System-on-chip (SOC) methodology/applications. • Intel P-III has 10 million transistors. • Semiconductor/IC: #1 key field for advancing into 2000 (Business Week, Jan.

    1995).

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    VLSI Design Considerations

    • Several conflicting considerations � Design complexity: large number of devices/transistors � Performance: optimization requirements for high performance � Time-to-market: about a 15% gain for early birds � Cost: die area, packaging, testing, etc � Others: power consumption, noise, reliability, etc

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    Moore’s Law: Predicting Technology Trends

    • Logic capacity doubles per IC at regular intervals (1965).

    • Logic capacity doubles per IC every 18 months (1975).

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    Semiconductor Technology Roadmap

    • Source: Semiconductor Industry Association (SIA), USA, Nov. 1999. http://www.itrs.net/ntrs/publntrs.nsf.

    • Deep submicron technology: node (feature size) < 0.25 ��. • Current design challenges: complexity (devices & interconnects), noise, power, SOC

    methodology, test, timing & function verification. • Additional challenges beyond 2005: 3D layout, signal skew, design convergence,

    embedded system, system test, heterogeneous system verification.

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    Problems with Future Technology

    • Designs are too complicated to be handled manually

    • Solutions:

    – CAD

    – Hierarchical design

    – Design reuse

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    Traditional VLSI Design Cycle

    • 1. System specification • 2. Functional design • 3. Logical synthesis • 4. Circuit design • 5. Physical Design • 6. Fabrication • 7. Packaging • Other tasks involved: function/timing

    verification, etc.

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    Traditional VLSI Design Flow

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    Traditional VLSI Design Flow (Cont’d)

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    Tasks in Physical Design

    1. Circuit partitioning

    2. Floorplanning, and placement

    3. Routing (global and detailed)

    4. Compaction

    5. Extraction and Verification

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    Physical Design Flow

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    Design Styles

    • Restricting design styles to reduce complexity.

    • Choosing design style according to

    design time, performance, size and cost, etc.

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    Design Styles (Cont’d)

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    Design Styles (Cont’d) • Full-Custom

    – Without any constraints • Standard Cell

    – A library of cells of equal height – A design consisting of rows of cells

    • Gate Array – A design consisting of an array of identical pre-

    fabricated gates/cells – Routing layers being fabricated on top of the wafer

    • Field Programmable Gate Array (FPGA) – Pre-fabricated cells and interconnects – Programmable cells and interconnects

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    SSI/SPLD Design Style

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    Full Custom Design Style

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    Standard Cell Design Style

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    Gate Array Design Style

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    FPGA Design Style

    • Illustrated by a symmetric array-based FPGA:

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    FPGA Design Process • Illustrated by a symmetric array-based FPGA:

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    Comparisons of Design Styles

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    Comparisons of Design Styles (Cont’d)

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    Design-Style trade-offs