Research ArticleCrypto-Stego-Real-Time (CSRT) System forSecure Reversible Data Hiding

Latika Desai and SureshMali

Dr D Y Patil Institute of Technology Savitribai Phule Pune University Pune India

Correspondence should be addressed to Latika Desai latikadesaigmailcom

Received 17 May 2018 Revised 16 August 2018 Accepted 1 September 2018 Published 27 September 2018

Academic Editor Maurizio Martina

Copyright copy 2018 Latika Desai and SureshMaliThis is an open access article distributed under the Creative Commons AttributionLicensewhichpermits unrestricteduse distribution and reproduction in anymedium provided the original work is properly cited

Due to demand of information transfer through higher speed wireless communication network it is time to think about securityof important information to be transferred Further as these communication networks are part of open channel to preservethe security of any Critical Information (CI) is really a challenging task in any real-time application Data hiding techniquesgive more security and robustness of important CI against encryption or cryptographic software solutions However hardwiredapproach exhibits better solution not only in terms of reduction of complexity but also in terms of adaptive real-time output Thispaper demonstrates frequency Discrete Cosine Transform (DCT) domain Steganographic data hiding hardware solution for secretcommunication called Crypto-Stego-Real-Time (CSRT) SystemThe challenge is to design a secure algorithm keeping reliability ofminimum distortion of original cover signal while embedding considerable amount of CI Field Programmable GateArray (FPGA)implementation shown in this paper is more secure robust and fast Pipelining process while embedding enhances the speed ofembedding optimizes the memory utilization and gives better Peak Signal to Noise Ratio (PSNR) and high robustness Practicallyimplemented hardware Steganographic solutions shown in this paper also give better performance than that of the current state-of-the-art hardware implementations

1 Introduction

In the todayrsquos Internet era there is a need of protection ofCritical Information (CI) like Personal Identification Num-ber (PIN) of Automated Teller Machine (ATM) card OneTime Password (OTP) bank transactions etc while com-municating CI in open channel system (internet) To avoidunauthorized access one can encrypt CI itself before it actu-ally gets transferred from one location to another Howeversuch encrypted CI is still specifically available to any hackerand will be in a position to extract CI Therefore to makehighest security of CI Steganographic data hiding techniquesare used to keep the communication of CI itself hidden fromthe hackerMany such techniques have been proposed earlierwhich comes under two categories namely spatial domainand frequency domain Most of the researchers are focusedon the software-data hiding through different approacheslike Least Significant Bit (LSB) 23 LSB n-bit LSB DCTandDiscreteWavelet Transform (DWT) Unfortunately soft-ware-data hiding techniques are generic complex and slow

Therefore these techniques are not suitable for real-timeapplications such asATMwhere uploadingauthentication cre-dentials (as CI) through Internet is always essential Authen-ticating mobile wallets online Stock trading and many morereal-time e-transactions applications are to be supported bycryptographic and steganographic security systems

Researchers are constantly trying to improve the capa-bilities of reversible Steganographic data hiding methodolo-gies in terms of parameters such as embedding capacityimperceptibility security time complexity and robustnessImplementation of embedding function (fEm) and extractionfunction (fEx)may be in either software or hardware platformHardware implementation has always offered advantagesover software realization [1] in terms of low executiontime low power consumption high reliability and real-time performance Implemented hardware can also be madecompatible with existing consumer electronics communicat-ing devices Table 1 also narrates many more advantages ofhardware approaches by [1ndash3]

HindawiVLSI DesignVolume 2018 Article ID 4804729 8 pageshttpsdoiorg10115520184804729

2 VLSI Design

Table 1 Hardware versus software based implementation of data security

Software Implementation Hardware ImplementationGeneralized design under PC environment Customized designed using FPGAs (ES)Complex Algorithms can be possible Simplified Algorithms with hardwareNot a Real time solution Real time solution with hardwareMore power requires for PC Less power required for embedded systemEasy to modify the design Difficult to modify the designMore area amp cannot execute without PC Less area amp can execute without PCNot Portable PortableThe Cost of PC OS and language support Low-cost due to specific hardware involvedLess secured More securedEasy to copy the implemented code Difficult to copy the implemented hardwareAll operations are sequential Parallel operations are possible

2 Overview of Reversible DataHiding Techniques

Reconfigurable hardware architecture supports algorithmchange andmultiple keys as well as different CI size It speedsup the process of embedding due to availability of cachememory Multiprocessor System on Chip (MPSoC) architec-tures demonstrated byMaity et al [4] exhibits high intrusionprotection It gives real-time transmission using channelcoding and biphase modulation However the computationrequirement for embedding is quite high The Adaptive Ran-dom InvertedKey (ARIK) LSB substitutionmethod proposedby Balakrishnan et al [5] using cyclone II FPGA board hasimproved performance with respect to imperceptibility ofStego However the designed architecture was operated ata frequency of 50 MHz occupies 10513 logic elements andconsumes 92 mw of power at the embedding stage Effectiveintegration of conventional cryptography encryption and Ste-ganography has been presented byMali et al [6] using Adap-tive Energy Thresholding (AET) technique The approachenhances the parameters security robustness and payloadagainst different attacks Being implemented in softwarethe approach cannot be applied in real-time environmentGomez-Hernandez et al [7] worked on context techniquesused for embedding where the loss of information duringrecovery process has been avoided using simple and repetitiveoperations with context technique However the perfor-mance would have been better with parallelism in terms ofarea and time

Mohd et al [8] demonstrate the FPGA hardware imple-mentation in spatial domain Steganography Simulation syn-thesis and analysis show that random embedding increasesutilization of LEs However spatial domain techniques arealways more vulnerable than that of frequency domain tech-niques Adaptive randomization in reconfigurable hardwarearchitecture using Integer Wavelet Transform (IWT) hasbeen proposed by Ramalingam et al [9] Although it givesPSNR up to 60 the design consumed 34 of the LEs 22of the dedicated logic register and 2 of the embeddedmultiplier on FPGA The main drawback of the IWT baseddata hiding is the computational overhead The performance

of the algorithm implemented in anFPGA-based hardware byMohd et al [10] has been examined with respect to resourceutilization timing and energy Because of higher complexcomputation the implementation has a higher cost and slow-er speed

The spatial domain hardware approach has also beenintroduced by Mahmoudpour and Mirzakuchaki et al [11]through randomizations using Linear Feedback ShiftRegister(LFSR) for getting better security against attack However themaximum value of PSNR in this approach is 51217 Hard-ware platform has also been used by Rajagopala et al [12]However being a spatial domain embedding approach itis less secure and non robust even if PSNR is up to 6098Reversible Steganography spatial domain implemented usingLFSR has been demonstrated by Mahmood et al [13] Thedifferent LFSR and seeds are preferred for better securityHowever complex logic consumes more hardware and themaximum value of PSNR is 5121 for even 10 of the pay loadof embedding

The reversible data hiding implementation proposed bySundararaman et al [14] is the spatial domain approach withLFSR Five different polynomials are used for five differentcovers with different sizes Because of the limited use ofbitwise Steganographic operation this hardware approachis less secure The demonstrated approach has maximumPSNR 5127 Also Synthesis report states that for 64 x 64 sizecover LEs used are 11493 Intermediate Significant Bit (ISB)replacement technique demonstrated by Shabir et al [15]suggests a fix location for embedding Although it providescapacity up to 25 the maximum PSNR achieved due to ISBprocess is 3797 The transform domain DCT based approachfor data hiding implemented in MATLAB by Rahman et al[16] uses sequential embedding of secret bits in the LSBs ofDCT coefficients The experimental results show that the useof middle frequency DCT coefficients has given better resultsof PSNR as compared to low frequency DCT coefficientsHowever being a software implementation it is not suitablefor real-time applications

Anderson and Petitcolas [17] show that considerations ofentropy give us better results as it gives us some quantitativeleverage The embedding of information is in parity checks

VLSI Design 3

Table 2 Analysis of various data hiding techniques

Approach Imperceptibility Capacity Robustness Time ComplexitySpatial Domain[31] Medium High Low LowFrequency Domain[32] High Low High LowSpread Spectrum [33] High High Medium HighMatrix Embedding [34] High High Low MediumDifference Expansion[35] High High Low LowOptimization Technique [36] High Medium High HighHistogramModification [37] High Medium Low Low

rather than in the data directlyThis approach gives improvedefficiency and also allows us to do public key SteganographyThe Steganography approach introduced by Odeh et al [18]is a real-time hardware engine where text is embedded Bytaking care of a real-time application proposed work isfaster to maintain security in communication over InternetHowever because of lack of parallel processing the speed ofembedding is low If we consider different applications likecovert communication fingerprinting and copyright protec-tion as well as many more the most important parametersobserved are the security robustness invisibility time com-plexity and area and power dissipation Among all theseparameters security is themajor aspect and is commonly usedin all these different applications announced by Fedrich [19]

The FPGA-based microarchitecture defined by Farouk etal [20] with the secret key feature is suitable for real-timeapplication Selecting the hiding bits in a pseudorandommanner as a function of a secret key has been used to increaseobscurity The receiver needs only the modulated cover andthe secret key to recover the message ie no original cover isrequired

The importance of DCT in terms of scalability and mini-mal distortion demonstrated by Cariccia et al [21] as well asRenda et al [22] is quite noticeable Because of the abilityof DCT algorithms to produce high throughput low powerdissipation and reduced chip area with primary objective ofsecurity they are more popular amongst the researchers

Cryptographic different approaches are demonstratedthrough [23ndash29] using Virtex 5 FPGA platform While secur-ing the data with AES (Advanced Encryption Standard) aswell as Data Decryption Systems Standard (DES) and TripleDES (TDES) using FPGA different approaches are imple-mented to enhance the performance for secure communica-tion However the area utilization is varying from 260 LEsto 9276 LEs Watermarking method using DWT [30] with344329 MHz frequency has also shown considerably lessarea utilized with more delays in the process of embeddingComparison of software and hardware implementation ofsuch systems is given in Table 1 This table shows that thehardware deployment gives more speed the secrecy andthe robustness with minimum cost as compared to softwarecounterpart Brief analysis of various techniques [31ndash37] todevelop such systems is given in Table 2 The frequencydomain techniques demonstrated in [32ndash37] as well as [2122] show better performance in terms of imperceptibilitycapacity robustness and process

Analysis of the state-of-the-art techniques leads to someinteresting findings frequency domain gives high robustnessand high imperceptibility However these techniques are verycomplex and time consuming while being implemented inhardware Further data hiding Capacity Security and Ro-bustness parameters are mutually exclusive to each other andtherefore optimizing them in real-time hardware environ-ment is really a tough task The support of parallel processinghelps in compensating for the time needed for such complexcomputations

3 Proposed Methodology

Any non-Critical Information called cover data (C) acts as acarrier of Critical Information (CI) A Secrete Key (K) is usedby the Steganographic embedding function (fEm) to hide CIand gives Stego data (S) as an output (device at Transmittingend DT) as shown in

119878119863119879

997888997888rarr 119891119864119898 (119862 119862119868119870) (1)

where S is Stego data C is cover data CI is Critical Informa-tion and K is Secrete Key

The same Secrete Key (K) is used by the Steganographicextraction function (fEx) to extract CI1015840 (as a device atreceiving end DR) as shown in

1198621198681015840119863119877

997888997888rarr 119891119864119909 (119878 119870) (2)

where S is Stego data CI1015840 is Extracted Critical Informationand K is Secrete Key

Typical generalized hardware Steganographic data hidingmechanism is as shown in Figure 1

Proposed hardware based reversible data hiding system toimplement data hiding system consists of both cryptographicand Steganographic approach and therefore is called Crypto-Stego-Real-Time (CSRT) System Figure 2 outlines the pro-posed methodology

As a part of cryptography the encryption process isconverting CI from plain text into unintelligible ciphertextOn the receiving side of the process decryption is used toconvert this unintelligible ciphertext back into plaintext CI1015840as an extracted CI If CI consists of M ldquoCharactersrdquo in CIstored in the Message Cache it can be represented as

119862119868 = [1198830 1198831 1198832 119883

119872minus1 ] (3)

4 VLSI Design

E ECover Data (C)

Critical Information (CI)

Unintentional Attacks(A) or

Intentional Trapping

By Hacker (H)

Extracted Critical

Information (CIrsquo)

Secret Key (K) Secret Key (K)

Stego Data(S)

Device at Device at

fEm fEx

Transmitting end (DT) Receiving end (DR)

Figure 1 Steganographic data hiding mechanism

Reducing the Chance of Suspect

Encryption Decryption

Non-SuspiciousHacker

Sharing of Common Key (K)

CI CIrsquoSteg

anog

raph

y

Steg

anog

raph

y

Embedding ( )

Extraction( )

C

S

fEm fEx

Figure 2 Proposed Crypto-Stego-Real-Time (CSRT) System

where M is number of characters in CI stored in ldquoMessageCacherdquo at lsquoA

0to AMminus1 address locations in a sequence

The process of encryption typically carried out usingldquoRandomly Selected Set of Addressesrdquo stored in a ldquoLOOK-UP Tablerdquo is randomly selecting any address location (Am)of Message Cache and hence at any given time one of thecharacters stored in Message Cache get selected as ldquoYmrdquoand can be written as follows there is a ldquoLOOK-UP Tablerdquoconsisting of random numbers which eventually act as anaddresses to locate any random character at ldquoMessage CacherdquoObviously the number of locations in ldquoLOOK-UP Tablerdquo is 8times more than that of the number of locations in ldquoMessageCacherdquo ie 8lowastM At any given time one of the charactersstored in ldquoMessage Cacherdquo gets selected as ldquoRandomly SelectedCharacterrdquo given by

119884119898= [119860119898] = [[119871 119894]] = [[119862119899119905]] (4)

where Ym is Randomly Selected Character and Amis Ran-domly Selected Address for ldquoMessage Cacherdquo and eventuallycontent of sequential location of ldquoLOOK-UP Tablerdquo 0 to M-1excluding three ldquoLeast Significant Bitsrdquo of content of Li

The ldquoClock Generatorrdquo of CSRT selects sequential loca-tions of ldquoLOOK-UP Tablerdquo and is given as

119871119894= 119862119899119905 (5)

where Cnt is output of the COUNTER

The format of content of Li while selecting the characterand specific bit of the character is as shown in Figure 3 Asthere are 8 bits in each character the randomization is alsoapplicable to these bits

The proposed algorithm works on 8 bytes of cover at atime as follows

119862 = [1198617 1198616 1198615 119861

0] (6)

where B7to B0= 8 bytes of the cover given to CSRT at any

given time whose DCT can be written as

119863 = 119863119862119879 (119862) (7)

where D is A set of 8 DCT coefficients of 8 respective bytes ofthe cover given in (6) which can also be written as

119863 = 1198627 1198626 1198625 119862

0 (8)

where every DCT coefficient (C) consists of signed binaryrepresentationThe bit selected (shown in Figure 3) is embed-ded in C

3 Embedding of the bit in C

3is nothing but making

LSB of C3as that of bit to be embedded as

LSB of 1198623= Selected Bit of 119884

119898

= Selected Bit of [[119871 119894]](9)

VLSI Design 5

Ym

MUX

Random lsquoBITrsquoSelectionrsquo

LOOK-UP Tablelsquo8 Mrsquo

Locations

Selected BIT for Embedding

Message Cache

lsquoMrsquoBytes

Random lsquoCharacter Selectionrsquo

COUNTER

CLOCK

AddressFor

LOOK-UP

Figure 3 Randomization of characters and bits of ldquoMessage Cacherdquo

After modifying the LSB of C3inverse DCT (IDCT) of D is

taken to get Stego as follows

119878 = 119868119863119862119879 (119863) (10)

where is S is the Stego block of data consisting of 8 byteshaving an embedded bit of information in LSB of C3

4 Embedding Algorithm

(1) Accept CI into Message Cache(2) Accept LOOK-UP Table as an Embedding Key (K)(3) Accept 8-byte cover data (C)(4) Compute DCT of 8 bytes of cover data(5) Randomly select byte (Ym) fromMessage Cache(6) Select a bit using 3 LSBs of contents of selected byte

LOOK-UP Table(7) Embed the selected bit at DCT coefficient C3(8) Compute IDCT of 8 bytes of cover data to get Stego

data(9) Repeat Step-3 to Step-8 for all the bits of all the

charactersMessage Cache(10) Stop

Although there are multiple steps in the proposed algorithmit is possible to have parallel processing of Step-(3) to Step-8If we take Pre Em= Step-(3) and Step-(4) Emd = Step-(5) andStep-(6) and Post-Em = Step-(7) and Step-(8) it is possible toreduce the total time required for embedding all the bits ofMessage Cache as shown in Figure 4

5 Experimental Set Up

The logic necessary to implement the algorithm is down-loaded from the PC to Configurable FPGA board usingVirtex-5 XC5VLX50T FFG1136C Board Critical Informa-tion (CI) and Embedding Key (K) are transferred to the FPGARAMatMessage Cache and LOOK-UPTable respectivelyThecover data (C) is then transferred on byte by byte basis Afterthe embedding process it gets validated by transferring Stegodata (S) back to PCWhile extracting theCritical Information

(CI1015840) the Stego data (S) sent from the PC to FPGA board onbyte by byte basis and the extracted CIrsquo stored in FPGARAMatMessage Cache is validated by receiving it on PC

6 Result and Discussion

This section declares the analysis of different parameters likePSNR area and the time The different methodologies areexplained in the literature such as LSB MSB DWT IWTand proposed approach [CSRT] The PSNR values are shownthrough Figure 5 The proposed hardware approach gives7377 dB PSNR value which is approximately 10 more thanmentioned approaches

The analysis of the proposed hardware approach forthe area in terms of Slice Registers Slice Look-Up-Tables(LUTs) and slice LUT-FF pair used in various approaches isdemonstrated through Figures 6 7 and 8 respectively TheproposedCSRTmethod uses only 241 Slice Registers and 1202LUTs

To understand the performance speed of execution ofalgorithm of embedding of CI has been considered This timevaries from 8448 120583s to 135168120583s while embedding of CIfrom 128 bytes to 2 K bytes in 1K bytes to 16 K bytes of coverdata Figure 9 gives an idea of reduction of processing speedof the proposed CSRT method

Security of the system is very high as the cryptographicEncryption and Steganographic data hiding processes hasbeen developed in FPGA hardware Although hidden dataare reversible and can be recovered by the intended user itshould not be detectable by any hacker (most of the hackersare nonsuspicious) as shown in Figure 2 The sharing of acommon key is important for the intended extractor Thiskey may be predecided from look up table which eventuallyrandomly select the bits of the characters frommessage cachefor embedding A personwho knows the algorithm and look-up table must be the person who will be able to extract theCritical Information (CI) For example for 128 bytes of CIthere will be 1 K bytes of look-up table and the attacker has totry 21024 and check permutations and combinations of look-up table provided that the embedder knows the algorithm AsCI increases the size of the look-up table also increases andhence the permutations and combinations of look-up tableAlthough this dependability is the drawback of the system

6 VLSI Design

Pre_Em Emd Post_Em

Pre_Em Emd

Pre_Em

Post_Em

Emd Post_Em

T

Pre_Em Emd Post_Em

Figure 4 Parallel processing of steps of CSRT algorithm

436512

609 6318

7377

1 2 3 4 5

PSNR

DWT [10] LSB[8] DCT[CSRT]MSB[12] IWT[9]0

1020304050607080

PSN

R

Figure 5 PSNR with different hardware approaches

399

1206

2056

255

1105808

241

1 2 3 4 5 6 7

Slice Register Used

[23] [24] [25] [26] [28] [29] [CSRT]0

500

1000

1500

2000

2500

Slic

e Reg

ister

Use

d

Figure 6 Slice registers used with different approaches

1338 1692

3788

9276

47213557

1202

1 2 3 4 5 6 7

Number of Slice LUTs Used

[23] [24] [25] [26] [28] [29] [CSRT]0

100020003000400050006000700080009000

10000

Num

ber o

f Slic

e LU

Ts u

sed

Figure 7 Number of slice LUTs used with different approaches

VLSI Design 7

260

632

1792

161 236

748 660

1 2 3 4 5 6 7

Number of Fully used LUT-FF Pairs

[CSRT]0

200400600800

100012001400160018002000

Fully

use

d LU

T-FF

Pai

rs[23] [24] [25] [26] [28] [29]

Figure 8 Fully used slice LUT-FF pairs with different approaches

8448 1689633792

67584

135168

1 2 3 4 5128 256 512 1024 2048Critical Information (Message Bits)

0200400600800

1000120014001600

Proc

essi

ng T

ime (

s)

Figure 9 Critical Information (CI) processing time

the system is reconfigurable and therefore one can designthe look-up table of any size based on size of the CI

7 Conclusion

The Crypto-Stego-Real-Time (CSRT) System presented inthis paper is highly secured due to its implementation inhardware As the encryption of CI has been done in the hard-ware using cache memory the random addresses of cachememory are used for scribbling CI to be embedded in thecover bit by bit fashion One cannot extract CI unless hesheknows the algorithmand look-up table as a key of embeddingPipelining process while embedding enhances the speedof embedding and optimizes the memory utilization Thesystem PSNR (7377) Number of Slice LUTs used (1202)and execution time (135168 120583S for 2 K bits of CI) show anevidence of better performance in terms of throughput ofthe system The drawback of the system is its EmbeddingKey which varies with CI As CI increases the size of thekey also increases However the system is reconfigurableand therefore one can design the look-up table of any sizebased on the size of the CI The overall performance of thepresented CSRT system is better than current state-of-the-artmethods and therefore it is most suitable for any real-timeapplications

Data Availability

The data used to support the findings of this study are avail-able from the corresponding author upon request

Conflicts of Interest

The authors declare that they have no conflicts of interest

Acknowledgments

We are thankful to Dr D Y Patil Institute of TechnologyPimpri Pune for encouragement and support

References

[1] S Debnath M Kalita and S Majumder ldquoA Review on Hard-ware Implementation of Steganographyrdquo in Proceedings of theDevices for Integrated Circuit pp 149ndash152 Kalyani IndiaMarch2017

[2] M Faheem S Jamel A Hassan Z A N Shafinaz andMMatldquoA Survey on the cryptographic encryption algorithmsrdquo Inter-national Journal of Advanced Computer Science and Applica-tions vol 8 no 11 pp 333ndash344 2017

[3] httpswwwinfosecurity-magazinecommagazine-featurestales-crypt-hardware-software

[4] S P Maity and M K Kundu ldquoDistortion free image-in-imagecommunication with implementation in FPGArdquo Elsevier Inter-national Journal of Electronics and Communications vol 67 pp438ndash447 2012

[5] R Balakrishnan A Rengarajan and J B B Rayappan ldquoMulti-plexed stego path on reconfigurable hardware a novel randomapproachrdquo Elsevier Computers and Electrical Engineering vol55 pp 153ndash163 2016

[6] S N Mali P M Patil and R M Jalnekar ldquoRobust and securedimage-adaptive data hidingrdquo Digital Signal Processing vol 22no 2 pp 314ndash323 2012

VLSI Design 3

Table 2 Analysis of various data hiding techniques

Approach Imperceptibility Capacity Robustness Time ComplexitySpatial Domain[31] Medium High Low LowFrequency Domain[32] High Low High LowSpread Spectrum [33] High High Medium HighMatrix Embedding [34] High High Low MediumDifference Expansion[35] High High Low LowOptimization Technique [36] High Medium High HighHistogramModification [37] High Medium Low Low

rather than in the data directlyThis approach gives improvedefficiency and also allows us to do public key SteganographyThe Steganography approach introduced by Odeh et al [18]is a real-time hardware engine where text is embedded Bytaking care of a real-time application proposed work isfaster to maintain security in communication over InternetHowever because of lack of parallel processing the speed ofembedding is low If we consider different applications likecovert communication fingerprinting and copyright protec-tion as well as many more the most important parametersobserved are the security robustness invisibility time com-plexity and area and power dissipation Among all theseparameters security is themajor aspect and is commonly usedin all these different applications announced by Fedrich [19]

The FPGA-based microarchitecture defined by Farouk etal [20] with the secret key feature is suitable for real-timeapplication Selecting the hiding bits in a pseudorandommanner as a function of a secret key has been used to increaseobscurity The receiver needs only the modulated cover andthe secret key to recover the message ie no original cover isrequired

The importance of DCT in terms of scalability and mini-mal distortion demonstrated by Cariccia et al [21] as well asRenda et al [22] is quite noticeable Because of the abilityof DCT algorithms to produce high throughput low powerdissipation and reduced chip area with primary objective ofsecurity they are more popular amongst the researchers

Cryptographic different approaches are demonstratedthrough [23ndash29] using Virtex 5 FPGA platform While secur-ing the data with AES (Advanced Encryption Standard) aswell as Data Decryption Systems Standard (DES) and TripleDES (TDES) using FPGA different approaches are imple-mented to enhance the performance for secure communica-tion However the area utilization is varying from 260 LEsto 9276 LEs Watermarking method using DWT [30] with344329 MHz frequency has also shown considerably lessarea utilized with more delays in the process of embeddingComparison of software and hardware implementation ofsuch systems is given in Table 1 This table shows that thehardware deployment gives more speed the secrecy andthe robustness with minimum cost as compared to softwarecounterpart Brief analysis of various techniques [31ndash37] todevelop such systems is given in Table 2 The frequencydomain techniques demonstrated in [32ndash37] as well as [2122] show better performance in terms of imperceptibilitycapacity robustness and process

Analysis of the state-of-the-art techniques leads to someinteresting findings frequency domain gives high robustnessand high imperceptibility However these techniques are verycomplex and time consuming while being implemented inhardware Further data hiding Capacity Security and Ro-bustness parameters are mutually exclusive to each other andtherefore optimizing them in real-time hardware environ-ment is really a tough task The support of parallel processinghelps in compensating for the time needed for such complexcomputations

3 Proposed Methodology

Any non-Critical Information called cover data (C) acts as acarrier of Critical Information (CI) A Secrete Key (K) is usedby the Steganographic embedding function (fEm) to hide CIand gives Stego data (S) as an output (device at Transmittingend DT) as shown in

119878119863119879

997888997888rarr 119891119864119898 (119862 119862119868119870) (1)

where S is Stego data C is cover data CI is Critical Informa-tion and K is Secrete Key

The same Secrete Key (K) is used by the Steganographicextraction function (fEx) to extract CI1015840 (as a device atreceiving end DR) as shown in

1198621198681015840119863119877

997888997888rarr 119891119864119909 (119878 119870) (2)

where S is Stego data CI1015840 is Extracted Critical Informationand K is Secrete Key

Typical generalized hardware Steganographic data hidingmechanism is as shown in Figure 1

Proposed hardware based reversible data hiding system toimplement data hiding system consists of both cryptographicand Steganographic approach and therefore is called Crypto-Stego-Real-Time (CSRT) System Figure 2 outlines the pro-posed methodology

As a part of cryptography the encryption process isconverting CI from plain text into unintelligible ciphertextOn the receiving side of the process decryption is used toconvert this unintelligible ciphertext back into plaintext CI1015840as an extracted CI If CI consists of M ldquoCharactersrdquo in CIstored in the Message Cache it can be represented as

119862119868 = [1198830 1198831 1198832 119883

119872minus1 ] (3)

4 VLSI Design

E ECover Data (C)

Critical Information (CI)

Unintentional Attacks(A) or

Intentional Trapping

By Hacker (H)

Extracted Critical

Information (CIrsquo)

Secret Key (K) Secret Key (K)

Stego Data(S)

Device at Device at

fEm fEx

Transmitting end (DT) Receiving end (DR)

Figure 1 Steganographic data hiding mechanism

Reducing the Chance of Suspect

Encryption Decryption

Non-SuspiciousHacker

Sharing of Common Key (K)

CI CIrsquoSteg

anog

raph

y

Steg

anog

raph

y

Embedding ( )

Extraction( )

C

S

fEm fEx

Figure 2 Proposed Crypto-Stego-Real-Time (CSRT) System

where M is number of characters in CI stored in ldquoMessageCacherdquo at lsquoA

0to AMminus1 address locations in a sequence

The process of encryption typically carried out usingldquoRandomly Selected Set of Addressesrdquo stored in a ldquoLOOK-UP Tablerdquo is randomly selecting any address location (Am)of Message Cache and hence at any given time one of thecharacters stored in Message Cache get selected as ldquoYmrdquoand can be written as follows there is a ldquoLOOK-UP Tablerdquoconsisting of random numbers which eventually act as anaddresses to locate any random character at ldquoMessage CacherdquoObviously the number of locations in ldquoLOOK-UP Tablerdquo is 8times more than that of the number of locations in ldquoMessageCacherdquo ie 8lowastM At any given time one of the charactersstored in ldquoMessage Cacherdquo gets selected as ldquoRandomly SelectedCharacterrdquo given by

119884119898= [119860119898] = [[119871 119894]] = [[119862119899119905]] (4)

where Ym is Randomly Selected Character and Amis Ran-domly Selected Address for ldquoMessage Cacherdquo and eventuallycontent of sequential location of ldquoLOOK-UP Tablerdquo 0 to M-1excluding three ldquoLeast Significant Bitsrdquo of content of Li

The ldquoClock Generatorrdquo of CSRT selects sequential loca-tions of ldquoLOOK-UP Tablerdquo and is given as

119871119894= 119862119899119905 (5)

where Cnt is output of the COUNTER

The format of content of Li while selecting the characterand specific bit of the character is as shown in Figure 3 Asthere are 8 bits in each character the randomization is alsoapplicable to these bits

The proposed algorithm works on 8 bytes of cover at atime as follows

119862 = [1198617 1198616 1198615 119861

0] (6)

where B7to B0= 8 bytes of the cover given to CSRT at any

given time whose DCT can be written as

119863 = 119863119862119879 (119862) (7)

where D is A set of 8 DCT coefficients of 8 respective bytes ofthe cover given in (6) which can also be written as

119863 = 1198627 1198626 1198625 119862

0 (8)

where every DCT coefficient (C) consists of signed binaryrepresentationThe bit selected (shown in Figure 3) is embed-ded in C

3 Embedding of the bit in C

3is nothing but making

LSB of C3as that of bit to be embedded as

LSB of 1198623= Selected Bit of 119884

119898

= Selected Bit of [[119871 119894]](9)

VLSI Design 5

Ym

MUX

Random lsquoBITrsquoSelectionrsquo

LOOK-UP Tablelsquo8 Mrsquo

Locations

Selected BIT for Embedding

Message Cache

lsquoMrsquoBytes

Random lsquoCharacter Selectionrsquo

COUNTER

CLOCK

AddressFor

LOOK-UP

Figure 3 Randomization of characters and bits of ldquoMessage Cacherdquo

After modifying the LSB of C3inverse DCT (IDCT) of D is

taken to get Stego as follows

119878 = 119868119863119862119879 (119863) (10)

where is S is the Stego block of data consisting of 8 byteshaving an embedded bit of information in LSB of C3

4 Embedding Algorithm

(1) Accept CI into Message Cache(2) Accept LOOK-UP Table as an Embedding Key (K)(3) Accept 8-byte cover data (C)(4) Compute DCT of 8 bytes of cover data(5) Randomly select byte (Ym) fromMessage Cache(6) Select a bit using 3 LSBs of contents of selected byte

LOOK-UP Table(7) Embed the selected bit at DCT coefficient C3(8) Compute IDCT of 8 bytes of cover data to get Stego

data(9) Repeat Step-3 to Step-8 for all the bits of all the

charactersMessage Cache(10) Stop

Although there are multiple steps in the proposed algorithmit is possible to have parallel processing of Step-(3) to Step-8If we take Pre Em= Step-(3) and Step-(4) Emd = Step-(5) andStep-(6) and Post-Em = Step-(7) and Step-(8) it is possible toreduce the total time required for embedding all the bits ofMessage Cache as shown in Figure 4

5 Experimental Set Up

The logic necessary to implement the algorithm is down-loaded from the PC to Configurable FPGA board usingVirtex-5 XC5VLX50T FFG1136C Board Critical Informa-tion (CI) and Embedding Key (K) are transferred to the FPGARAMatMessage Cache and LOOK-UPTable respectivelyThecover data (C) is then transferred on byte by byte basis Afterthe embedding process it gets validated by transferring Stegodata (S) back to PCWhile extracting theCritical Information

(CI1015840) the Stego data (S) sent from the PC to FPGA board onbyte by byte basis and the extracted CIrsquo stored in FPGARAMatMessage Cache is validated by receiving it on PC

6 Result and Discussion

This section declares the analysis of different parameters likePSNR area and the time The different methodologies areexplained in the literature such as LSB MSB DWT IWTand proposed approach [CSRT] The PSNR values are shownthrough Figure 5 The proposed hardware approach gives7377 dB PSNR value which is approximately 10 more thanmentioned approaches

The analysis of the proposed hardware approach forthe area in terms of Slice Registers Slice Look-Up-Tables(LUTs) and slice LUT-FF pair used in various approaches isdemonstrated through Figures 6 7 and 8 respectively TheproposedCSRTmethod uses only 241 Slice Registers and 1202LUTs

To understand the performance speed of execution ofalgorithm of embedding of CI has been considered This timevaries from 8448 120583s to 135168120583s while embedding of CIfrom 128 bytes to 2 K bytes in 1K bytes to 16 K bytes of coverdata Figure 9 gives an idea of reduction of processing speedof the proposed CSRT method

Security of the system is very high as the cryptographicEncryption and Steganographic data hiding processes hasbeen developed in FPGA hardware Although hidden dataare reversible and can be recovered by the intended user itshould not be detectable by any hacker (most of the hackersare nonsuspicious) as shown in Figure 2 The sharing of acommon key is important for the intended extractor Thiskey may be predecided from look up table which eventuallyrandomly select the bits of the characters frommessage cachefor embedding A personwho knows the algorithm and look-up table must be the person who will be able to extract theCritical Information (CI) For example for 128 bytes of CIthere will be 1 K bytes of look-up table and the attacker has totry 21024 and check permutations and combinations of look-up table provided that the embedder knows the algorithm AsCI increases the size of the look-up table also increases andhence the permutations and combinations of look-up tableAlthough this dependability is the drawback of the system

6 VLSI Design

Pre_Em Emd Post_Em

Pre_Em Emd

Pre_Em

Post_Em

Emd Post_Em

T

Pre_Em Emd Post_Em

Figure 4 Parallel processing of steps of CSRT algorithm

436512

609 6318

7377

1 2 3 4 5

PSNR

DWT [10] LSB[8] DCT[CSRT]MSB[12] IWT[9]0

1020304050607080

PSN

R

Figure 5 PSNR with different hardware approaches

399

1206

2056

255

1105808

241

1 2 3 4 5 6 7

Slice Register Used

[23] [24] [25] [26] [28] [29] [CSRT]0

500

1000

1500

2000

2500

Slic

e Reg

ister

Use

d

Figure 6 Slice registers used with different approaches

1338 1692

3788

9276

47213557

1202

1 2 3 4 5 6 7

Number of Slice LUTs Used

[23] [24] [25] [26] [28] [29] [CSRT]0

100020003000400050006000700080009000

10000

Num

ber o

f Slic

e LU

Ts u

sed

Figure 7 Number of slice LUTs used with different approaches

VLSI Design 7

260

632

1792

161 236

748 660

1 2 3 4 5 6 7

Number of Fully used LUT-FF Pairs

[CSRT]0

200400600800

100012001400160018002000

Fully

use

d LU

T-FF

Pai

rs[23] [24] [25] [26] [28] [29]

Figure 8 Fully used slice LUT-FF pairs with different approaches

8448 1689633792

67584

135168

1 2 3 4 5128 256 512 1024 2048Critical Information (Message Bits)

0200400600800

1000120014001600

Proc

essi

ng T

ime (

s)

Figure 9 Critical Information (CI) processing time

the system is reconfigurable and therefore one can designthe look-up table of any size based on size of the CI

7 Conclusion

The Crypto-Stego-Real-Time (CSRT) System presented inthis paper is highly secured due to its implementation inhardware As the encryption of CI has been done in the hard-ware using cache memory the random addresses of cachememory are used for scribbling CI to be embedded in thecover bit by bit fashion One cannot extract CI unless hesheknows the algorithmand look-up table as a key of embeddingPipelining process while embedding enhances the speedof embedding and optimizes the memory utilization Thesystem PSNR (7377) Number of Slice LUTs used (1202)and execution time (135168 120583S for 2 K bits of CI) show anevidence of better performance in terms of throughput ofthe system The drawback of the system is its EmbeddingKey which varies with CI As CI increases the size of thekey also increases However the system is reconfigurableand therefore one can design the look-up table of any sizebased on the size of the CI The overall performance of thepresented CSRT system is better than current state-of-the-artmethods and therefore it is most suitable for any real-timeapplications

Data Availability

The data used to support the findings of this study are avail-able from the corresponding author upon request

Conflicts of Interest

The authors declare that they have no conflicts of interest

Acknowledgments

We are thankful to Dr D Y Patil Institute of TechnologyPimpri Pune for encouragement and support

References

[1] S Debnath M Kalita and S Majumder ldquoA Review on Hard-ware Implementation of Steganographyrdquo in Proceedings of theDevices for Integrated Circuit pp 149ndash152 Kalyani IndiaMarch2017

[2] M Faheem S Jamel A Hassan Z A N Shafinaz andMMatldquoA Survey on the cryptographic encryption algorithmsrdquo Inter-national Journal of Advanced Computer Science and Applica-tions vol 8 no 11 pp 333ndash344 2017

[3] httpswwwinfosecurity-magazinecommagazine-featurestales-crypt-hardware-software

[4] S P Maity and M K Kundu ldquoDistortion free image-in-imagecommunication with implementation in FPGArdquo Elsevier Inter-national Journal of Electronics and Communications vol 67 pp438ndash447 2012

[5] R Balakrishnan A Rengarajan and J B B Rayappan ldquoMulti-plexed stego path on reconfigurable hardware a novel randomapproachrdquo Elsevier Computers and Electrical Engineering vol55 pp 153ndash163 2016

[6] S N Mali P M Patil and R M Jalnekar ldquoRobust and securedimage-adaptive data hidingrdquo Digital Signal Processing vol 22no 2 pp 314ndash323 2012

4 VLSI Design

E ECover Data (C)

Critical Information (CI)

Unintentional Attacks(A) or

Intentional Trapping

By Hacker (H)

Extracted Critical

Information (CIrsquo)

Secret Key (K) Secret Key (K)

Stego Data(S)

Device at Device at

fEm fEx

Transmitting end (DT) Receiving end (DR)

Figure 1 Steganographic data hiding mechanism

Reducing the Chance of Suspect

Encryption Decryption

Non-SuspiciousHacker

Sharing of Common Key (K)

CI CIrsquoSteg

anog

raph

y

Steg

anog

raph

y

Embedding ( )

Extraction( )

C

S

fEm fEx

Figure 2 Proposed Crypto-Stego-Real-Time (CSRT) System

where M is number of characters in CI stored in ldquoMessageCacherdquo at lsquoA

0to AMminus1 address locations in a sequence

The process of encryption typically carried out usingldquoRandomly Selected Set of Addressesrdquo stored in a ldquoLOOK-UP Tablerdquo is randomly selecting any address location (Am)of Message Cache and hence at any given time one of thecharacters stored in Message Cache get selected as ldquoYmrdquoand can be written as follows there is a ldquoLOOK-UP Tablerdquoconsisting of random numbers which eventually act as anaddresses to locate any random character at ldquoMessage CacherdquoObviously the number of locations in ldquoLOOK-UP Tablerdquo is 8times more than that of the number of locations in ldquoMessageCacherdquo ie 8lowastM At any given time one of the charactersstored in ldquoMessage Cacherdquo gets selected as ldquoRandomly SelectedCharacterrdquo given by

119884119898= [119860119898] = [[119871 119894]] = [[119862119899119905]] (4)

where Ym is Randomly Selected Character and Amis Ran-domly Selected Address for ldquoMessage Cacherdquo and eventuallycontent of sequential location of ldquoLOOK-UP Tablerdquo 0 to M-1excluding three ldquoLeast Significant Bitsrdquo of content of Li

The ldquoClock Generatorrdquo of CSRT selects sequential loca-tions of ldquoLOOK-UP Tablerdquo and is given as

119871119894= 119862119899119905 (5)

where Cnt is output of the COUNTER

The format of content of Li while selecting the characterand specific bit of the character is as shown in Figure 3 Asthere are 8 bits in each character the randomization is alsoapplicable to these bits

The proposed algorithm works on 8 bytes of cover at atime as follows

119862 = [1198617 1198616 1198615 119861

0] (6)

where B7to B0= 8 bytes of the cover given to CSRT at any

given time whose DCT can be written as

119863 = 119863119862119879 (119862) (7)

where D is A set of 8 DCT coefficients of 8 respective bytes ofthe cover given in (6) which can also be written as

119863 = 1198627 1198626 1198625 119862

0 (8)

where every DCT coefficient (C) consists of signed binaryrepresentationThe bit selected (shown in Figure 3) is embed-ded in C

3 Embedding of the bit in C

3is nothing but making

LSB of C3as that of bit to be embedded as

LSB of 1198623= Selected Bit of 119884

119898

= Selected Bit of [[119871 119894]](9)

VLSI Design 5

Ym

MUX

Random lsquoBITrsquoSelectionrsquo

LOOK-UP Tablelsquo8 Mrsquo

Locations

Selected BIT for Embedding

Message Cache

lsquoMrsquoBytes

Random lsquoCharacter Selectionrsquo

COUNTER

CLOCK

AddressFor

LOOK-UP

Figure 3 Randomization of characters and bits of ldquoMessage Cacherdquo

After modifying the LSB of C3inverse DCT (IDCT) of D is

taken to get Stego as follows

119878 = 119868119863119862119879 (119863) (10)

where is S is the Stego block of data consisting of 8 byteshaving an embedded bit of information in LSB of C3

4 Embedding Algorithm

(1) Accept CI into Message Cache(2) Accept LOOK-UP Table as an Embedding Key (K)(3) Accept 8-byte cover data (C)(4) Compute DCT of 8 bytes of cover data(5) Randomly select byte (Ym) fromMessage Cache(6) Select a bit using 3 LSBs of contents of selected byte

LOOK-UP Table(7) Embed the selected bit at DCT coefficient C3(8) Compute IDCT of 8 bytes of cover data to get Stego

data(9) Repeat Step-3 to Step-8 for all the bits of all the

charactersMessage Cache(10) Stop

Although there are multiple steps in the proposed algorithmit is possible to have parallel processing of Step-(3) to Step-8If we take Pre Em= Step-(3) and Step-(4) Emd = Step-(5) andStep-(6) and Post-Em = Step-(7) and Step-(8) it is possible toreduce the total time required for embedding all the bits ofMessage Cache as shown in Figure 4

5 Experimental Set Up

The logic necessary to implement the algorithm is down-loaded from the PC to Configurable FPGA board usingVirtex-5 XC5VLX50T FFG1136C Board Critical Informa-tion (CI) and Embedding Key (K) are transferred to the FPGARAMatMessage Cache and LOOK-UPTable respectivelyThecover data (C) is then transferred on byte by byte basis Afterthe embedding process it gets validated by transferring Stegodata (S) back to PCWhile extracting theCritical Information

(CI1015840) the Stego data (S) sent from the PC to FPGA board onbyte by byte basis and the extracted CIrsquo stored in FPGARAMatMessage Cache is validated by receiving it on PC

6 Result and Discussion

This section declares the analysis of different parameters likePSNR area and the time The different methodologies areexplained in the literature such as LSB MSB DWT IWTand proposed approach [CSRT] The PSNR values are shownthrough Figure 5 The proposed hardware approach gives7377 dB PSNR value which is approximately 10 more thanmentioned approaches

The analysis of the proposed hardware approach forthe area in terms of Slice Registers Slice Look-Up-Tables(LUTs) and slice LUT-FF pair used in various approaches isdemonstrated through Figures 6 7 and 8 respectively TheproposedCSRTmethod uses only 241 Slice Registers and 1202LUTs

To understand the performance speed of execution ofalgorithm of embedding of CI has been considered This timevaries from 8448 120583s to 135168120583s while embedding of CIfrom 128 bytes to 2 K bytes in 1K bytes to 16 K bytes of coverdata Figure 9 gives an idea of reduction of processing speedof the proposed CSRT method

Security of the system is very high as the cryptographicEncryption and Steganographic data hiding processes hasbeen developed in FPGA hardware Although hidden dataare reversible and can be recovered by the intended user itshould not be detectable by any hacker (most of the hackersare nonsuspicious) as shown in Figure 2 The sharing of acommon key is important for the intended extractor Thiskey may be predecided from look up table which eventuallyrandomly select the bits of the characters frommessage cachefor embedding A personwho knows the algorithm and look-up table must be the person who will be able to extract theCritical Information (CI) For example for 128 bytes of CIthere will be 1 K bytes of look-up table and the attacker has totry 21024 and check permutations and combinations of look-up table provided that the embedder knows the algorithm AsCI increases the size of the look-up table also increases andhence the permutations and combinations of look-up tableAlthough this dependability is the drawback of the system

6 VLSI Design

Pre_Em Emd Post_Em

Pre_Em Emd

Pre_Em

Post_Em

Emd Post_Em

T

Pre_Em Emd Post_Em

Figure 4 Parallel processing of steps of CSRT algorithm

436512

609 6318

7377

1 2 3 4 5

PSNR

DWT [10] LSB[8] DCT[CSRT]MSB[12] IWT[9]0

1020304050607080

PSN

R

Figure 5 PSNR with different hardware approaches

399

1206

2056

255

1105808

241

1 2 3 4 5 6 7

Slice Register Used

[23] [24] [25] [26] [28] [29] [CSRT]0

500

1000

1500

2000

2500

Slic

e Reg

ister

Use

d

Figure 6 Slice registers used with different approaches

1338 1692

3788

9276

47213557

1202

1 2 3 4 5 6 7

Number of Slice LUTs Used

[23] [24] [25] [26] [28] [29] [CSRT]0

100020003000400050006000700080009000

10000

Num

ber o

f Slic

e LU

Ts u

sed

Figure 7 Number of slice LUTs used with different approaches

VLSI Design 7

260

632

1792

161 236

748 660

1 2 3 4 5 6 7

Number of Fully used LUT-FF Pairs

[CSRT]0

200400600800

100012001400160018002000

Fully

use

d LU

T-FF

Pai

rs[23] [24] [25] [26] [28] [29]

Figure 8 Fully used slice LUT-FF pairs with different approaches

8448 1689633792

67584

135168

1 2 3 4 5128 256 512 1024 2048Critical Information (Message Bits)

0200400600800

1000120014001600

Proc

essi

ng T

ime (

s)

Figure 9 Critical Information (CI) processing time

the system is reconfigurable and therefore one can designthe look-up table of any size based on size of the CI

7 Conclusion

The Crypto-Stego-Real-Time (CSRT) System presented inthis paper is highly secured due to its implementation inhardware As the encryption of CI has been done in the hard-ware using cache memory the random addresses of cachememory are used for scribbling CI to be embedded in thecover bit by bit fashion One cannot extract CI unless hesheknows the algorithmand look-up table as a key of embeddingPipelining process while embedding enhances the speedof embedding and optimizes the memory utilization Thesystem PSNR (7377) Number of Slice LUTs used (1202)and execution time (135168 120583S for 2 K bits of CI) show anevidence of better performance in terms of throughput ofthe system The drawback of the system is its EmbeddingKey which varies with CI As CI increases the size of thekey also increases However the system is reconfigurableand therefore one can design the look-up table of any sizebased on the size of the CI The overall performance of thepresented CSRT system is better than current state-of-the-artmethods and therefore it is most suitable for any real-timeapplications

Data Availability

The data used to support the findings of this study are avail-able from the corresponding author upon request

Conflicts of Interest

The authors declare that they have no conflicts of interest

Acknowledgments

We are thankful to Dr D Y Patil Institute of TechnologyPimpri Pune for encouragement and support

References

[1] S Debnath M Kalita and S Majumder ldquoA Review on Hard-ware Implementation of Steganographyrdquo in Proceedings of theDevices for Integrated Circuit pp 149ndash152 Kalyani IndiaMarch2017

[2] M Faheem S Jamel A Hassan Z A N Shafinaz andMMatldquoA Survey on the cryptographic encryption algorithmsrdquo Inter-national Journal of Advanced Computer Science and Applica-tions vol 8 no 11 pp 333ndash344 2017

[3] httpswwwinfosecurity-magazinecommagazine-featurestales-crypt-hardware-software

[4] S P Maity and M K Kundu ldquoDistortion free image-in-imagecommunication with implementation in FPGArdquo Elsevier Inter-national Journal of Electronics and Communications vol 67 pp438ndash447 2012

[5] R Balakrishnan A Rengarajan and J B B Rayappan ldquoMulti-plexed stego path on reconfigurable hardware a novel randomapproachrdquo Elsevier Computers and Electrical Engineering vol55 pp 153ndash163 2016

[6] S N Mali P M Patil and R M Jalnekar ldquoRobust and securedimage-adaptive data hidingrdquo Digital Signal Processing vol 22no 2 pp 314ndash323 2012

VLSI Design 5

Ym

MUX

Random lsquoBITrsquoSelectionrsquo

LOOK-UP Tablelsquo8 Mrsquo

Locations

Selected BIT for Embedding

Message Cache

lsquoMrsquoBytes

Random lsquoCharacter Selectionrsquo

COUNTER

CLOCK

AddressFor

LOOK-UP

Figure 3 Randomization of characters and bits of ldquoMessage Cacherdquo

After modifying the LSB of C3inverse DCT (IDCT) of D is

taken to get Stego as follows

119878 = 119868119863119862119879 (119863) (10)

where is S is the Stego block of data consisting of 8 byteshaving an embedded bit of information in LSB of C3

4 Embedding Algorithm

(1) Accept CI into Message Cache(2) Accept LOOK-UP Table as an Embedding Key (K)(3) Accept 8-byte cover data (C)(4) Compute DCT of 8 bytes of cover data(5) Randomly select byte (Ym) fromMessage Cache(6) Select a bit using 3 LSBs of contents of selected byte

LOOK-UP Table(7) Embed the selected bit at DCT coefficient C3(8) Compute IDCT of 8 bytes of cover data to get Stego

data(9) Repeat Step-3 to Step-8 for all the bits of all the

charactersMessage Cache(10) Stop

Although there are multiple steps in the proposed algorithmit is possible to have parallel processing of Step-(3) to Step-8If we take Pre Em= Step-(3) and Step-(4) Emd = Step-(5) andStep-(6) and Post-Em = Step-(7) and Step-(8) it is possible toreduce the total time required for embedding all the bits ofMessage Cache as shown in Figure 4

5 Experimental Set Up

The logic necessary to implement the algorithm is down-loaded from the PC to Configurable FPGA board usingVirtex-5 XC5VLX50T FFG1136C Board Critical Informa-tion (CI) and Embedding Key (K) are transferred to the FPGARAMatMessage Cache and LOOK-UPTable respectivelyThecover data (C) is then transferred on byte by byte basis Afterthe embedding process it gets validated by transferring Stegodata (S) back to PCWhile extracting theCritical Information

(CI1015840) the Stego data (S) sent from the PC to FPGA board onbyte by byte basis and the extracted CIrsquo stored in FPGARAMatMessage Cache is validated by receiving it on PC

6 Result and Discussion

This section declares the analysis of different parameters likePSNR area and the time The different methodologies areexplained in the literature such as LSB MSB DWT IWTand proposed approach [CSRT] The PSNR values are shownthrough Figure 5 The proposed hardware approach gives7377 dB PSNR value which is approximately 10 more thanmentioned approaches

The analysis of the proposed hardware approach forthe area in terms of Slice Registers Slice Look-Up-Tables(LUTs) and slice LUT-FF pair used in various approaches isdemonstrated through Figures 6 7 and 8 respectively TheproposedCSRTmethod uses only 241 Slice Registers and 1202LUTs

To understand the performance speed of execution ofalgorithm of embedding of CI has been considered This timevaries from 8448 120583s to 135168120583s while embedding of CIfrom 128 bytes to 2 K bytes in 1K bytes to 16 K bytes of coverdata Figure 9 gives an idea of reduction of processing speedof the proposed CSRT method

Security of the system is very high as the cryptographicEncryption and Steganographic data hiding processes hasbeen developed in FPGA hardware Although hidden dataare reversible and can be recovered by the intended user itshould not be detectable by any hacker (most of the hackersare nonsuspicious) as shown in Figure 2 The sharing of acommon key is important for the intended extractor Thiskey may be predecided from look up table which eventuallyrandomly select the bits of the characters frommessage cachefor embedding A personwho knows the algorithm and look-up table must be the person who will be able to extract theCritical Information (CI) For example for 128 bytes of CIthere will be 1 K bytes of look-up table and the attacker has totry 21024 and check permutations and combinations of look-up table provided that the embedder knows the algorithm AsCI increases the size of the look-up table also increases andhence the permutations and combinations of look-up tableAlthough this dependability is the drawback of the system

6 VLSI Design

Pre_Em Emd Post_Em

Pre_Em Emd

Pre_Em

Post_Em

Emd Post_Em

T

Pre_Em Emd Post_Em

Figure 4 Parallel processing of steps of CSRT algorithm

436512

609 6318

7377

1 2 3 4 5

PSNR

DWT [10] LSB[8] DCT[CSRT]MSB[12] IWT[9]0

1020304050607080

PSN

R

Figure 5 PSNR with different hardware approaches

399

1206

2056

255

1105808

241

1 2 3 4 5 6 7

Slice Register Used

[23] [24] [25] [26] [28] [29] [CSRT]0

500

1000

1500

2000

2500

Slic

e Reg

ister

Use

d

Figure 6 Slice registers used with different approaches

1338 1692

3788

9276

47213557

1202

1 2 3 4 5 6 7

Number of Slice LUTs Used

[23] [24] [25] [26] [28] [29] [CSRT]0

100020003000400050006000700080009000

10000

Num

ber o

f Slic

e LU

Ts u

sed

Figure 7 Number of slice LUTs used with different approaches

VLSI Design 7

260

632

1792

161 236

748 660

1 2 3 4 5 6 7

Number of Fully used LUT-FF Pairs

[CSRT]0

200400600800

100012001400160018002000

Fully

use

d LU

T-FF

Pai

rs[23] [24] [25] [26] [28] [29]

Figure 8 Fully used slice LUT-FF pairs with different approaches

8448 1689633792

67584

135168

1 2 3 4 5128 256 512 1024 2048Critical Information (Message Bits)

0200400600800

1000120014001600

Proc

essi

ng T

ime (

s)

Figure 9 Critical Information (CI) processing time

the system is reconfigurable and therefore one can designthe look-up table of any size based on size of the CI

7 Conclusion

The Crypto-Stego-Real-Time (CSRT) System presented inthis paper is highly secured due to its implementation inhardware As the encryption of CI has been done in the hard-ware using cache memory the random addresses of cachememory are used for scribbling CI to be embedded in thecover bit by bit fashion One cannot extract CI unless hesheknows the algorithmand look-up table as a key of embeddingPipelining process while embedding enhances the speedof embedding and optimizes the memory utilization Thesystem PSNR (7377) Number of Slice LUTs used (1202)and execution time (135168 120583S for 2 K bits of CI) show anevidence of better performance in terms of throughput ofthe system The drawback of the system is its EmbeddingKey which varies with CI As CI increases the size of thekey also increases However the system is reconfigurableand therefore one can design the look-up table of any sizebased on the size of the CI The overall performance of thepresented CSRT system is better than current state-of-the-artmethods and therefore it is most suitable for any real-timeapplications

Data Availability

The data used to support the findings of this study are avail-able from the corresponding author upon request

Conflicts of Interest

The authors declare that they have no conflicts of interest

Acknowledgments

We are thankful to Dr D Y Patil Institute of TechnologyPimpri Pune for encouragement and support

References

[1] S Debnath M Kalita and S Majumder ldquoA Review on Hard-ware Implementation of Steganographyrdquo in Proceedings of theDevices for Integrated Circuit pp 149ndash152 Kalyani IndiaMarch2017

[2] M Faheem S Jamel A Hassan Z A N Shafinaz andMMatldquoA Survey on the cryptographic encryption algorithmsrdquo Inter-national Journal of Advanced Computer Science and Applica-tions vol 8 no 11 pp 333ndash344 2017

[3] httpswwwinfosecurity-magazinecommagazine-featurestales-crypt-hardware-software

[4] S P Maity and M K Kundu ldquoDistortion free image-in-imagecommunication with implementation in FPGArdquo Elsevier Inter-national Journal of Electronics and Communications vol 67 pp438ndash447 2012

[5] R Balakrishnan A Rengarajan and J B B Rayappan ldquoMulti-plexed stego path on reconfigurable hardware a novel randomapproachrdquo Elsevier Computers and Electrical Engineering vol55 pp 153ndash163 2016

[6] S N Mali P M Patil and R M Jalnekar ldquoRobust and securedimage-adaptive data hidingrdquo Digital Signal Processing vol 22no 2 pp 314ndash323 2012

6 VLSI Design

Pre_Em Emd Post_Em

Pre_Em Emd

Pre_Em

Post_Em

Emd Post_Em

T

Pre_Em Emd Post_Em

Figure 4 Parallel processing of steps of CSRT algorithm

436512

609 6318

7377

1 2 3 4 5

PSNR

DWT [10] LSB[8] DCT[CSRT]MSB[12] IWT[9]0

1020304050607080

PSN

R

Figure 5 PSNR with different hardware approaches

399

1206

2056

255

1105808

241

1 2 3 4 5 6 7

Slice Register Used

[23] [24] [25] [26] [28] [29] [CSRT]0

500

1000

1500

2000

2500

Slic

e Reg

ister

Use

d

Figure 6 Slice registers used with different approaches

1338 1692

3788

9276

47213557

1202

1 2 3 4 5 6 7

Number of Slice LUTs Used

[23] [24] [25] [26] [28] [29] [CSRT]0

100020003000400050006000700080009000

10000

Num

ber o

f Slic

e LU

Ts u

sed

Figure 7 Number of slice LUTs used with different approaches

VLSI Design 7

260

632

1792

161 236

748 660

1 2 3 4 5 6 7

Number of Fully used LUT-FF Pairs

[CSRT]0

200400600800

100012001400160018002000

Fully

use

d LU

T-FF

Pai

rs[23] [24] [25] [26] [28] [29]

Figure 8 Fully used slice LUT-FF pairs with different approaches

8448 1689633792

67584

135168

1 2 3 4 5128 256 512 1024 2048Critical Information (Message Bits)

0200400600800

1000120014001600

Proc

essi

ng T

ime (

s)

Figure 9 Critical Information (CI) processing time

the system is reconfigurable and therefore one can designthe look-up table of any size based on size of the CI

7 Conclusion

The Crypto-Stego-Real-Time (CSRT) System presented inthis paper is highly secured due to its implementation inhardware As the encryption of CI has been done in the hard-ware using cache memory the random addresses of cachememory are used for scribbling CI to be embedded in thecover bit by bit fashion One cannot extract CI unless hesheknows the algorithmand look-up table as a key of embeddingPipelining process while embedding enhances the speedof embedding and optimizes the memory utilization Thesystem PSNR (7377) Number of Slice LUTs used (1202)and execution time (135168 120583S for 2 K bits of CI) show anevidence of better performance in terms of throughput ofthe system The drawback of the system is its EmbeddingKey which varies with CI As CI increases the size of thekey also increases However the system is reconfigurableand therefore one can design the look-up table of any sizebased on the size of the CI The overall performance of thepresented CSRT system is better than current state-of-the-artmethods and therefore it is most suitable for any real-timeapplications

Data Availability

The data used to support the findings of this study are avail-able from the corresponding author upon request

Conflicts of Interest

The authors declare that they have no conflicts of interest

Acknowledgments

We are thankful to Dr D Y Patil Institute of TechnologyPimpri Pune for encouragement and support

References

[1] S Debnath M Kalita and S Majumder ldquoA Review on Hard-ware Implementation of Steganographyrdquo in Proceedings of theDevices for Integrated Circuit pp 149ndash152 Kalyani IndiaMarch2017

[2] M Faheem S Jamel A Hassan Z A N Shafinaz andMMatldquoA Survey on the cryptographic encryption algorithmsrdquo Inter-national Journal of Advanced Computer Science and Applica-tions vol 8 no 11 pp 333ndash344 2017

[3] httpswwwinfosecurity-magazinecommagazine-featurestales-crypt-hardware-software

[4] S P Maity and M K Kundu ldquoDistortion free image-in-imagecommunication with implementation in FPGArdquo Elsevier Inter-national Journal of Electronics and Communications vol 67 pp438ndash447 2012

[5] R Balakrishnan A Rengarajan and J B B Rayappan ldquoMulti-plexed stego path on reconfigurable hardware a novel randomapproachrdquo Elsevier Computers and Electrical Engineering vol55 pp 153ndash163 2016

[6] S N Mali P M Patil and R M Jalnekar ldquoRobust and securedimage-adaptive data hidingrdquo Digital Signal Processing vol 22no 2 pp 314ndash323 2012

VLSI Design 7

260

632

1792

161 236

748 660

1 2 3 4 5 6 7

Number of Fully used LUT-FF Pairs

[CSRT]0

200400600800

100012001400160018002000

Fully

use

d LU

T-FF

Pai

rs[23] [24] [25] [26] [28] [29]

Figure 8 Fully used slice LUT-FF pairs with different approaches

8448 1689633792

67584

135168

1 2 3 4 5128 256 512 1024 2048Critical Information (Message Bits)

0200400600800

1000120014001600

Proc

essi

ng T

ime (

s)

Figure 9 Critical Information (CI) processing time

the system is reconfigurable and therefore one can designthe look-up table of any size based on size of the CI

7 Conclusion

The Crypto-Stego-Real-Time (CSRT) System presented inthis paper is highly secured due to its implementation inhardware As the encryption of CI has been done in the hard-ware using cache memory the random addresses of cachememory are used for scribbling CI to be embedded in thecover bit by bit fashion One cannot extract CI unless hesheknows the algorithmand look-up table as a key of embeddingPipelining process while embedding enhances the speedof embedding and optimizes the memory utilization Thesystem PSNR (7377) Number of Slice LUTs used (1202)and execution time (135168 120583S for 2 K bits of CI) show anevidence of better performance in terms of throughput ofthe system The drawback of the system is its EmbeddingKey which varies with CI As CI increases the size of thekey also increases However the system is reconfigurableand therefore one can design the look-up table of any sizebased on the size of the CI The overall performance of thepresented CSRT system is better than current state-of-the-artmethods and therefore it is most suitable for any real-timeapplications

Data Availability

The data used to support the findings of this study are avail-able from the corresponding author upon request

Conflicts of Interest

The authors declare that they have no conflicts of interest

Acknowledgments

We are thankful to Dr D Y Patil Institute of TechnologyPimpri Pune for encouragement and support

References

[1] S Debnath M Kalita and S Majumder ldquoA Review on Hard-ware Implementation of Steganographyrdquo in Proceedings of theDevices for Integrated Circuit pp 149ndash152 Kalyani IndiaMarch2017

[2] M Faheem S Jamel A Hassan Z A N Shafinaz andMMatldquoA Survey on the cryptographic encryption algorithmsrdquo Inter-national Journal of Advanced Computer Science and Applica-tions vol 8 no 11 pp 333ndash344 2017

[3] httpswwwinfosecurity-magazinecommagazine-featurestales-crypt-hardware-software

[4] S P Maity and M K Kundu ldquoDistortion free image-in-imagecommunication with implementation in FPGArdquo Elsevier Inter-national Journal of Electronics and Communications vol 67 pp438ndash447 2012

[5] R Balakrishnan A Rengarajan and J B B Rayappan ldquoMulti-plexed stego path on reconfigurable hardware a novel randomapproachrdquo Elsevier Computers and Electrical Engineering vol55 pp 153ndash163 2016

[6] S N Mali P M Patil and R M Jalnekar ldquoRobust and securedimage-adaptive data hidingrdquo Digital Signal Processing vol 22no 2 pp 314ndash323 2012

8 VLSI Design

[7] E Gomez-Hernandez C Feregrino-Uribe and R CumplidoldquoFPGA hardware architecture of the steganographic contexttechniquerdquo in Proceedings of the IEEE Computer Society Inter-national Conference on Electronics Communications and Com-puters pp 123ndash128 Mexico March 2008

[8] B J Mohd T Hayajneh S Abed and A Itradat ldquoAnalysis andmodeling of FPGA implementations of spatial steganographymethodsrdquo Journal of Circuits Systems and Computers vol 23no 2 pp 1ndash25 2014

[9] B Ramalingam R Amirtharajan and J B B Rayappan ldquoStegoon FPGA An IWTApproachrdquoHindawi Publishing CorporationScientific World Journal pp 1ndash9 2014

[10] B J Mohd T Hayajneh and A N Quttoum ldquoWavelet-trans-form steganography Algorithm and hardware implementa-tionrdquo International Journal of Electronic Security and DigitalForensics vol 5 no 3-4 pp 241ndash256 2013

[11] S Mahmoudpour and S Mirzakuchaki ldquoHardware Architec-ture for aMessage Hiding Algorithm with Novel RandomizersrdquoInternational Journal of Computer Applications vol 37 no 7 pp46ndash53 2012

[12] S Rajagopala P J Prabhakar M S Kumar et al ldquoMSB BasedEmbedding with Integrity An Adaptive RGB Stego on FPGAPlatformrdquo Information Technology Journal vol 13 no 12 pp1945ndash1952 2014

[13] A Mahmood N Kanai and S Mohmmad ldquoAn FPGA imple-mentation of secured steganography communication systemrdquoTikrit Journal of Engineering Sciences vol 19 no 4 pp 14ndash232012

[14] R Sundararaman and H Narayan Upadhyay ldquoStego system onchipwith lfsr based information hiding approachrdquo InternationalJournal of Computer Applications vol 18 no 2 pp 24ndash31 2011

[15] A Shabir A Parah Javaid and G M Bhat ldquoData hiding inintermediate significant bit planes a high capacity blind ste-ganographic techniquerdquo in Proceedings of the IEEE InternationalConference on Emerging Trends in Science Engineering andTechnology pp 192ndash197 2012

[16] S A El Rahman ldquoA comparative analysis of image steganog-raphy based on DCT algorithm and steganography tool to hidenuclear reactors confidential informationrdquoComputers and Elec-trical Engineering pp 1ndash20 2016

[17] R J Anderson and F A P Petitcolas ldquoOn the limits of steganog-raphyrdquo IEEE Journal on Selected Areas in Communications vol16 no 4 pp 474ndash481 1998

[18] A Odeh K Elleithy and M Faezipour ldquoFast real-time hard-ware engine for multipoint text steganographyrdquo in Proceedingsof the 2014 IEEE Long Island Systems Applications and Technol-ogy Conference LISAT 2014 pp 1ndash5 May 2014

[19] J Fridrich Steganography in Digital Media Principles Algo-rithms and Applications Cambridge University Press NewYork NY USA 2009

[20] HA Farouk andM Saeb ldquoDesign and implementation of a sec-ret key steganographicmicro-architecture employing FPGArdquo inProceedings of the ASP - DAC 2004Asia and South PacificDesignAutomation Conference - 2004 pp 577-578 Japan January2004

[21] F Cariccia P Cariccia M Martina A Molino and F VaccaldquoMultimedia SoC A systolic core for embedded DCT evalu-ationrdquo in Proceedings of the IEEE Conference Paper pp 1749ndash1753 USA November 2002

[22] G Renda M Masera M Martina and G Masera ldquoApproxi-mate Arai DCT architecture for HEVCrdquo in Proceedings of the1st New Generation of CAS NGCAS 2017 pp 133ndash136 ItalySeptember 2017

[23] M H Rais and S M Qasim ldquoVirtex-5 Fpga implementation ofadvanced encryptionstandard algorithmrdquo in Proceedings of the3rd Global Conference on Power Control and Optimization pp201ndash206 May 2010

[24] P Ghosal M Biswas and M Biswas ldquoHardware Implementa-tion of TDES CryptoSystemwith on chip verification in FPGArdquoJournal of Telecommunications vol 1 no 1 pp 113ndash117 2010

[25] K Rahimunnisa P Karthigaikumar S Rasheed J Jayakumarand S Sureshkumar ldquoFPGA implementation of AES algorithmfor high throughput using folded parallel architecturerdquo Securityand Communication Networks vol 7 no 11 pp 2225ndash22362014

[26] U Farooq and M F Aslam ldquoComparative analysis of differentAES implementation techniques for efficient resource usage andbetter performance of an FPGArdquo Journal of King Saud Uni-versity - Computer and Information Sciences vol 29 no 3 pp295ndash302 2017

[27] A Gielata P Russek and K Wiatr ldquoAES Hardware Implemen-tation in FPGA for Algorithm Acceleration Purposerdquo in Pro-ceedings of the ICSES 2008 International Conference on Signalsand Electronic Systems ICSESrsquo08 pp 137ndash140 Poland Septem-ber 2008

[28] S Sadoudi C Tanougast M S Azzaz and A DandacheldquoDesign and FPGA Implementation of a wireless hyperchaoticcommunication system for secure real-time image transmis-sionrdquo Journal on Image and Video Processing Springer pp 1ndash182013

[29] R R Farashahi B Rashidi and S M Sayedi ldquoFPGA based fastand high-throughput 2-slow retiming 128-bit AES encryptionalgorithmrdquoMicroelectronics Journal vol 45 pp 1014ndash1025 2014

[30] P P Karthigai and A K Baskaran ldquoFPGA implementation ofhigh speed low area DWT based invisible image watermarkingalgorithmrdquo in Proceedings of the International Conference onCommunication Technology and System Design Elsevier vol 30pp 266ndash273 October 2012

[31] T-T Quach ldquoOptimal cover estimation methods and stegano-graphic payload locationrdquo IEEE Transactions on InformationForensics and Security vol 6 no 4 pp 1214ndash1222 2011

[32] H-L Yeh S-T Gue P Tsai andW-K Shih ldquoWavelet bit-planebased data hiding for compressed imagesrdquo AEU - InternationalJournal of Electronics and Communications vol 67 no 9 pp808ndash815 2013

[33] AValizadeh andZ JWang ldquoCorrelation-and-bit-aware spreadspectrum embedding for data hidingrdquo IEEE Transactions onInformation Forensics and Security vol 6 no 2 pp 267ndash2822011

[34] QMao ldquoA fast algorithm formatrix embedding steganographyrdquoDigital Signal Processing vol 25 no 1 pp 248ndash254 2014

[35] O M Al-Qershi and B E Khoo ldquoHigh capacity data hidingschemes formedical images based on difference expansionrdquoTheJournal of Systems and Software vol 84 no 1 pp 105ndash112 2011

[36] A Khamrui and J K Mandal ldquoA Genetic Algorithm-BasedSteganography using Discrete Cosine Transformation (GAS-DCT)rdquo in Proceedings of the International Conference on Com-putational Intelligence Modeling Techniques and Applicationsvol 10 pp 105ndash111 2013

[37] N A Saleh H N Boghdady S I Shaheen and A M DarwishldquoHigh capacity lossless data embedding technique for paletteimages based on histogram analysisrdquo Digital Signal Processingvol 20 no 6 pp 1629ndash1636 2010

International Journal of

AerospaceEngineeringHindawiwwwhindawicom Volume 2018

RoboticsJournal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Active and Passive Electronic Components

VLSI Design

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Shock and Vibration

Hindawiwwwhindawicom Volume 2018

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawiwwwhindawicom

Volume 2018

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

Control Scienceand Engineering

Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom

Journal ofEngineeringVolume 2018

SensorsJournal of

Hindawiwwwhindawicom Volume 2018

International Journal of

RotatingMachinery

Hindawiwwwhindawicom Volume 2018

Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Navigation and Observation

International Journal of

Hindawi

wwwhindawicom Volume 2018

Advances in

Multimedia

Submit your manuscripts atwwwhindawicom

International Journal of

AerospaceEngineeringHindawiwwwhindawicom Volume 2018

RoboticsJournal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Active and Passive Electronic Components

VLSI Design

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Shock and Vibration

Hindawiwwwhindawicom Volume 2018

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawiwwwhindawicom

Volume 2018

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

Control Scienceand Engineering

Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom

Journal ofEngineeringVolume 2018

SensorsJournal of

Hindawiwwwhindawicom Volume 2018

International Journal of

RotatingMachinery

Hindawiwwwhindawicom Volume 2018

Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Navigation and Observation

International Journal of

Hindawi

wwwhindawicom Volume 2018

Advances in

Multimedia

Submit your manuscripts atwwwhindawicom