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CROP MONITORING SYSTEM
A
Mini Project Report
Submitted in the Partial Fulfillment of the
Requirements
For the Award of the Degree of
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
Submitted
By
J.PAVAN KUMAR 10881A0427
J.HAREEN SAI 10881A0413
P.DINESH KUMAR 10881A0409
Under the Guidance of
MR. J. KRISHNA CHAITHANYA
Associate Professor
Department of ECE
Department of Electronics and Communication Engineering
(AUTONOMOUS)
(Approved by AICTE, Affiliated to JNTUH & Accredited by NBA)
2013 - 14
(AUTONOMOUS) Estd.1999 Shamshabad, Hyderabad - 501218
Kacharam (V), Shamshabad (M), Ranga Reddy (Dist.) 501 218, Hyderabad, A.P. Ph: 08413-253335, 253201, Fax: 08413-253482, www.vardhaman.org
Department of Electronics and Communication Engineering
CERTIFICATE
This is to certify that the technical seminar report work entitled Crop Monitoring
System carried out by Mr. J.Pavan Kumar, Roll Number 10881A0427; Hareen Sai Javaji, Roll
Number 10881A0413; Dinesh Kumar Pentam , Roll number 10881A0409 submitted to the
department of Electronics and Communication Engineering, in partial fulfillment of the
requirements for the award of degree of Bachelor of Technology in Electronics and
Communication Engineering during the year 2013 2014.
Name & Signature of the Supervisor
Mr. J.KRISHNA CHAITHANYA
Associate Professor
Name & Signature of the HOD
Dr. J. V. R. Ravindra
Head, ECE
iii
ACKNOWLEDGEMENTS
The satisfaction that accompanies the successful completion of the task would be put
incomplete without the mention of the people who made it possible, whose constant guidance
and encouragement crown all the efforts with success.
We express my heartfelt thanks to Mr. J. Krishna Chaithanya, Associate Professor, technical seminar supervisor, for his suggestions in selecting and carrying out the in-depth study
of the topic. His valuable guidance, encouragement and critical reviews really helped to shape
this report to perfection. We wish to express my deep sense of gratitude to Dr. J. V. R. Ravindra, Head of the
Department for his able guidance and useful suggestions, which helped me in completing the
technical seminar on time.
We also owe my special thanks to our Director Prof. L. V. N. Prasad for his intense
support, encouragement and for having provided all the facilities and support.
We am highly indebted to Prof. Y. Pandurangaiah, Ms. A. Vijaya Lakshmi, Mr. H. Shravan Kumar and Mr. S. Rajendar for their guidance and constant supervision as well as
moral strength and courage during the tough times of our academic career.
Finally thanks to all our family members and friends for their continuous support and
enthusiastic help.
Yours Sincerely,
J. Pavan Kumar
HareenSai Javaji
Pentam Dinesh
iv
ABSTRACT
Appropriate soil water level is a necessary pre-requisite for optimum plant growth. Also, water
being an essential element for life sustenance, there is the necessity to avoid its undue usage.
Irrigation is a dominant consumer of water. This calls for the need to regulate water supply for
irrigation purposes. Fields should neither be over-irrigated nor under-irrigated. Over time,
systems have been implemented towards realizing this objective of which automated processes
are the most popular as they allow information to be collected at high frequency with less labor
requirements. Bulk of the existing systems employ micro-processor based systems. These
systems offer several technological advantages but are unaffordable, bulky, difficult to maintain
and less accepted by the technologically unskilled workers in the rural scenario.
The objective of this project is to design a simple, easy to install methodology to monitor and
indicate the level of soil moisture that is continuously controlled in order to achieve maximum
plant growth and simultaneously optimize the available irrigation resources. A simple AVR
Atmega 64 based comparator circuit is used coupled with relay units which control the water
pumps. The use of easily available components reduces the manufacturing and maintenance
costs. This makes the proposed system to be an economical, appropriate and a low maintenance
solution for applications, especially in rural areas and for small scale agriculturists.
This Project allows farmers to monitor their farm staying away from field and precisely know
whether the soil is dry or wet with, humidity and temperature at the field , apart from this , the
circuit application allows to switch the Pump Set Motor ON and OFF right from home sitting
away from the crop field. Using Atmega 64 and necessary interface integrating circuits like
RS232, LM 2685 the hardware components and sensor components are interfaced. Later using
switches the complete crop status such as Temperature and Humidity at crop Field, whether the
soil is wet or dry and necessary actions can be taken as stated before.
v
CONTENTS
Acknowledgements (iii)
Abstract (iv)
List of Figures (vii)
List of Tables (viii)
1 INTRODUCTION 1
1.1 Device Overview 2
1.2 Device Architecture
1.3 Development And Features
3
7
1.4 Programing Interfacing 10
1.5 Debugging Interfaces 12
2 AVR ATmega64A PERIPHERALS 14
2.1 Interrupts 15
2.2 I/O Ports 18
2.3 USART 23
3 DEVELOPMENT BOARD AND PERIPHERALS 27
3.1 UniBoard Development Board 27
3.2 Needs for programming the Board 28
3.3 Hardware Connections 29
3.4 Fea tur es 31
3.5 Setting up Board Configuration 33
3.6 Genera l Purpose PORTS 37
4 SESORS 39
4.1 Temperature Sensor 39
4.2 CMOS Humidity Sensors 43
vi
4.3 Soil Moisture Sensor 49
5 Relay And Motor Driver 55
5.1 Relay 55
5.2 Motor Driver 65
6 Conclusions 66
REFERENCES 67
APPENDIX 68-79
vii
LIST OF FIGURES
1.2 Atmega 64 4
1.3 Uniboard development board 10
1.4.6 Uniboard development board 10
2.1 Program memory 15
2.2 I/O Pin Equivalent Schematic 19
3.3 UniBoard Atmege 64 Development Board 30
3.6 Pin out Diagram Of Atmega64 38
4.1 LM35- Temperature Sensor 39
4.1.1 LM35 Sensor Pin outs and Packaging 40
4.2.3 Humidity sensor 46
4.3.1 Soil moisture sensor LM324 49
4.3.2 Pin Out LM324 50
4.3.3 Pin Diagram of LM324 50
5.1 Working Of Relay 55
5.1.1 Electromagnetic Relay 56
5.1.2 Electromagnetic Relay Operation 56
5.1.3 Latching Relay 58
5.1.4 Reed Relay 59
5.1.5 Solid State Relay 60
5.1.6 A DPDT AC coil relay with "ice cube" packaging 62
5.1.7 Relay Driver 64 5.2 Motor Driver Pin Out 65
viii
LIST OF TABLES
2.1.1 Port A Pins Alternate Functions 20
2.2.2 Overriding Signals for Alternate Functions in PA7.PA4 20
2.2.3 Overriding Signals for Alternate Functions in PA3.PA0 21
2.2.4 Port C Pins Alternate Functions 21
2.2.5 Overriding Signals for Alternate Functions in PC7.PC4 22
2.2.6 Overriding Signals for Alternate Functions in PC3.PC0 23
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CHAPTER 1
INTRODUCTION
The original AVR MCU was developed at a local ASIC house in Trondheim,
Norway called Nordic VLSI at the time, now Nordic Semiconductor, where Bogen and Wollan
were working as students. It was known as a RISC (Micro RISC) and was available as silicon
IP/building block from Nordic VLSI. When the technology was sold to Atmel from Nordic VLSI,
the internal architecture was further developed by Bogen and Wollan at Atmel Norway, a
subsidiary of Atmel. The designers worked closely with compiler writers at IAR Systems to
ensure that the instruction set provided for more efficient compilation of high-level languages.
Atmel says that the name AVR is not an acronym and does not stand for anything in particular.
The creators of the AVR give no definitive answer as to what the term "AVR" stands for.
However, it is commonly accepted that AVR stands for Alf (Egil Bogen) andVegard
(Wollan)'s RISC processor.
Note that the use of "AVR" in this article generally refers to the 8-bit RISC line of Atmel
AVR Microcontrollers. Among the first of the AVR line was the AT90S8515, which in a 40-pin
DIP package has the same pinout as an 8051 microcontroller, including the external multiplexed
address and data bus. The polarity of the RESET line was opposite (8051's having an active-high
RESET, while the AVR has an active-low RESET), but other than that the pinout was identical.
Based on industry-leading, proven technology, the megaAVR family offers our widest
selection of devices in terms of memories, pin-counts and peripherals. Choose from general-
purpose devices to models with specialized peripherals like USB, or LCD controllers, or CAN,
LIN and Power Stage Controllers. It's easy to find the perfect fit for your project in the megaAVR
product family. Being supported by the Atmel Studio development platform further reduces your
time-to-market.
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1.1 Device overview
The AVR is a modified Harvard architecture machine where program and data are
stored in separate physical memory systems that appear in different address spaces, but having
the ability to read data items from program memory using special instructions.
Basic families
AVRs are generally classified into six broad groups:
tinyAVR the ATtiny series
0.516 kB program memory
632-pin package
Limited peripheral set
megaAVR the ATmega series
4512 kB program memory
28100-pin package
Extended instruction set (multiply instructions and instructions for handling larger program
memories)
Extensive peripheral set
XMEGA the ATxmega series
16384 kB program memory
4464100-pin package (A4, A3, A1)
Extended performance features, such as DMA, "Event System", and cryptography support.
Extensive peripheral set with ADCs
Application-specific AVR
megaAVRs with special features not found on the other members of the AVR family, such as
LCD controller, USB controller, advanced PWM, CAN, etc.
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FPSLIC (AVR with FPGA)
FPGA 5K to 40K gates
SRAM for the AVR program code, unlike all other AVRs
AVR core can run at up to 50 MHz
32-bit AVRs
In 2006 Atmel released microcontrollers based on the 32-bit AVR32 architecture. They
include SIMD and DSP instructions, along with other audio and video processing features. This
32-bit family of devices is intended to compete with the ARM based processors. The instruction
set is similar to other RISC cores, but it is not compatible with the original AVR or any of the
various ARM cores.
1.2 Device architecture
Flash, EEPROM, and SRAM are all integrated onto a single chip, removing the
need for external memory in most applications. Some devices have a parallel external bus
option to allow adding additional data memory or memory-mapped devices. Almost all devices
(except the smallest TinyAVR chips) have serial interfaces, which can be used to connect larger
serial EEPROMs or flash chips.
Program memory
Program instructions are stored in non-volatile flash memory. Although the MCUs
are 8-bit, each instruction takes one or two 16-bit words.
The size of the program memory is usually indicated in the naming of the device itself (e.g., the
ATmega64x line has 64 kB of flash while the ATmega32x line has 32 kB).
There is no provision for off-chip program memory; all code executed by the AVR core must
reside in the on-chip flash. However, this limitation does not apply to the AT94 FPSLIC
AVR/FPGA chips.
Internal data memory
The data address space consists of the register file, I/O registers, and SRAM.
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Fig 1.2 Atmega 64A
Internal registers
The AVRs have 32 single-byte registers and are classified as 8-bit RISC devices.
In most variants of the AVR architecture, the working registers are mapped in as the first 32
memory addresses (000016001F16) followed by the 64 I/O registers (002016005F16).
Actual SRAM starts after these register sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case the memory mapped
I/O registers will occupy a portion of the SRAM address space.)
Even though there are separate addressing schemes and optimized opcodes for register
file and I/O register access, all can still be addressed and manipulated as if they were in
SRAM.In the XMEGA variant, the working register file is not mapped into the data address
space; as such, it is not possible to treat any of the XMEGA's working registers as though they
were SRAM. Instead, the I/O registers are mapped into the data address space starting at the very
beginning of the address space. Additionally, the amount of data address space dedicated to I/O
registers has grown substantially to 4096 bytes (0000160FFF16). As with previous generations,
however, the fast I/O manipulation instructions can only reach the first 64 I/O register locations
(the first 32 locations for bitwise instructions). Following the I/O registers, the XMEGA series
sets aside a 4096 byte range of the data address space which can be used optionally for mapping
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the internal EEPROM to the data address space (1000161FFF16). The actual SRAM is located
after these ranges, starting at 200016.
I/O Registers in AVR
Each port consists of three registes: DDRx, PORTx and PINx.
DDRx : Data direction register.
PORTx : Output port register. Used only for output.
PINx : Input register. Used only for input.
Pin toggling with PINx: "writing a logic one to PINx n bit toggles the value of
PORTx n bit, independent on the value of DDRx n". This may not be true for all AVR
devices, check the datasheet of the device.
EEPROM
Almost all AVR microcontrollers have internal EEPROM for semi-permanent data storage.
Like flash memory, EEPROM can maintain its contents when electrical power is removed.
In most variants of the AVR architecture, this internal EEPROM memory is not mapped into
the MCU's addressable memory space. It can only be accessed the same way an external
peripheral device is, using special pointer registers and read/write instructions which makes
EEPROM access much slower than other internal RAM.
However, some devices in the SecureAVR (AT90SC) family [7] use a special EEPROM
mapping to the data or program memory depending on the configuration. The XMEGA
family also allows the EEPROM to be mapped into the data address space.
Since the number of writes to EEPROM is not unlimited Atmel specifies 100,000 write
cycles in their datasheets a well designed EEPROM write routine should compare the
contents of an EEPROM address with desired contents and only perform an actual write if
the contents need to be changed.
Note that erase and write can be performed separately in many cases, byte-by-byte, which
may also help prolong life when bits only need to be set to all 1s (erase) or selectively
cleared to 0s (write).
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Program execution
Atmel's AVRs have a two stage, single level pipeline design. This means the next machine
instruction is fetched as the current one is executing. Most instructions take just one or two
clock cycles, making AVRs relatively fast among eight-bit microcontrollers.
The AVR processors were designed with the efficient execution of compiled C code in mind
and have several built-in pointers for the task.
Instruction set
Main article: Atmel AVR instruction set
The AVR instruction set is more orthogonal than those of most eight-bit microcontrollers, in
particular the 8051 clones and PIC microcontrollers with which AVR competes today.
However, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that are different from each
other.
Register locations R0 to R15 have different addressing capabilities than register locations
R16 to R31.
I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63.
CLR affects flags, while SER does not, even though they are complementary instructions.
CLR set all bits to zero and SER sets them to one. (Note that CLR is pseudo-op for EOR
R, R; and SER is short for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.)
Accessing read-only data stored in the program memory (flash) requires special LPM
instructions; the flash bus is otherwise reserved for instruction memory.
Additionally, some chip-specific differences affect code generation. Code pointers (including
return addresses on the stack) are two bytes long on chips with up to 128 kBytes of flash
memory, but three bytes long on larger chips; not all chips have hardware multipliers; chips
with over 8 kBytes of flash have branch and call instructions with longer ranges; and so
forth.
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The mostly regular instruction set makes programming it using C (or even Ada) compilers
fairly straightforward. GCC has included AVR support for quite some time, and that support
is widely used. In fact, Atmel solicited input from major developers of compilers for small
microcontrollers, to determine the instruction set features that were most useful in a compiler
for high-level languages.
MCU speed
The AVR line can normally support clock speeds from 0 to 20 MHz, with some devices
reaching 32 MHz. Lower powered operation usually requires a reduced clock speed. All
recent (Tiny, Mega, and Xmega, but not 90S) AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry. Some AVRs also have a system clock
prescaler that can divide down the system clock by up to 1024. This prescaler can be
reconfigured by software during run-time, allowing the clock speed to be optimized.
Since all operations (excluding literals) on registers R0 - R31 are single cycle, the AVR can
achieve up to 1 MIPS per MHz, i.e. an 8 MHz processor can achieve up to 8 MIPS. Loads
and stores to/from memory take two cycles, branching takes two cycles. Branches in the
latest "3-byte PC" parts such as ATmega2560 are one cycle slower than on previous devices.
1.3 Development and Features
AVRs have a large following due to the free and inexpensive development tools
available, including reasonably priced development boards and free development software. The
AVRs are sold under various names that share the same basic core, but with different peripheral
and memory combinations. Compatibility between chips in each family is fairly good, although
I/O controller features may vary.
See external links for sites relating to AVR development.
Features
Current AVRs offer a wide range of features:
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Multifunction, bi-directional general-purpose I/O ports with configurable, built-in pull-up
resistors
Multiple internal oscillators, including RC oscillator without external parts
Internal, self-programmable instruction flash memory up to 256 kB (384 kB on XMega)
In-system programmable using serial/parallel low-voltage proprietary interfaces or JTAG
Optional boot code section with independent lock bits for protection
On-chip debugging (OCD) support through JTAG or debugWIRE on most devices
The JTAG signals (TMS, TDI, TDO, and TCK) are multiplexed on GPIOs. These pins
can be configured to function as JTAG or GPIO depending on the setting of a fuse bit,
which can be programmed via ISP or HVSP. By default, AVRs with JTAG come with
the JTAG interface enabled.
debugWIRE uses the /RESET pin as a bi-directional communication channel to access
on-chip debug circuitry. It is present on devices with lower pin counts, as it only requires
one pin.
Internal data EEPROM up to 4 kB
Internal SRAM up to 16 kB (32 kB on XMega)
External 64 kB little endian data space on certain models, including the Mega8515 and
Mega162.
The external data space is overlaid with the internal data space, such that the full 64 kB
address space does not appear on the external bus and accesses to e.g. address
010016 will access internal RAM, not the external bus.
In certain members of the XMega series, the external data space has been enhanced to
support both SRAM and SDRAM. As well, the data addressing modes have been
expanded to allow up to 16 MB of data memory to be directly addressed.
AVRs generally do not support executing code from external memory.
Some ASSPs using the AVR core do support external program memory.
8-bit and 16-bit timers
PWM output (some devices have an enhanced PWM peripheral which includes a dead-
time generator)
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Input capture that record a time stamp triggered by a signal edge
Analog comparator
10 or 12-bit A/D converters, with multiplex of up to 16 channels
12-bit D/A converters
A variety of serial interfaces, including
IC compatible Two-Wire Interface (TWI)
Synchronous/asynchronous serial peripherals (UART/USART) (used with RS-232, RS-
485, and more)
Serial Peripheral Interface Bus (SPI)
Universal Serial Interface (USI) for two or three-wire synchronous data transfer
Brownout detection
Watchdog timer (WDT)
Multiple power-saving sleep modes
Lighting and motor control (PWM-specific) controller models
CAN controller support
USB controller support
Proper full-speed (12 Mbit/s) hardware & Hub controller with embedded AVR.
Also freely available low-speed (1.5 Mbit/s) (HID) bitbanging software emulations
Ethernet controller support
LCD controller support
Low-voltage devices operating down to 1.8 V (to 0.7 V for parts with built-in DCDC
upconverter)
picoPower devices
DMA controllers and "event system" peripheral communication.
Fast cryptography support for AES and DES.
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Fig 1.3 Uniboard development board
1.4 Programming interfaces:
There are many means to load program code into an AVR chip. The methods to
program AVR chips varies from AVR family to family.
ISP
Fig 1.4.6 10-pin ISP header diagrams
The in-system programming (ISP) programming method is functionally performed through SPI,
plus some twiddling of the Reset line. As long as the SPI pins of the AVR are not connected to
anything disruptive, the AVR chip can stay soldered on a PCB while reprogramming. All that is
needed is a 6-pin connector and programming adapter. This is the most common way to develop
with an AVR. The Atmel AVR ISP mkII device connects to a computer's USB port and performs
in-system programming using Atmel's software. AVRDUDE (AVR Downloader/UploaDEr) runs
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on Linux, FreeBSD, Windows, and Mac OS X, and supports a variety of in-system programming
hardware, including Atmel AVR ISP mkII, Atmel JTAG ICE, older Atmel serial-port based
programmers, and various third-party and "do-it-yourself" programmers.
PDI
The Program and Debug Interface (PDI) is an Atmel proprietary interface for external
programming and on-chip debugging of XMEGA devices. The PDI supports high-speed
programming of all non-volatile memory (NVM) spaces; flash, EEPROM, fuses, lock-bits and
the User Signature Row. This is done by accessing the XMEGA NVM controller through the
PDI interface, and executing NVM controller commands. The PDI is a 2-pin interface using the
Reset pin for clock input (PDI_CLK) and a dedicated data pin (PDI_DATA) for input and
output.
High voltage serial
High-voltage serial programming (HVSP) is mostly the backup mode on smaller AVRs. An 8-
pin AVR package does not leave many unique signal combinations to place the AVR into a
programming mode. A 12 volt signal, however, is something the AVR should only see during
programming and never during normal operation.
High voltage parallel
High voltage parallel programming (HVPP) is considered the "final resort" and may be the only
way to fix AVR chips with bad fuse settings.
ROM
The AT90SC series of AVRs are available with a factory mask-ROM rather than flash for
program memory.[15] Because of the large up-front cost and minimum order quantity, a mask-
ROM is only cost-effective for high production runs.
aWire
aWire is a new one-wire debug interface available on the new UC3L AVR32 devices.
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1.5 Debugging interfaces
The AVR offers several options for debugging, mostly involving on-chip debugging while
the chip is in the target system.
Debug WIRE
Debug WIRE is Atmel's solution for providing on-chip debug capabilities via a single
microcontroller pin. It is particularly useful for lower pin count parts which cannot provide the
four "spare" pins needed for JTAG. The JTAGICE mkII, mkIII and the AVR Dragon support
debug WIRE. It was developed after the original JTAGICE release, and now clones support it.
JTAG
The Joint Test Action Group (JTAG) feature provides access to on-chip debugging
functionality while the chip is running in the target system. JTAG allows accessing internal
memory and registers, setting breakpoints on code, and single-stepping execution to observe
system behaviour.
Atmel provides a series of JTAG adapters for the AVR:
1. The JTAGICE 3 is the latest member of the JTAGICE family (JTAGICE mkIII). It
supports JTAG, aWire, SPI, and PDI interfaces.
2. The JTAGICE mkII replaces the JTAGICE and is similarly priced. The JTAGICE mkII
interfaces to the PC via USB, and supports both JTAG and the newer debugWIRE
interface. Numerous third-party clones of the Atmel JTAGICE mkII device started
shipping after Atmel released the communication protocol.
3. The AVR Dragon is a low-cost (approximately $50) substitute for the JTAGICE mkII for
certain target parts. The AVR Dragon provides in-system serial programming, high-
voltage serial programming and parallel programming, as well as JTAG or debugWIRE
emulation for parts with 32 KB of program memory or less. ATMEL changed the
debugging feature of AVR Dragon with the latest firmware of AVR Studio 4 - AVR
Studio 5 and now it supports devices over 32 KB of program memory.
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4. The JTAGICE adapter interfaces to the PC via a standard serial port. Although the
JTAGICE adapter has been declared "end-of-life" by Atmel, it is still supported in AVR
Studio and other tools.
JTAG can also be used to perform a boundary scan test, which tests the electrical connections
between AVRs and other boundary scan capable chips in a system. Boundary scan is well-suited
for a production line, while the hobbyist is probably better off testing with a multimeter or
oscilloscope.
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CHAPTER 2
AVR ATmega64A PERIPHERALS
The AVR architecture has two main memory spaces, the Data Memory and the Program
Memory space. In addition, the ATmega64 features an EEPROM Memory for data storage. All
three memory spaces are linear and regular.
In-System Reprogrammable Flash Program Memory
The ATmega64 contains 64 Kbytes On-chip In-System Reprogrammable Flash memory
for program storage. Since all AVR instructions are 16 bits or 32 bits wide, the Flash is
organized as 32K x 16. For software security, the Flash Program memory space is divided into
two sections,
Boot Program section and Application Program section. The Flash memory has an endurance of
at least 10,000 write/erase cycles. The ATmega64 Program Counter (PC) is 15 bits wide, thus
addressing the 32K program memory locations. Constant tables can be allocated within the entire
program memory address space (see the LPM Load Program Memory instruction description).
SRAM Data Memory
The ATmega64 is a complex microcontroller with more peripheral units than can be
supported
within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the
Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used. The Extended I/O space does not exist when the ATmega64 is in the
ATmega103 compatibility mode. The first 4,352 data memory locations address both the
Register File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32
locations address the Register File, the next 64 location the standard I/O memory, then 160
locations of Extended I/O memory, and the next 4,096 locations address the internal data SRAM.
In ATmega103 compatibility mode, the first 4,096 data memory locations address both the
Register
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File, the I/O memory and the internal data SRAM. The first 32 locations address the Register
File, the next 64 location the standard I/O memory, and the next 4,000 locations address the
internal data SRAM.
Fig 2.1 Program memory
2.1 Interrupts
Address Source Interrupt Definition
1 0x0000 RESET External Pin, Power-on Reset, Brown-outReset,
Watchdog Reset, and JTAG AVR Reset
2 0x0002 INT0 External Interrupt Request 0
3 0x0004 INT1 External Interrupt Request 1
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4 0x0006 INT2 External Interrupt Request 2
5 0x0008 INT3 External Interrupt Request 3
6 0x000A INT4 External Interrupt Request 4
7 0x000C INT5 External Interrupt Request 5
8 0x000E INT6 External Interrupt Request 6
9 0x0010 INT7 External Interrupt Request 7
10 0x0012 TIMER2 COMP Timer/Counter2 Compare Match
11 0x0014 TIMER2 OVF Timer/Counter2 Overflow
12 0x0016 TIMER1 CAPT Timer/Counter1 Capture Event
13 0x0018 TIMER1 COMPA Timer/Counter1 Compare Match A
14 0x001A TIMER1 COMPB Timer/Counter1 Compare Match B
15 0x001C TIMER1 OVF Timer/Counter1 Overflow
16 0x001E TIMER0 COMP Timer/Counter0 Compare Match
17 0x0020 TIMER0 OVF Timer/Counter0 Overflow
18 0x0022 SPI, STC SPI Serial Transfer Complete
19 0x0024 USART0, RX USART0, Rx Complete
20 0x0026 USART0, UDRE USART0 Data Register Empty
21 0x0028 USART0, TX USART0, Tx Complete
22 0x002A ADC ADC Conversion Complete
23 0x002C EE READY EEPROM Ready
24 0x002E ANALOG COMP Analog Comparator
25 0x0030 TIMER1 COMPC Timer/Countre1 Compare Match C
26 0x0032 TIMER3 CAPT Timer/Counter3 Capture Event
27 0x0034 TIMER3 COMPA Timer/Counter3 Compare Match A
28 0x0036 TIMER3 COMPB Timer/Counter3 Compare Match B
29 0x0038 TIMER3 COMPC Timer/Counter3 Compare Match C
30 0x003A TIMER3 OVF Timer/Counter3 Overflow
31 0x003C USART1, RX USART1, Rx Complete
The most typical and general program setup for the Reset and Interrupt Vector Addresses in
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ATmega64 is:
Address Labels Code Comments
0x0000 jmp RESET ; Reset Handler
0x0002 jmp EXT_INT0 ; IRQ0 Handler
0x0004 jmp EXT_INT1 ; IRQ1 Handler
0x0006 jmp EXT_INT2 ; IRQ2 Handler
0x0008 jmp EXT_INT3 ; IRQ3 Handler
0x000A jmp EXT_INT4 ; IRQ4 Handler
0x000C jmp EXT_INT5 ; IRQ5 Handler
0x000E jmp EXT_INT6 ; IRQ6 Handler
0x0010 jmp EXT_INT7 ; IRQ7 Handler
0x0012 jmp TIM2_COMP ; Timer2 Compare Handler
0x0014 jmp TIM2_OVF ; Timer2 Overflow Handler
0x0016 jmp TIM1_CAPT ; Timer1 Capture Handler
0x0018 jmp TIM1_COMPA ; Timer1 CompareA Handler
0x001A jmp TIM1_COMPB ; Timer1 CompareB Handler
0x001C jmp TIM1_OVF ; Timer1 Overflow Handler
0x001E jmp TIM0_COMP ; Timer0 Compare Handler
0x0020 jmp TIM0_OVF ; Timer0 Overflow Handler
The General Interrupt Control Register controls the placement of the Interrupt Vector table.
MCUCR MCU Control Register
7 6 5 4 3 2 1 0
SRE SRW10 SE SM1 SM0 SM2 IVSEL IVCE
Bit 1 IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the
Flash Memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the
Boot Loader section of the Flash. The actual address of the start of the Boot Flash section is
determined by the BOOTSZ Fuses. To avoid unintentional changes of Interrupt Vector tables, a
special write procedure must be followed to change the IVSEL bit:
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1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are
disabled in the cycle IVCE is set, and they remain disabled until after the instruction following
the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit
in the Status Register is unaffected by the automatic disabling.
Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is
programmed, interrupts are disabled while executing from the Application section. If Interrupt
Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts
are disabled while executing from the Boot Loader section.
Bit 0 IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared
by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will
disable interrupts, as explained in the IVSEL description above.
2.2 I/O Ports
All AVR ports have true Read-Modify-Write functionality when used as general digital
I/O ports. This means that the direction of one port pin can be changed without unintentionally
changing the direction of any other pin with the SBI and CBI instructions. The same applies
when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if
configured as input). Each output buffer has symmetrical drive characteristics with both high
sink and source capability. The pin driver is strong enough to drive LED displays directly. All
port pins have individually selectable pull-up resistors with a supply voltage invariant
resistance.
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Fig 2.2 I/O Pin Equivalent Schematic
All registers and bit references in this section are written in general form. A lower case
x represents the numbering letter for the port, and a lower case n represents the bit number.
However,when using the register or bit defines in a program, the precise form must be used (i.e.,
PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn). Three I/O memory
address locations are allocated for each port, one each for the Data Register PORTx, Data
Direction Register DDRx, and the Port Input Pins PINx. The Port Input Pins I/O location is
read only, while the Data Register and the Data Direction Register are read/write. In addition, the
Pull-up Disable PUD bit in SFIOR disables the pull-up function for all pins in all ports when
set.
Note that enabling the alternate function of some of the port pins does not affect the use of
the other pins in the port as general digital I/O.
Alternate Functions of Port A
The Port A has an alternate function as the address low byte and data lines for the External
Memory Interface.
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Port Pin Alternate Function
PA7 AD7 (External memory interface address and data bit 7)
PA6 AD6 (External memory interface address and data bit 6)
PA5 AD5 (External memory interface address and data bit 5)
PA4 AD4 (External memory interface address and data bit 4)
PA3 AD3 (External memory interface address and data bit 3)
PA2 AD2 (External memory interface address and data bit 2)
PA1 AD1 (External memory interface address and data bit 1)
PA0 AD0 (External memory interface address and data bit 0)
Table 2.2.1 Port A Pins Alternate Functions
SignalName PA7/AD7 PA6/AD6 PA5/AD5 PA4/AD4 PUOE SRE SRE SRE SRE PUOV ~(WR | ADA)
PORTA7PUD ~(WR|ADA)
PORTA6PUD ~(WR | ADA) PORTA5 PUD
~(WR | ADA)
PORTA4 PUD
DDOE SRE SRE SRE SRE DDOV WR | ADA WR | ADA WR | ADA WR | ADA PVOE SRE SRE SRE SRE PVOV A7 ADA | D7
OUTPUT WR
A6 ADA | D6 OUTPUT WR
A5 ADA | D5 OUTPUT WR
A4 ADA | D4 OUTPUT WR
DIEOE 0 0 0 0 DIEOV 0 0 0 0
DI D7 INPUT D6 INPUT D5 INPUT D4 INPUT
AIO
Table 2.2.2 Overriding Signals for Alternate Functions in PA7..PA4
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Signal Name PA3/AD3 PA2/AD2 PA1/AD1 PA0/AD0
PUOE SRE SRE SRE SRE
PUOV ~(WR | ADA) PORTA3 PUD
~(WR | ADA) PORTA2 PUD
~(WR | ADA) PORTA1 PUD
~(WR | ADA) PORTA0 PUD
DDOE SRE SRE SRE SRE
DDOV WR | ADA WR | ADA WR | ADA WR | ADA
PVOE SRE SRE SRE SRE
PVOV A3 ADA | D3 OUTPUT WR
A2 ADA | D2 OUTPUT WR
A1 ADA | D1 OUTPUT WR
A0 ADA | D0 OUTPUT WR
DIEOE 0 0 0 0
DIEOV 0 0 0 0
DI D3 INPUT D2 INPUT D1 INPUT D0 INPUT
AIO
Table 2.2.3. Overriding Signals for Alternate Functions in PA3..PA0
Alternate Functions of Port C
In ATmega103 compatibility mode, Port C is output only. The Port C has an alternate
function as the address high byte for the External Memory Interface.
Port Pin Alternate Function
PC7 A15
PC6 A14
PC5 A13
PC4 A12
PC3 A11
PC2 A10
PC1 A9
PC0 A8
Table 2.2.4 Port C Pins Alternate Functions
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Signal Name PC7/A15 PC6/A14 PC5/A13 PC4/A12
PUOE SRE
(XMM
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DIEOE 0 0 0 0
DIEOV 0 0 0 0
DI
AIO
Table 2.2.6 Overriding Signals for Alternate Functions in PC3..PC0
2.3 USART
The Universal Synchronous and Asynchronous serial Receiver and Transmitter
(USART) is a
highly flexible serial communication device. The main features are:
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
3.3.1 Dual USART
The ATmega64 has two USARTs, USART0 and USART1. USART0 and USART1 have
different I/O Registers. Note that in ATmega103 compatibility mode, USART1 is not available,
neither is the UBRR0H or UCRS0C registers. This means that in ATmega103 compatibility
mode, the ATmega64 supports asynchronous operation of USART0 only.
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Fig 2.3.1 USART Block Diagram
The dashed boxes in the block diagram separate the three main parts of the USART (listed
from the top): Clock generator, Transmitter and Receiver. Control registers are shared by all
units.The Clock Generation logic consists of synchronization logic for external clock input used
by synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is
only
used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial
Shift Register, Parity Generator and Control Logic for handling different serial frame formats.
The write buffer allows a continuous transfer of data without any delay between frames. The
Receiver is the most complex part of the USART module due to its clock and data recovery
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units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the Receiver includes a Parity Checker, Control Logic, a Shift Register and a two level
receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
AVR USART vs. AVR UART Compatibility
The USART is fully compatible with the AVR UART regarding:
Bit locations inside all USART Registers
Baud Rate Generation.
Transmitter Operation.
Transmit Buffer Functionality.
Receiver Operation.
However, the receive buffering has two improvements that will affect the compatibility in some
Special cases:
A second buffer register has been added. The two buffer registers operate as a circular FIFO
buffer. Therefore the UDRn must only be read once for each incoming data! More important
is the fact that the error flags (FEn and DORn) and the ninth data bit (RXB8n) are buffered
with the data in the receive buffer. Therefore the status bits must always be read before the
UDRn Register is read. Otherwise the error status will be lost since the buffer state is lost.
The Receiver Shift Register can now act as a third buffer level. This is done by allowing the
received data to remain in the serial Shift Register if the buffer registers are full, until a new start
bit is detected. The USART is therefore more resistant to Data Over Run (DORn) error
conditions.
The following control bits have changed name, but have same functionality and register location:
CHR9 is changed to UCSZn2.
OR is changed to DORn.
Clock Generation The Clock Generation logic generates the base clock for the Transmitter and
Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double
Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSELn bit in
USART Control and Status Register n C (UCSRnC) selects between asynchronous and
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synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2Xn
found in the UCSRnB Register. When using synchronous mode (UMSELn = 1), the Data
Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal
(Master mode) or external (Slave mode). The XCK pin is only active when using synchronous
mode.
External Clock External clocking is used by the synchronous slave modes of operation. External
clock input from the XCK pin is sampled by a synchronization register to minimize the chance of
meta-stability. The output from the synchronization register must then pass through an edge
detector before it can be used by the Transmitter and Receiver. This process introduces a two
CPU clock period delay and therefore the maximum external XCK clock frequency is limited by
the following equation:
>8);
UBRR1L=(unsigned char)(ubrr);
UCSR1C|=((1
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{
p++;
*p=uart1_read_data();
}
*p=0;
}
Header file to enable LCD Module:
//#define F_CPU 12000000UL
#include
#include
#include
#define rs PA0
#define rw PA1
#define en PA2
void lcd_init();
void dis_cmd(char);
void dis_data(char);
void lcdcmd(char);
void lcddata(char);
void lcd_init() // fuction for intialize
{
DDRA=0xFF;
dis_cmd(0x02); // to initialize LCD in 4-bit mode.
dis_cmd(0x28); //to initialize LCD in 2 lines, 5X7 dots and 4bit mode.
dis_cmd(0x0F);
dis_cmd(0x06);
dis_cmd(0x01);
_delay_ms(10);
}
void dis_cmd(char cmd_value)
{
char cmd_value1;
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cmd_value1 = cmd_value & 0xF0; //mask lower nibble because PA4-PA7 pins
are used.
lcdcmd(cmd_value1); // send to LCD
cmd_value1 = ((cmd_value
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dis_cmd(0x80+x);
}
else
{
dis_cmd(0xc0+x);
}
}
void disp_string(char *p)
{
while(*p!=0)
{
dis_data(*p);
p++;
}
}
void disp_clear()
{
dis_cmd(0x01);
_delay_ms(10);
}
Header file to enable ADC:
//for X axis and Yaxis simultaneously moving
#include //uart1.h is used to see de disply de o/p
#include
//for x-axis
void adc_x_init()
{
ADMUX&=~(1
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//for y-axis
void adc_y_init()
{
ADMUX&=~(1
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Embedded C Program:
//thanks to think labs
//mini project by J PAVAN KUMAR , HAREENSAI JAVAGI, P.DINESH KUMAR
// VARDHAMAN COLLEGE OF ENGINEERING
//before start of experiment place a wire from PORTC to soil and another wire from Ground Pin
of ADC PORT i.e PORT F to soil
//connect the dc enable wire of relay to 5th analog pin of portF (ADC SENSOR PORTS); ( start
count from 0 from right to left)
//if soil is wet the ac device and dc motor will be off
//if soil is wet ac device and dc motor will be on
#include
#include
#define SET_BIT(a,b) a|=(1
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void timer1_init()
{
TCCR1A=(1
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lcd_gotoxy(0,1);
disp_string("only if soil is");
lcd_gotoxy(0,2);
disp_string("dry ");
lcd_gotoxy(0,1);
disp_string("Press Switch4 to");
lcd_gotoxy(0,2);
disp_string("To OFF Relay&DC");
_delay_ms(5000);
lcd_gotoxy(0,1);
disp_string(" Temperature. ");
lcd_gotoxy(0,2);
disp_string(" :-p :-0 :-) ");
_delay_ms(1000);
unsigned char temp;
DDRA = 0xff;
DDRC = 0;
PORTC = 0xff;
CLR_BIT(DDRD,6);
SET_BIT(PORTD,6);
CLR_BIT(DDRD,7);
SET_BIT(PORTD,7);
CLR_BIT(DDRE,6);
SET_BIT(PORTE,6);
CLR_BIT(DDRE,7);
SET_BIT(PORTE,7);
init_adc();
while(1)
{
if(!(PIND&(1
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{
PORTF |= (1
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_delay_ms(500);
if(!(PINE&(1
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timer1_init();
while(1)
{
OCR1A=30000;
_delay_ms(100);
if(!(PINE&(1
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}
else if((!(PINE&(1