CR-GENI - GENI Open Cognitive Radio Platform Dirk Grunwald , Peter Wolniansky, Prasanthi Maddala, Khanh Le, Ivan

Seskar

R4 Development Framework: Radio System with Pluggable User Applications

RTS

HW Platform - Phase 0

• Xilinx V5LX50 FPGA• Gigabit Ethernet• 2 Half duplex RF modules• 20 MHz band• 2.4 GHz, 5 GHz

Flexible IP/VITA Parser

Flexible Packet Processing

HW Platform - Phase 1

• V5LX50/SX95• PCI express bus• 4 Full duplex RF modules• 25 MHz baseband• 300 – 6000 MHz

VRT Receiver

Lookup using PortID

dMAC/Ethertype from IPProcessor

if (IP == 1) then Enable IP processing (append dIP, sIP & UDP) Forward dMAC/Ethertype (Note, sMAC provided in RMAP)

else

Disable IP Processing Forward dMAC/Ethertype (Note, sMAC provided in RMAP)

endif

Lookup using PortID

if (V == 1) then Enable VITA formatting else

Disable VITA formatting endif

dMAC/Ethertype appended to IP/VITA data

Forward ethernet payload if :

incoming MAC = dMAC incoming MAC = Broadcast

Append Ethertype field (16-bit) to ethernet payload

if (ethertype == IPv4 & Incoming IP == dIP & UDP = 1000) then forward UDP payload to VITA Receiver

else

forward packet to PCORE

PCORE CMD FORMAT

If (V==1) then VITA context packetElse non-VITA packet use ethertype field for further parsingEndif;

Ethertype = 0x0800 - IPv4 0x0806 - ARP

Use CMD_CNT as ACK to MEM_CTL to indicate completion of PCORE data removal from MEM.