CPLD 3.1

Note: We use the Altera CPLD design software in this course. Please see the Altera web site (www.altera.com) for more details on their product and design solutions.

Last Mod: November 2013©Paul R. Godin

CPLD 3.2

Introduction

Due to their numerous advantages, programmable logic devices are becoming predominant in the digital logic industry.

CPLD logic design is as basic or complex as you want it to be.

This presentation addresses the setup and basic design processes.

This course makes use of the Altera devices and software. See www.altera.com for more information.

CPLD 3.3

CPLDs have 2 basic methods for designing logic circuits:

• Graphical• Text (VHDL)

CPLD 3.4

CPLD 3.5

Graphical

Graphical design is used when a visual design process is desired (similar to Electronics WorkBench / Multisim).

Examples of visual design components: Logic Gates Latches and Flip-Flops Counters and Registers Multiplexers and De-multiplexers Etc…

CPLD 3.6

Templates

Templates, called SYMBOLS, are available for more complex devices.

See the Altera software for a list of the available devices. Many are listed using easy-to-read notation or industry-standard model/part numbers.

Custom design templates may also be created.

CPLD 3.7

A few of the device symbols available in the CPLD software.

CPLD 3.8

CPLD 3.9

1-Launch the Quartus II software

2-Create a New Project: File New Project Wizard

Creating a Logic Design with Quartus II:

On “Page 1 of 5”•Select the working directory for the project (create a new folder if needed)•Name the project

Skip Page 2

On “Page 3 of 5” select the device:Family: MAX7000SDevice: EPM7064SLC44-10

Skip Page 4, select “Finish” on Page 5

CPLD 3.10

Quartus II Rev 13.0.1: Main Screen

CPLD 3.11

Using the Quartus II Software

To open a Graphic Editor workspace: Select “File”, “New” Select “Block Diagram/Schematic File”

This opens a workspace with a grid

To add a logic symbol double-click anywhere on the blank window. This opens a “Symbol” window. Navigate: click on the “+” symbol to the left

of the folder to expand it Logic Elements: located under “primitives”,

“logic”

Hint: Right-click in the work area will also open the Symbol Window.

CPLD 3.12

Symbol WindowThe symbol window contains many of the basic logic symbols needed for a basic logic design.

The short-hand used to describe the symbols should be clear enough. To see what a symbol looks like before using it in a design, single-click on it. To select, click “OK”

CPLD 3.13

Interconnection of devices Click and drag the

elements to where you want to place them.

To interconnect inputs and outputs, click from one input/output and drag the line to the connection point.

Hint: if the devices are out of alignment, add mid-points (route at 90 degree angles) so that the devices can connect to the point “head-on”. If not, there is a risk of having an open without realizing it.

No Yes

Using the Quartus II Software

CPLD 3.14

Inputs and Outputs Inputs and outputs are graphic elements that must be

added. They must be re-labeled. Just highlight the “PIN_NAME”

and add the new label. Do not use spaces. Do not exceed 8 characters. Do not use reserved words (example: “IN” and “OUT” are reserved)

Hint: If there are several elements to add, such as multiple inputs and outputs, a copy-paste can be done. Use right-click on the device to open a menu. Use SHIFT key to select multiple elements.

Using the Quartus II Software

CPLD 3.15

An example of a graphic design

CPLD 3.16

Compiling

Before proceeding, you should save and compile the file. Select the “purple triangle” symbol

The project cannot have critical errors (warnings are expected).

CPLD 3.17

Assigning Pins

Once all of the logic elements have been added and interconnected, logical connections to the physical pins need to be established.

Some of the pins are reserved for the parallel cable, JTAG connections (in more advanced devices), Vcc, and Ground connections. Do not use these pins for I/O!

NOTE: The Pin-Out is available in the device specification sheet from Altera. In the software, go to the Floorplan and double-click on any of the LABs that pop up. Alternately, the pinout for the devices used in lab is on the following slide…

CPLD 3.18

Pin

-Out

From

Alt

era

’s M

70

00

.pdf

speci

fica

tion s

heet

CPLD 3.19

Assigning Pins

The pins marked I/O are available to use as either input or output. Decide which pins will be used for the design.

Assign the pins using the pin planning tool.

The tool provides graphic guidance on the pins that have been used.

Once completed, the project must be recompiled.

CPLD 3.20

Writing to the device Once satisfied with the design it needs to be re-saved and

re-compiled. The compiler translates from a higher-level language to binary values that the hardware device can understand.

Once compiled without error, connect the device to via the adapter to the USB port of your system. The CPLD board should have Vcc and Ground connection ONLY, and power applied.

Select Programmer from the menu and click on Program. A few seconds later and the device should be programmed.

Do not connect input devices such as switches until the programming is complete. Damage will occur.

CPLD 3.21

Overview

Setting up the software and hardware defaults should be a one-time process.

When designing a circuit using the graphics editor, the following basic steps should be followed:

1. Open a new “gdf” file and save it2. Design the circuit, including input and output elements3. Rename the inputs and outputs4. Assign the device and Compile5. Assign each of the input and output pins6. Compile and save7. Program the device

CPLD 3.22

Advantages to Graphical Design

Easier to visualize and understand a circuit and its logic flow.

Easier for some specific, moderately complex logic such as shift registers and counters.

Easy to re-create an existing or previously designed logic diagram directly as a logic diagram in the CPLD software.

User can create new graphical models to use. Easier for users with a basic to intermediate

digital electronics background.

CPLD 3.23

Disadvantages to Graphical Design

Takes much longer to design more complex circuits that may require extensive design time (especially Boolean-based circuits such as decoders).

More complex circuits means difficulty routing wires and troubleshooting.

Limited logic operations to the device models available.

Files created are proprietary, so will only work with that manufacturer’s software and devices.

CPLD 3.24

Floorplan

The Floorplan is the physical layout of the compiled design, and provides another means of viewing the reduced design.

1. Compile the project

2. Go to the Floorplan tool

3. Check the lines indicated in the Layout menu

NOTE: OLDER SOFTWARE VERSION

CPLD 3.25

Floorplan

The diagram indicates the LABs (Logic Array Blocks) and the connections indicated in your design.

NOTE: OLDER SOFTWARE VERSION

CPLD 3.26

Floorplan

Double-click on a LAB provides the physical device pinout.

Note the color coding used to identify the various inputs and outputs.

Clicking on an output will provide the simplified equation at bottom.

NOTE: OLDER SOFTWARE VERSION

CPLD 3.27

Exercise

Design the following circuit using the graphical design tool in Altera’s Quartus II software, and simulate the output:

CPLD 3.28

CPLD 3.29

Quirks and Tips #1

The Quartus II software tools and the MAX series of hardware sometimes responds in an unusual fashion in some situations. Here is a list of those identified “challenges”:

Be aware that most CPLDs require an external source of edges, and these edges must follow certain parameters (the steeper the edge the better). The oscillator on the experimenter’s boards may not be appropriate. Use a 74LS14 to clean up the edges. The edge-sensitive input on the 7032 and 7064 are pins 43 and 2.

The Entity name and the file name must be the same on a VHDL design.

If you get a “WORK” error when compiling a file, try saving it to a different directory. The software saves several files with each design file.

There are timing problems with truncated asynchronous counters when using the graphics design tool. Use synchronous counters.

CPLD 3.30

Quirks and Tips #2

Saving files to the desktop is not recommended. Many files are created with the designs, and the path name to the desktop may be too long.

There may be timing problems in some circuit designs. The actual internal functionality of a logic design is different from an equivalent standard TTL/CMOS gate circuit. Propagation delay is not accurately represented. If gates are added to create extra delay, the program will eliminate what it considers redundant gates.

Output high current for the device (IOH) is relatively low and loading the output will likely cause the voltage (VOH) to drop, causing faults with logic operation. Configure the loading devices to operate with active low logic.

CPLD 3.31

CAUTIONS

A list of cautions when using the CPLD NEVER connect inputs and outputs of a chip before

programming it. There is likely a previous program already loaded on the chip and you may inadvertently create a short circuit on an output. These devices are much more sensitive to short circuits and voltage problems. When using a device, first connect the Vcc and Ground, then connect the programming cable and program it, then carefully connect the inputs and outputs.

There are maximum current carrying capabilities for outputs. Refer to the specification sheet to make sure that IOH and IOL are not exceeded.

CPLD 3.32

CAUTIONS

There may be a mix of devices in the device boards. Some may be 7032’s and others may be 7064’s. Please check before attempting to program the device.

CPLD 3.33

End

©Paul R. Godinprgodin @ gmail.com