COSC 3430

Midterm Review

Some old midterm questions• 1. Write the hexadecimal representation of binary

1011010100100110

• 2. What is the sum of hexadecimal 0BCA and 3FC9? • 3. Suppose in the machine translation of the

instruction bne $t0, $s0, label the 16 bit address segment has the value 0x0820 and the program counter (PC) register has the value 0x7B5D3B5C. What is the 32 bit address of label?

4. How can one determine when the result of an unsigned addition operation on 32 bit binary integers causes overflow?

When the carry out of the 31st bit is 1

Use the following data to answer questions 5-8. Assume that ArrayB begins at 0x10010000:.dataArrayB: .byte 0x10,0x20,0x30,0x40,0x50,0x60ArrayW: .half 0x89AB,0x6543Str: .asciiz “abcd”ArrayD: .word 0x12345678

Data stored in memory as follows: 10 20 30 40 50 60 AB 89 43 65 61 62 63 64 00 00 78 56 34 12

5. What will be the value of $s0 after the following sequence of statements execute? la $a0, ArrayBlh $s0, 2($a0)

4030

6. What will be the value of $s0 after the following statements execute? la $a0, ArrayWaddi $a0, $a0, 2lb $s0, 0($a0)

43 What if 43 were 83? What would $s0 be?

7. What will be printed to the screen after the following statements execute?

la $a0, ArrayWaddi $a0, $a0, 3li $v0, 4Syscall

eabcd

8. What will be printed to the screen after the following statements execute?

la $a0, ArrayDaddi $a0, $a0, -8li $v0, 4Syscall

Ceabcd

9. What value will be moved to $a0 and $t1 after the following statements have executed?

addi $a0, $0, 0x1234 # $a0 = 00001234addi $t1, $0, 0x789A # $t1 = 0000789asll $a0, $a0, 16 # $a0 = 12340000and $a0, $a0, $t1 # $a0 = 00000000or $t1, $a0, $t1 # $t1 = 0000789asll $a0, $t1, 8 # $a0 = 00789a00add $a0, $a0, $t1 # $a0 = 0079129a $t1 = 0000789a

10. Write a sequence of MIPS statements that will write out to the screen the 5th binary bit of a byte stored in the lower byte of $a0. (Hint: You can use logical operations to determine the value of the 5th bit.)

and $s0, $a0, 32srl $s0, $s0, 5move $a0, $s0li $v0, 1syscall

Single Cycle Datapath with Control Unit

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

R-type Instruction Data/Control Flow

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

Load Word Instruction Data/Control Flow

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

Branch Instruction Data/Control Flow

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

Adding the Jump Operation

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

Shiftleft 2

0

1

Jump

32Instr[25-0]

26PC+4[31-28]

28

5.2 Describe the effect that a single stuck-at-0 fault would have for the signals below, in the single-cycle datapath in figure 5.17 on page 307. Which instructions, if any, would work correctly?

• RegWrite = 0: All R-format instructions, in addition to lw, will not work because these instructions will not be able to write their results to the register file. Would not affect any instructions that do not write a register, so far as causing them to execute. It could, of course, cause them to have incorrect arguments.

• ALUOp0 = 0: Branch will not work correctly since the ALUop = 00 will call for addition instead of subtraction (see figure 5.12).

• ALUOp1 = 0: All R-format instructions except addition will not work correctly because this will cause addition always to be performed instead of the required ALU op (see figure 5.13).

• Branch = 0: beq will not execute correctly as the branch address will never be loaded into the PC. (This is equivalent to PCSrc being deasserted which causes PC to always be incremented by 4).

• MemRead = 0: lw will not work correctly since the contents of the memory at the address will not be put on the read data output.

• MemWrite = 0: MemWrite being deasserted will not let the contents at the write data port to be written to memory so sw will not work properly.

Simple datapath with the control unit

Solution: Fetching, reading registers, and writing the destination register takes a total of 300ps for both floating point add/sub and mul/div. Thus, floating point add/sub takes 300ps + 400ps = 700ps, and floating point mul/div takes 300ps + 600ps = 900ps.

We wish to add the jr instruction to the single-cycle-datapath figure 5.17. Add any necessary datapaths and control signals to the single-cycle datatpath and show the necessary addition to figure 5.18.

• Table 5.18 for problem 5.8. JumpReg must be set to 1 so the multiplexor will read the address from register 1 as shown in the diagram above.

Solution: If RegDst = 0, all R-format instructions will not work properly because we will specify the wrong register to write. If ALUSrc = 0, then all I-format instructions except branch will not work because we will not be able to get the sign-extended 16 bits into the ALU. If MemtoReg = 0, then loads will not work. If Zero = 0, the branch instruction will never branch, even when it should.

Solution: No additions to the datapath are required. A new row should be added to the truth table figure 5.18. The new control is similar to lw because we want to use the ALU to add the immediate to a register (and thus RegDst = 0, ALUSrc = 1, ALUOp = 00). The new control is also similar to an R-format instruction because we want to write the result of the ALU into a register (and thus MemtoReg = 0, RegWrite = 1) and of course we aren’t branching or using memory (Branch = 0, MemRead = 0, MemWrite = 0). Modifications to 5.18 are shown on the next chart.

Instruction RegDst ALUSrcMemto-

RegReg

WriteMem Read

Mem Write Branch ALUOp1 ALUp0

R-format 1 0 0 1 0 0 0 1 0lw 0 1 1 1 1 0 0 0 0sw X 1 X 0 0 1 0 0 0beq X 0 X 0 0 0 1 0 1

addi 0 1 0 1 0 0 0 0 0