Cortex-M3 Reference Manual

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Cortex -M3

r2p0

Technical Reference Manual

Copyright 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G

Cortex-M3Technical Reference Manual Copyright 2005-2008 ARM Limited. All rights reserved.Release Information The following changes have been made to this book.Change History Date 15 December 2005 13 January 2006 10 May 2006 27 September 2006 13 June 2007 11 April 2008 26 June 2008 Issue A B C D E F G Confidentiality Confidential Non-Confidential Non-Confidential Non-Confidential Non-Confidential Confidential Non-Confidential Change First Release Confidentiality status amended First Release for r1p0 First Release for r1p1 Minor update with no technical changes Limited release for SC300 r0p0 First Release for r2p0

Proprietary Notice Words and logos marked with or are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. Where the term ARM is used it means ARM or any of its subsidiaries as appropriate. Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to. Unrestricted Access is an ARM internal classification.

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Copyright 2005-2008 ARM Limited. All rights reserved.

ARM DDI 0337GUnrestricted Access

Product Status The information in this document is Final (information on a developed product). Web Addresshttp://www.arm.com

ARM DDI 0337GUnrestricted Access

Copyright 2005-2008 ARM Limited. All rights reserved. Confidential

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Copyright 2005-2008 ARM Limited. All rights reserved.

ARM DDI 0337GUnrestricted Access

Contents Cortex-M3 Technical Reference Manual

PrefaceAbout this book ............................................................................................. xx Feedback .................................................................................................... xxv

Chapter 1

Introduction1.1 1.2 1.3 1.4 1.5 1.6 1.7 About the processor .................................................................................... 1-2 Components, hierarchy, and implementation .............................................. 1-4 Execution pipeline stages ......................................................................... 1-12 Prefetch Unit ............................................................................................. 1-14 Branch target forwarding ........................................................................... 1-15 Store buffers ............................................................................................. 1-18 Product revisions ...................................................................................... 1-19

Chapter 2

Programmers Model2.1 2.2 2.3 2.4 2.5 2.6 About the programmers model ................................................................... 2-2 Privileged access and user access ............................................................. 2-3 Registers ..................................................................................................... 2-4 Data types ................................................................................................. 2-10 Memory formats ........................................................................................ 2-11 Instruction set summary ............................................................................ 2-13

ARM DDI 0337GUnrestricted Access

Copyright 2005-2008 ARM Limited. All rights reserved. Non-Confidential

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Contents

Chapter 3 Chapter 4

System Control3.1 Summary of processor registers ................................................................. 3-2

Memory Map4.1 4.2 4.3 About the memory map .............................................................................. 4-2 Bit-banding ................................................................................................. 4-5 ROM memory table .................................................................................... 4-7

Chapter 5

Exceptions5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 About the exception model ......................................................................... 5-2 Exception types .......................................................................................... 5-4 Exception priority ........................................................................................ 5-6 Privilege and stacks .................................................................................... 5-9 Pre-emption .............................................................................................. 5-11 Tail-chaining ............................................................................................. 5-14 Late-arriving .............................................................................................. 5-15 Exit ............................................................................................................ 5-17 Resets ...................................................................................................... 5-20 Exception control transfer ......................................................................... 5-24 Setting up multiple stacks ......................................................................... 5-25 Abort model .............................................................................................. 5-27 Activation levels ........................................................................................ 5-32 Flowcharts ................................................................................................ 5-34

Chapter 6

Clocking and Resets6.1 6.2 6.3 Clocking ...................................................................................................... 6-2 Resets ........................................................................................................ 6-4 Cortex-M3 reset modes .............................................................................. 6-5

Chapter 7

Power Management7.1 7.2 About power management ......................................................................... 7-2 System power management ....................................................................... 7-3

Chapter 8

Nested Vectored Interrupt Controller8.1 8.2 8.3 About the NVIC ........................................................................................... 8-2 NVIC programmers model ......................................................................... 8-3 Level versus pulse interrupts .................................................................... 8-43

Chapter 9

Memory Protection Unit9.1 9.2 9.3 9.4 9.5 9.6 About the MPU ........................................................................................... 9-2 MPU programmers model .......................................................................... 9-3 MPU access permissions ......................................................................... 9-13 MPU aborts ............................................................................................... 9-15 Updating an MPU region .......................................................................... 9-16 Interrupts and updating the MPU .............................................................. 9-19

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Copyright 2005-2008 ARM Limited. All rights reserved. Non-Confidential

ARM DDI 0337GUnrestricted Access

Contents

Chapter 10

Core Debug10.1 10.2 10.3 10.4 About core debug ...................................................................................... 10-2 Core debug registers ................................................................................ 10-3 Core debug access example .................................................................. 10-12 Using application registers in core debug ............................................... 10-13

Chapter 11

System Debug11.1 11.2 11.3 11.4 11.5 11.6 11.7 About system debug ................................................................................. 11-2 System debug access ............................................................................... 11-3 System debug programmers model ......................................................... 11-5 FPB ........................................................................................................... 11-6 DWT ........................................................................................................ 11-13 ITM .........................................................................................