Product Brief

ARM® CortexTM-M1

Product Summary

Key Features• Designed Specifically for Implementation in FPGAs• 32-Bit RISC Architecture (ARMv6-M) • 32-Bit AHB-Lite Bus Interface• 3-Stage Pipeline • 32-Bit ALU • 32-Bit Memory Addressing Range • Embedded ICE-RT Real-Time Debug Unit • JTAG Interface Unit

Intended Use• MicroTCA• System Management• Avionics• Robotics• Medical Equipment• Automotive Infotainment• Personal Media Players• Wireless Handsets• Digital Still Cameras

Benefits• Fully Implemented in FPGA Fabric• User Can Access All Core Signals and I/Os• User Can Program into FPGA• No License Fees or Royalties• Can Run All Existing Thumb® Code • Upward Compatible with Cortex-M3

Supported Families• Fusion (M1AFS)• IGLOO™ (M1AGL)• IGLOOe (M1AGLE)• ProASIC®3L (M1A3PXXXXL)• ProASIC3 (M1A3P)• ProASIC3E (M1A3PE)

Synthesis and Simulation support• Directly Supported within the Actel Libero®

Integrated Design Environment (IDE)• Synthesis: Synplify® and Design Compiler• Simulation: Vital-Compliant VHDL Simulators and

OVI-Compliant Verilog Simulators

Verification and Compliance• Compliant with ARMv6-M (ARM Cortex-M1)

Instruction Set Architecture (ISA)

Core VersionThis product brief defines the functionality for ARMCortex-M1 v2.2.

Introduction The Cortex-M1 soft IP core is a member of the ARMCortex family of processors and has been optimized foruse in Actel ARM-enabled FPGAs. Refer to the ARMCortex-M1 Handbook for detailed information on theCortex-M1.

The ARM Cortex-M1 is supplied with an AMBA AHB-Liteinterface for inclusion in an AMBA-based processorsystem such as the one generated by the ActelCoreConsole IP deployment platform.

Cortex-M1 ProcessorARM Cortex-M1 is a general purpose, 32-bitmicroprocessor that offers high performance and smallsize in FPGAs. ARM Cortex-M1 runs a subset of theThumb-2 instruction set (ARMv6-M), which includes allbase 16-bit Thumb instructions and a few Thumb-2 32-bitinstructions (BL, MRS, MSR, ISB, DSB, and DMB). Thisenables very tight and efficient code to be written forthe processor that is ideal for the limited memorytypically found in embedded applications.

The main blocks in ARM Cortex-M1 are the processorcore, the Nested Vectored Interrupt Controller (NVIC),the AHB interface, and the debug unit. The processorcore supports 13 general purpose 32-bit registers,including the Link Register (LR), Program Counter (PC),Program Status Register (xPSR), and two banked StackPointers (SP).

Product Brief

January 2008 1© 2008 Actel Corporation See Actel’s website for the latest version of the datasheet

ARM® CortexTM-M1

Figure 1 shows an ARM Cortex-M1 processor with debug block diagram.

The NVIC is closely coupled to the ARM Cortex-M1 coreto achieve low-latency interrupt processing. The versionscurrently available for use in M1 devices support 1interrupt with 4 levels of priority. Future versions willsupport up to 32 interrupts. To simplify softwaredevelopment, the processor state is automatically savedon interrupt entry, and restored on interrupt exist, withno instruction overhead.

The ARM Cortex-M1 Thumb instruction set’s 16-bitinstruction length allows it to approach twice the densityin memory of standard 32-bit ARM code while retainingmost of the ARM performance advantage over atraditional 16-bit processor using 16-bit registers. This ispossible because Thumb code operates on the 32-bitregister set in the processor. Thumb code is able toprovide up to 65% of the code size of ARM, and 160% ofthe performance of an equivalent ARM processorconnected to a 16-bit memory system.

Figure 1 • Processor with Debug Block Diagram

Processor with Debug

AHB-PPB

NVIC

Debug Subsystem

AHB Decoder

AHB Multiplexer

AHB Matrix

Debug ITCM Interface

Debug DTCM Interface

Breakpoint Unit

Data Watchpoint Unit

Debug Control

ROM Table

Internal PPB Signals

External Bus SignalsDAP

AHB-AP SWJ-DP

Memory Interface

ITCM

DTCM

CoreDbg

AHB Master

NVIC Interrupt Interface External Interface Debug Port

2 Product Brief

ARM® CortexTM-M1

ARM Cortex-M1–Enabled FPGAsARM Cortex-M1 is available for use in a growing numberof Actel M1 devices. These include M1AFS600,M1AGL600, M1A3P1000, and a number of additional M1devices. The devices listed have the features shown in thefollowing sections:

M1AFS600 FusionActel Fusion™ Programmable System Chips (PSCs) are theworld’s first mixed-signal FPGAs. Fusion integrates a12-bit analog-to-digital converter, as many as 40 analogI/Os, up to 8 Mbits of flash memory, and FPGA fabric allin a single device. When used in conjunction with a softprocessor such as ARM Cortex-M1, Actel Fusion devicesrepresent the definitive soft MCU platform.

M1AFS600 Features• Industry’s first mixed-signal FPGA

• 600,000 system gates – 13,824 logic tiles

• ARM Cortex-M1 uses less than 30% of FPGA logic

• 4 Mbits flash, 108 kbits SRAM

• 30 analog inputs, 10 analog outputs

• 172 digital I/Os

• 2 PLLs, 1% RC oscillator, Xtal oscillator, RTC

M1AGL600 IGLOO FPGAsThe M1 IGLOO devices are reprogrammable, full-featured flash FPGAs designed to meet the demanding

power and area requirements of today's portableelectronics. Featuring Flash*Freeze™ technology andwith operating voltages of 1.2 V / 1.5 V, these devicesoffer the industry's lowest power consumption. M1IGLOO devices give designers a flexible systemconstruction platform for building portable productsthat offer maximum battery life.

M1AGL600 Features• Ultra-low power flash-based FPGA

• 600,000 system gates – 13,824 logic tiles

• ARM Cortex-M1 uses less than 33% of FPGA logic

• 144 kbits SRAM, 235 digital I/Os

M1A3P1000 ProASIC3/E FPGAsProASIC3/E devices, the third generation of Actel FlashFPGAs, offer industry-leading unit cost and lowest totalsystem cost—up to 504 kbits of SRAM, 350 MHzoperation, and best-in-class logic utilization. Thesesingle-chip FPGAs require no boot ROMs or othersupport chips and are highly secure, with 128-bit AESencryption and FlashLock® technology.

M1A3P1000 Features• Low-cost flash-based FPGA

• 1,000,000 system gates – 24,576 logic tiles

• ARM Cortex-M1 uses less than 20% of FPGA logic

• 144 kbits SRAM

• 300 digital I/Os

Table 1 • ARM Cortex-M1 Utilization Data

Device Variant

Performance (MHz) Size (tiles)

Size (tiles) RVDS

Size (tiles) FlashPro RAM Blocks Device

Utilization (%)

M1 Fusion

No debug 67.5 4,452 – – 4 M1AFS600 31

With debug 66.9 – 9,272 9,462 4 M1AFS600 68

M1 IGLOO 1.5 V

No debug 39 4,435 – – 4 M1AGL600 31

With debug 39 – 9,250 9,440 4 M1AGL600 68

M1 IGLOO 1.2 V

No debug 24 4,435 – – 4 M1AGL600 31

With debug 24 – 9,250 9,440 4 M1AGL600 68

M1 ProASIC3/E

No debug 69.9 4,435 – – 4 M1A3PE1500 12

With debug 66.5 – 9,250 9,440 4 M1A3PE1500 25

Note: Configuration is 0 kbytes ITCM, 0 kbytes DTCM, small multiplier, 1interrupt, no OS extensions, little-endian, and debug as shown.

Product Brief 3

ARM® CortexTM-M1

ARM Cortex-M1 SignalsThe signals of the core are given in Table 2.

Table 2 • ARM Cortex-M1 Signal Descriptions

Name Width Type Description

HCLK 1 Input Main processor clock

NSYSRESET 1 Input External push-button/power-up reset

WDOGRES 1 Input Watchdog reset to ARM Cortex-M1

WDOGRESn 1 Output Reset of watchdog timer

HRESETn 1 Output Reset to other components in AHB system

RV_TCK 1 Input RealView JTAG

RV_nTRST 1 Input RealView JTAG

RV_TMS 1 Input RealView JTAG

RV_TDI 1 Input RealView JTAG

RV_nSRST_IN 1 Input RealView JTAG

RV_TRCK 1 Input RealView JTAG

RV_TDOUT 1 Output RealView JTAG

RV_nTDOEN 1 Output RealView JTAG

UJTAG_TCK 1 Input FlashPro3 JTAG

UJTAG_TDI 1 Input FlashPro3 JTAG

UJTAG_TMS 1 Input FlashPro3 JTAG

UJTAG_TRSTB 1 Input FlashPro3 JTAG

UJTAG_TDO 1 Output FlashPro3 JTAG

IRQ[31:0] 32 Input External Interrupts

NMI 1 Input Non-maskable Interrupt

EDBGRQ 1 Input External debug request

nTRST 1 Input JTAG reset

JTAGTOP 1 Output State Controller Indicator

nTDOEN 1 Output JTAG data out enable

LOCKUP 1 Output Core is locked up

HALTED 1 Output Core is in Halt Debug state

HREADY 1 Input Slave ready signal

HRESP 1 Input AHB response signal

HRDATA[31:0] 32 Input Data from Slave to Master

HTRANS[1:0] 2 Output AHB transfer type signal

HBURST[2:0] 3 Output AHB burst signal

HPROT[3:0] 4 Output Transfer protection bits

HSIZE[2:0] 3 Output Transfer size

HWRITE 1 Output Transfer direction

HMASTLOCK 1 Output Transfer is part of a locked sequence

HADDR[31:0] 32 Output Transfer address

HWDATA[31:0] 32 Output Data from Master to Slave

4 Product Brief

ARM® CortexTM-M1

Programmer’s ModelThe ARM Cortex-M1 processor supports all ARMv6-MThumb instructions. This includes the entire 16-bitThumb instruction set architecture and some 32-bitinstructions. or information on ARMv6-M Thumbinstructions, see the ARMv6-M Architecture ReferenceManual. The processor does not support ARMinstructions.

Processor Operating StatesThe ARM Cortex-M1 processor has two operating states:

• Thumb state – This is the normal execution state,with the processor running the 16-bit and 32-bithalfword-aligned Thumb and Thumb-2 BL, MRS,MSR, ISB, DSB, and DMB instructions.

• Debug state – This is the state the processor is infor debugging.

Processor Operating ModesThe ARM Cortex-M1 processor supports two modes ofoperation:

• Thread mode – Entered on Reset, and can be re-entered as a result of an exception return.

• Handler mode – Entered as a result of anexception.

Main Stack and Process Stack AccessOut of reset, all code uses the main stack. An exceptionhandler such as SVC can change the stack used by Threadmode from main stack to process stack by changing theEXC_RETURN value it uses on exit. All exceptionscontinue to use the main stack. The stack pointer, R13, isa banked register that switches between the main stackand the process stack. Only one stack, either the processstack or the main stack, is visible, using R13, at any time.

It is also possible to switch from the main stack to processstack while in Thread mode by writing to the specialpurpose Control Register using an MSR instruction.

RegistersThe processor has the following 32-bit registers(Figure 2):

• 13 general purpose registers, R0–R12

• Stack Pointer (SP) (SP, R13) and banked registeraliases, SP_process and SP_main

• Link Register (LR, R14)

• Program Counter (PC, R15)

• Program status registers (xPSR)

General Purpose RegistersThe general purpose registers, R0–R12, have no specialarchitecturally-defined uses.

• Low registers – Registers R0–R7 are accessible byall instructions that specify a general purposeregister.

• High registers – Registers R8-R12 are notaccessible by all 16-bit instructions.

The R13, R14, and R15 registers have the followingspecial functions:

• Stack Pointer – Register R13 is used as the StackPointer (SP). Because the SP ignores writes to bits[1:0], it is auto-aligned to a word, four-byte, andboundary. Handler mode always uses SP_main, butyou can configure Thread mode to use eitherSP_main or SP_process.

• Link Register – Register R14 is the subroutineLink Register (LR). The LR receives the returnaddress from PC when a Branch and Link (BL)instruction is executed. The LR is also used for anexception return. At all other times, you can treatR14 as a general purpose register.

• Program Counter – Register R15 is the ProgramCounter (PC). Bit 0 is always 0, so instructions arealways aligned to halfword boundaries.

Special Purpose Program Status Registers (xPSR)Processor status at the system level breaks down intothree categories and can be accessed as individualregisters, a combination of any two from three, or acombination of all three, using the MRS and MSRinstructions.

• Application PSR (APSR) – Contains the conditioncode flags. Before entering an exception, theprocessor saves the condition code flags on thestack. You can access the APSR with the MSR andMRS instructions.

• Interrupt PSR (IPSR) – Contains the InterruptService Routine (ISR) number of the currentexception activation.

Figure 2 • Processor Register Set

r1r2r3r4r5

r0

High Registers

Low Registers

r9r10r11r12

ProgramStatus Register

r8r7r6

r13 (SP)r14 (LR)r15 (PC)

xPSR

SP_mainSP_process

Product Brief 5

ARM® CortexTM-M1

• Execution PSR (EPSR) – Contains the Thumb statebit (T-bit). Unless the processor is in Debug state,the EPSR is not directly accessible. All fields read aszero using an MRS instruction and MSR instructionwrites are ignored.

On entering an exception, the processor saves thecombined information from the three status registers onthe stack.

Special Purpose Priority Mask RegisterUse the special purpose Priority Mask Register forpriority boosting. You can access the special purposePriority Mask Register using the MSR and MRSinstructions. You can also use the CPS instruction to set orclear PRIMASK.

Special Purpose Control RegisterThe special purpose Control Register identifies the stackpointers used.

Data TypesThe processor supports the following data types:

• 32-bit words

• 16-bit halfwords

• 8-bit bytes

Note: Unless otherwise stated, the core can access allregions of the memory map, including the code region,with all data types. To support this, the system mustsupport sub-word writes without corrupting neighboringbytes in that word.

Memory FormatsThe processor views memory as a linear collection ofbytes numbered in ascending order from 0 (Figure 3).

Figure 3 • Processor Memory Map

0xE00FFFFF

0xF00FF000

0xE000ED00

0xE000E000

0xE0003000

0xE0002000

0xE0001000

0xE0000000

0xE000F000

0xE003FFFF0xE0040000

0xE0041000

0xE0042000

ROM Table

Reserved

Reserved

BP

DW

Reserved

NVIC

Debug Control

Reserved

Reserved

Reserved

0x3FFFFFFF

0x20100000511 MB

1 MB

511 MB

1 MB

External

DTCM

External

ITCM0x00100000

0x1FFFFFFF

0x20000000

0x00000000

Reserved

Internal Private Peripheral Bus

1 GB

1 GB

0.5 GB

0.5 GB

Code

SRAM

Peripheral

External

External Device

0.5 GB

0xFFFFFFFF

0xE0100000

0x5FFFFFFF

0x400000000x3FFFFFFF

0x200000000x1FFFFFFF

0x00000000

0x60000000

0x9FFFFFFF0xA0000000

0xDFFFFFFF0x00000000

6 Product Brief

ARM® CortexTM-M1

For example:

• Bytes 0–3 hold the first stored word

• Bytes 4–7 hold the second stored word

The processor accesses data and code words in little-endian format. Little-endian is the default memoryformat for ARM processors.

In little-endian format, the byte with the lowest addressin a word is the least significant byte of the word. Thebyte with the highest address in a word is the mostsignificant. The byte at address 0 of the memory systemconnects to data lines 7–0.

ExceptionsThe processor and the Nested Vectored InterruptController (NVIC) prioritize and handle all exceptions. Allexceptions are handled in Handler mode. Processor stateis automatically stored to the stack on an exception, andautomatically restored from the stack at the end of theexception handler Interrupt Service Routine (ISR). Thefollowing features enable efficient, low-latencyexception handling:

• Automatic state saving and restoring. Theprocessor pushes state registers on the stackbefore entering the ISR, and pops them afterexiting the ISR with no instruction overhead.

• Automatic reading of the vector table entry thatcontains the ISR address in code memory or dataSRAM

• Closely-coupled interface between the processorand the NVIC to enable early processing ofinterrupts and processing of late-arrivinginterrupts with higher priority

• Fixed number of interrupt priorities, from 2 bits, 4levels

• Separate stacks for Handler and Thread modes ifOS extensions are implemented

• ISR control transfer using the calling conventionsof the C/C++ standard Procedure Call Standard forthe ARM Architecture (PCSAA)

• Priority masking to support critical regions

Exception TypesVarious types of exceptions exist in the processor. A faultis an exception that results from an error condition.Faults can be reported synchronously or asynchronouslyto the instruction that caused them. In general, faults arereported synchronously. Faults caused by writes over thebus are asynchronous faults. A synchronous fault isalways reported with the instruction that caused thefault. An asynchronous fault does not guarantee how itis reported with respect to the instruction that causedthe fault. See Table 3 for a list and description of theexceptions supported by ARM Cortex-M1.

Table 3 • Exception Types

PositionException

Type Priority Description Activated

– – – Stack top is loaded from first entry of vector table on Reset. –

1 Reset –3 (highest) Invoked on power-up and warm Reset. On first instruction,drops to lowest priority. Thread mode.

Asynchronous

2 Non-maskable –2 Cannot be marked, prevented by activation, by any otherexception. Cannot be preempted by any other exceptionother than Reset.

Asynchronous

3 Hard fault –1 All classes of fault Synchronous or asynchronous

4–10 – – Reserved –

11 SVCall Configurable System service call with SVC instruction Synchronous

12–13 – – Reserved –

14 PendSV Configurable Pendable request for system service. This is only pended bysoftware.

Asynchronous

15 SysTick Configurable System tick timer has fired. Asynchronous

16–48 External interrupt

Configurable Asserted from outside the processor, IRQ[2n-1:0], and fedthrough the NVIC (prioritized).

Asynchronous

Product Brief 7

ARM® CortexTM-M1

Exception PriorityIn the processor exception model, priority determineswhen and how the processor takes exceptions. You canassign software priority levels to interrupts.

The NVIC supports software-assigned priority levels. Youcan assign a priority level from 0 to 3 to an interrupt bywriting to the 2-bit IP_N field in an Interrupt PriorityRegister. Hardware priority decreases with increasinginterrupt number. Priority level –3 is the highest prioritylevel, and priority level 3 is the lowest. The priority leveloverrides the hardware priority.

StacksThe processor supports two separate stacks:

• Process stack – You can configure Thread modeto use the process stack. Thread mode uses themain stack out of reset. SP_process is the StackPointer (SP) register for the process stack.

• Main stack – Handler mode uses the main stack.SP_main is the SP register for the main stack.

Only one stack, the process stack or the main stack, isvisible at any time, using R13. After pushing the content,the ISR uses the main stack, and all subsequent interruptpreemptions use the main stack.

Clocking and ResetsThe processor has one functional clock input, HCLK, andone reset signal, SYSRESETn. If debug is implemented,there is also a SWJ-DP clock, SWCLKTCK, and nTRST.SWCLKTCK relates to the DAP logic. The debug resetsignal DBGRESETn relates to the debug logic clocked byHCLK.

The SYSRESETn signal resets the entire processor systemwith the exception of debug logic in the following:

• Nested Vectored Interrupt Controller (NVIC)

• Debug subsystem

The register file cannot be reset by SYSRESETn orDBGRESETn.

Nested Vectored Interrupt ControllerThe NVIC facilitates low-latency exception and interrupthandling, and implements System Control Registers. TheNVIC supports reprioritizable interrupts. The NVIC andthe processor core interface are closely coupled, whichenables low latency interrupt processing and efficientprocessing of late-arriving interrupts. All NVIC registersare only accessible using word transfers. Any attempt towrite a halfword or byte individually causes corruptionof the register bits. All NVIC registers and system debugregisters are little-endian, regardless of the endiannessstate of the processor. See Table 4 for a list of the NVICregisters and their addresses.

Table 4 • NVIC Register

Name of Register Type Address Reset Value

IRQ 0 to 31 Set Enable Register R/W 0xE000E100 0x00000000

IRQ 0 to 31 Clear Enable Register R/W 0xE000E180 0x00000000

IRQ 0 to 31 Set Pending Register R/W 0xE000E200 0x00000000

IRQ 0 to 31 Clear Pending Register R/W 0xE000E280 0x00000000

Priority 0 Register R/W 0xE000E400 0x00000000

Priority 1 Register R/W 0xe000e404 0x00000000

Priority 2 Register R/W 0xe000e408 0x00000000

Priority 3 Register R/W 0xe000e40c 0x00000000

Priority 4 Register R/W 0xe000e410 0x00000000

Priority 5 Register R/W 0xe000e414 0x00000000

Priority 6 Register R/W 0xe000e418 0x00000000

Priority 7 Register R/W 0xe000e41c 0x00000000

8 Product Brief

ARM® CortexTM-M1

The processor supports both level and pulse interrupts. Alevel interrupt is held asserted until it is cleared by theISR accessing the device. A pulse interrupt is a variant ofan edge model. The edge must be sampled on the risingedge of the processor clock, HCLK, instead of beingasynchronous.

For level interrupts, if the signal is not deasserted beforethe return from the interrupt routine, the interruptrepends and reactivates. This is particularly useful forFIFO and buffer-based devices because it ensures thatthey drain either by a single ISR or by repeatedinvocations, with no extra work. This means that thedevice holds the signal in assert until the device is empty.

A pulse interrupt can be reasserted during the ISR so thatthe interrupt can be pended and active at the same time.The application design must ensure that a second pulsedoes not arrive before the first pulse is activated. If itdoes the second pend has no affect because it is alreadypended. However, if the interrupt is asserted for at leastone cycle, the NVIC latches the pend bit. When the ISRactivates, the pend bit is cleared. If the interrupt assertsagain while it is activated, it can latch the pend bit again.

Processor Bus InterfacesAs currently available for use in M1 devices, the ARMCortex-M1 has an AHB-Lite external interface. Theprocessor also contains an internal bus called the PrivatePeripheral Bus (PPB) for accesses to the Nested VectoredInterrupt Controller (NVIC), Data Watchpoint (DW) unit,and BreakPoint (BPU), but this is not directly accessible tothe user.

External InterfaceThe external interface is an AHB-Lite bus interface. Theprocessor accesses to AHB peripherals and memory areimplemented over this bus.

To prevent bus wait cycles from stalling the processorduring data stores, buffered stores to the externalinterface go through a one-entry write buffer. If thewrite buffer is full, subsequent accesses to the bus stalluntil the write buffer has drained. The write buffer isonly used if the bus waits for the data phase of thebuffered store; otherwise, the transaction completes onthe bus.

Memory InterfacesThe tightly coupled memory interface defined in theARM Cortex-M1 architecture is not currently supportedon M1 devices. Future core releases will have support forthis memory interface.

Private Peripheral BusThe AHB PPB is used to access the Nested VectorInterrupt Controller and the debug components whenthey are present. The PPB allows communication to flowbetween the AHB and NVIC units and the debug circuitrywhen it is implemented in the core.

Delivery and DeploymentARM Cortex-M1 is delivered as a series of files byCoreConsole that are directly imported into the Designand Simulation folders by Libero IDE. These consist of theBFM files and test wrapper, and the A1S secured CDB file,which is the placed-and-routed ARM Cortex-M1 core,actually instantiated on the user device. This deploymentflow is adopted to ensure that the design is keptcompletely secure at all times.

Initially, the ARM Cortex-M1 processor is being madeavailable for use in Actel M1 devices with only one userselectable option: with or without debug. The core isconfigured with 0K ITCM, 0K DTCM, small multiplier,little-endian, no OS extensions, and 1 interrupt. In thefuture, versions of the core will be offered with all of theconfigurable options available for configuration by theuser.

Product Brief 9

ARM® CortexTM-M1

Bus Functional Model (BFM)

IntroductionDuring the development of an FPGA-based SoC, thereare various stages of testing that can be undertaken. Thiscan involve some, or all, of the following approaches:

• Hardware simulation using Verilog or VHDL

• Software simulation using a host-based instructionset simulator (ISS) of the SoC’s processor

• Hardware and software co-verification using afull-functional model of the processor in Verilog,VHDL or SWIFT form, or using a tool such asSeamless

BFM Usage FlowThe BFM acts as a pin-for-pin replacement of theCortex-M1 in the simulation of the SoC subsystem. Itinitiates bus transactions on the native ARM Cortex-M1bus, which are cycle-accurate with real bus cycles thatARM Cortex-M1 would produce. It does not have theability, however, to implement real ARM Cortex-M1instructions. The BFM may be used to run a basic testsuite of the SoC subsystem, using the skeleton systemtestbench.

You can edit the SoC Verilog/VHDL to add new designblocks. You can also fill out the system-level testbench toinclude tasks that test any newly added functionality, oradd stubs to allow more complex system testinginvolving the IP cores. The BFM input scripts can also bemanually enhanced to test out access to registerlocations in newly added logic. In this way, you canprovide stimuli to the system from the inside (via theARM Cortex-M1 BFM), as well as from the outside (viatestbench tasks).

Timing ShellThere is a timing shell provided for each ARM Cortex-M1variant wrapped around the BFM. Therefore, the BFM isbus cycle accurate, and performs setup/hold checks tomodel output propagation delays.

DebugThe ARM Debug Architecture uses a protocol converterbox to allow the debugger to talk directly to the core viaa JTAG port. In effect, the scan chains in the core that arerequired for test are re-used for debugging. The coreuses the scan chains to insert instructions directly intoARM Cortex-M1. The instructions are executed on thecore and depending on the type of instruction that hasbeen inserted, the core or the system state can beexamined, saved, or changed. The architecture has theability to execute instructions at a slow debug speed orto execute instructions at system speed.

In debug mode, the user can perform the followingfunctions:

• Core halt

• Core stepping

• Core register access

• Read/Write to TCMs

• Read/Write to AHB address space

• Breakpoint

• Watchpoints

The main debug components are the following:

• Debug control registers – to access and controldebugging of the core

• Breakpoint Unit (BPU) – to implement breakpoints

• Data Watchpoint Unit (DW) – to implementwatchpoints and trigger resources

• Debug memory interfaces – to access externalITCM and DTCM

• ROM table

10 Product Brief

ARM® CortexTM-M1

Datasheet CategoriesIn order to provide the latest information to designers, some datasheets are published before data has been fullycharacterized. Datasheets are designated as "Product Brief," "Advanced," and "Production." The definitions of thesecategories are as follows:

Product BriefThe product brief is a summarized version of an advanced or production datasheet containing general productinformation. This brief summarizes specific device and family information for unreleased products.

AdvancedThis datasheet version contains initial estimated information based on simulation, other products, devices, or speedgrades. This information can be used as estimates, but not for production.

Unmarked (production)This datasheet version contains information that is considered to be final.

Product Brief 11

51700087PB-3/1.08

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