corg

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BITS Pilani, Pilani Campus

Components of a Computer

Input (mouse, keyboard, …)

Output (display, printer, …)

Memory

–main (DRAM), cache (SRAM)

– secondary (disk,

CD, DVD, …)

Datapath

Control

Input

Processor

Control

Datapath

Output

Memory10010100101100000010100101010001

1111011101100110

1001010010110000

1001010010110000

1001010010110000

Processor

(CPU)

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Von Neumann architecture

Single bank of memory which processor accesses through

a single set of address and data lines.

Processor core

Address bus

Memory

Data bus

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Harvard Architecture

Processor connected to two independent memory banks

via two independent set of buses.

Program bank and Data bank

Program bank will hold program instructions and data

bank with data.

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A CISC Architecture

Larger instructions with variable formats

(16-64 bits/ instruction)

Larger Addressing Modes (12- 24)

Few Registers

Most Microcoded with control Memory

Close to high level language

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Reduced Instruction Set Computer

LOAD- STORE Architecture

Fewer Addressing Modes

Fixed Length Instructions

More Registers

Designed for Pipeline Efficiency

Hardwired Control Unit

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Instruction Cycle

Two steps:

– Fetch

– Execute

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Steps in Execution of an Instruction

CPU fetches instruction from Main Memory

CPU Decodes the Instruction Op-code

Depending on Op-code

- Fetches operand

- Execute instruction via register to register transfer

- Write the results in M- Write the results in I/O

Repeat steps

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Instruction and Address Formats:

Opcode + Operands

First Generation Computers

Opcode A0 A1 A2 A3

- Because of sequential nature A3 not required

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Two address Format

OPCODE A0 A1

ADD AX, BX (8086)

One Address Format

OPCODE A0

ADD B

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Zero address Machines:

(Stack Machines)

ADD

Ex:

X = A*B + C*D

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REG SET

ALU

CLU

CENTRAL PROCESSING UNIT

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Clock Generator Bus Controller

Processor Controller

Execution Unit

A SINGLE CHIP MICROPROCESSOR

Control Part

Data Part

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EXECUTION UNIT

Programmers Register set

Additional registers ( IR, PC , Temp Reg)

ALU and any special function units

Internal Data paths

All connected through a interconnect network

usually comprised of one/more buses

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ARITHMETIC LOGIC UNIT

F1 F2

MUX

A B

SEL LINES

CONTROL

LINES

R

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CONTROL LOGIC UNIT

-Directs all hardware activity inside

-Controls Fetch, Decode, Execute Cycle

Macro/Micro Instructions

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A TYPICAL INSTRUCTION

- ADD R1, D2(B2)

(R1, B2 - Registers ), D2- displacement

(R1) + (Memory) (R1) ; (B2) + D2 Memory

5A R1 B2 D20 15 16 31

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CPU Operations

Fetch a word from Memory

Store a word into memory

Reg Transfers

Performing an ALU function

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Instruction Decoder

IR

PC

MAR

MDR

R0

Rn-1

Y

ALU

Z

Address Bus

Data Bus

C P U B

u s

A BControl Lines

Clear Y

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Register Transfer:

R2R1

To enable data transfer between various blocks connected

to common bus provide input output gating.

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Example Microinstructions:

Open/.Close a gate from Reg to a bus

Transfer data along a bus

Send timing signals

Test bits within a register

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R1

R1in

R1out

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R

Rin

Rout

Control Signals for

R1 R2

R 2OUT , R 1in

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Fetching a word from memory:

i. MAR (R1)

ii. Read Signal

iii. Wait for Memory-function-complete

(MFC) signaliv. R2(MDR)

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Storing a word into Memory:

i. MAR (R1)

ii. MDR (R2)

iii. Memory write signal

iv. Wait for MFC

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Performing an Arithmetic or Logic Operation:

i. R1out, Yin

ii. R2out, Add, Zin

iii. Zout, R3in

R

Rin

Rout

ALU

Y

Z

Zin

Yin

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Ex: Add contents of a memory

location to register R1

(Address of Memory location is in part of

the instruction )

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Step RTL Control Sequence

T1 MARPC; PCPC+1 PCout, MARin, Clear Y, Set

Carryin of ALU, ADD, Zin,

READ



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READ

T2 Wait Zout, PCin, Wait for MFC

T3 IRMDR MDRout, IRin



- Instruction Fetch

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T4 MARIR Addr-field of IRout, MARin,

READ

T5 YR1 R1out, Yin, Wait for MFC

T6 Z Y + M[MAR] MDRout, ADD, Zin

T7 R1Z Zout, R1in, END



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READ



Ex: Branch by an offset x

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T4 YPC PCout, Yin

T5 Z Y + [x of IR] ADD, Zin Addr-field of IRout

T6 PC

Z Zout, PCin, END

Ex: Branch by an offset x

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Ex: CALL absolute address

-Address fetched along with

instruction

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T1 MARPC; PCPC+1 PCout, MARin, Clear Y,

Set Carryin of ALU, ADD,

Zin, READ




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T1 MARPC; PCPC+1 PCout, MARin, Clear Y,

Set Carryin of ALU, ADD,

Zin, READ



T4 ZSP-1 Set Y, SPout, ADD, Zin


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T1 MARPC; PC

PC+1

PCout, MARin, Clear Y,

Set Carryin of ALU,

ADD, Zin, READ

T2 Wait Zout

, PCin

, Wait for MFC


T4 ZSP-1 Set Y, SPout, ADD, Zin

T5 SPZ, MAR Z Zout, ,MARin,,SPin

T6 MDRPC MDRin, PCout, WRITE

T7 PCIR PCin, Addr-field of Ir out,

Wait for MFC, END


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Load Register from Memory

with Absolute address

( LDA 1000)

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READ



T4 MAR IR Add field of IRout, READ

T5 Wait Wait for MFC

T6 R2 MDR MDRout, R2in

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ADD RX, RY

rxaalu

rybalu

t1

b

ry

state

sequence Time

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Design of CLU

- Hard wired design

- Microprogrammed design

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HARDWIRED CONTROL UNIT

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Hard-wired Control Unit

The opcode field of IR. This field is decoded toprovide the encoder information about

instruction being decoded

-Signals from status and condition

-Control step information

( Step generator for T1, T2, ….)

-External signals such as start, MFC,

interrupts etc.

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Control signal generator generates Individual

control signals.

Ex:

Zin = T1 + T6.ADD + T5. BR + ….

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Control signal generator generates Individual

control signals.

Ex:

Zin = T1 + T6.ADD + T5. BR + ….

PCin = T2 +T6 .BR + T7.CALL +…..

- IMPLEMENTED AS A COMBINATIONAL CIRCUIT.

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Combinational design could be using PLDs.

Hard wired logic difficult to implement changes

Provides faster execution.

Another approach

Microprogrammed control unit

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Microprogrammed Unit

-Sequence of microinstructions corresponding

to each instruction is stored in ROM called

Control Memory

-Called Microprogram

-Provides flexibility of implementation

-Less hardware

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Micro instruction word is the word whose

bits represent control signals

Ex:

Y R1 ;

R1out, Yin, Wait for MFC

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Micro instruction word is the word whosebits represent control signals

Z Y + MDR ;

MDRout, ADD, Zin

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Micro instruction word is the word whosebits represent control signals

R1 Z ;

Zout, R1in, END

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Step :R1in R1out Yin Zin Zout MDRout ADD WMFC END

5 0 1 1 0 0 0 0 1 0

6 0 0 0 1 0 1 1 0 0

7 1 0 0 0 1 0 0 0 1

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Microprogramming Types

Horizontal Microprogramming

Vertical Microprogramming

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Horizontal Approach

-1 bit per control signal

-Many control signals generated concurrently

-Permitting very fast operation

-Requires large control memory area

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Vertical Approach

- Most Micro instructions are mutually exclusiveand never invoked simultaneously

- Possible to divide into groups and use few bits

to represent each group

- A Decoder then used to select a particular

Microoperation to be invoked

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. . . . . . . . .

Decoder

Micro instruction

Control Lines

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-Resembles Macro instruction

-Easier to write

-Control Memory size reduced

-Additional hardware required

-Slow down the process

Combinational approach can be used

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Control Unit

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Nanomemory

-Third memory unit beside main memory and

control memory

-Appropriate when many microinstructionsoccur several time

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Example:

Microprogram with k t-bit micro instructions

To store this k x t size control memory required

Assume only n distinct microinstructions are

used where n k

Store these instr ctions in n ord t bit nanomemor

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Store these instructions in n-word, t-bit nanomemory

Original program replaced by address of nanomemory word

Reduction in memory size

Store these instructions in n word t bit nanomemory

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Store these instructions in n-word, t-bit nanomemory

Original program replaced by address of nanomemory word

Reduction in memory size

For ex:

16, 384 x 128 is the original size

But has only 256 different microinstructions

Nanomemory size is 256 x 128

Control ROM size is 16,384 x 8

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Size saved = (16,384 x 128)-(16,384x8) – (256 x 128)

= 1,933,312

Speed reduced because two levels of memory

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MPXControlStore

Address

MUX

select

TY NA

Instruction

Decoders

Trace

address

Trace

bit

To controlstore

Documents

corg