Core Interview Quesns

8/10/2019 Core Interview Quesns

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Here is a nice collection of Interview questions with reponses:

CMOS interview questions.

1/ What is latch up?

Latchup pertains to a failure !echanis! wherein a parasitic th"ristor #such as a parasitic silicon

controlle$ rectifier% or SC&' is ina$vertentl" create$ within a circuit% causin( a hi(h a!ount of current to

continuousl" flow throu(h it once it is acci$entall" tri((ere$ or turne$ on. )epen$in( on the circuits

involve$% the a!ount of current flow pro$uce$ *" this !echanis! can *e lar(e enou(h to result in

per!anent $estruction of the $evice $ue to electrical overstress #+OS'

,'Wh" is --) (ate preferre$ over -O& (ate for fa*rication?

--) is a *etter (ate for $esi(n than -O& *ecause at the transistor level the !o*ilit" of electrons is

nor!all" three ti!es that of holes co!pare$ to -O& an$ thus the --) is a faster (ate.

$$itionall"% the (ateleaa(e in --) structures is !uch lower. If "ou consi$er t0phl an$ t0plh $ela"s

"ou will fin$ that it is !ore s"!!etric in case of --) # the $ela" profile'% *ut for -O&% one $ela" is

!uch hi(her than the other#o*viousl" t0plh is hi(her since the hi(her resistance p !oss are in seriesconnection which a(ain increases the resistance'.

2'What is -oise Mar(in? +3plain the proce$ure to $eter!ine -oise Mar(in

4he !ini!u! a!ount of noise that can *e allowe$ on the input sta(e for which the output will not *e

effecte$.

5'+3plain si6in( of the inverter?

In or$er to $rive the $esire$ loa$ capacitance we have to increase the si6e #wi$th' of the inverters to (et

an opti!i6e$ perfor!ance.

7' How $o "ou si6e -MOS an$ 8MOS transistors to increase the threshol$ volta(e?


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9' What is -oise Mar(in? +3plain the proce$ure to $eter!ine -oise Mar(in?

4he !ini!u! a!ount of noise that can *e allowe$ on the input sta(e for which the output will not *e

effecte$.

' What happens to $ela" if "ou increase loa$ capacitance?

$ela" increases.

;'What happens to $ela" if we inclu$e a resistance at the output of a CMOS circuit?

Increases. #&C $ela"'

CA,f %fro! this !ini!i6e the loa$ capacitance% $c volta(e an$ the operatin(

frequenc".

1,' What is Char(e Sharin(? +3plain the Char(e Sharin( pro*le! while sa!plin( $ata fro! a Bus?

In the seriall" connecte$ -MOS lo(ic the input capacitance of each (ate shares the char(e with the loa$

capacitance *" which the lo(ical levels $rasticall" !is!atche$ than that of the $esire$ once. 4o


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eli!inate this loa$ capacitance !ust *e ver" hi(h co!pare$ to the input capacitance of the (ates

#appro3i!atel" 1= ti!es'.

12'Wh" $o we (ra$uall" increase the si6e of inverters in *uffer $esi(n? Wh" not (ive the output of a

circuit to one lar(e inverter?

Because it can not $rive the output loa$ strai(ht awa"% so we (ra$uall" increase the si6e to (et an

opti!i6e$ perfor!ance.

15'What is Latch p? +3plain Latch p with cross section of a CMOS Inverter. How $o "ou avoi$ Latch

p?

Latchup is a con$ition in which the parasitic co!ponents (ive rise to the +sta*lish!ent of low

resistance con$uctin( path *etween A)) an$ ASS with )isastrous results.

17' Dive the e3pression for CMOS switchin( power $issipation?

CA,

19' What is Bo$" +ffect?

In (eneral !ultiple MOS $evices are !a$e on a co!!on su*strate. s a result% the su*strate volta(e of

all $evices is nor!all" equal. However while connectin( the $evices seriall" this !a" result in an

increase in sourcetosu*strate volta(e as we procee$ verticall" alon( the series chain #As*1>=% As*,='.Which results Ath,EAth1.

1' Wh" is the su*strate in -MOS connecte$ to Droun$ an$ in 8MOS to A))?


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we tr" to reverse *ias not the channel an$ the su*strate *ut we tr" to !aintain the $rain%source

Functions reverse *iase$ with respect to the su*strate so that we $ont loose our current into the

su*strate.

1;' What is the fun$a!ental $ifference *etween a MOS@+4 an$ BG4 ?

In MOS@+4% current flow is either $ue to electrons#nchannel MOS' or $ue to holes#pchannel MOS' In

BG4% we see current $ue to *oth the carriers.. electrons an$ holes. BG4 is a current controlle$ $evice an$

MOS@+4 is a volta(e controlle$ $evice.

1


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output to (roun$ ann 8MOS helps in pullin( up the output to A$$. If the si6es of 8MOS an$ -MOS are

the sa!e% then 8MOS taes lon( ti!e to char(e up the output no$e. If we have a lar(er 8MOS than

there will *e !ore carriers to char(e the no$e quicl" an$ overco!e the slow nature of 8MOS . Basicall"

we $o all this to (et equal rise an$ fall ti!es for the output no$e.

,,'Wh" 8MOS an$ -MOS are si6e$ equall" in a 4rans!ission Dates?

In 4rans!ission Date% 8MOS an$ -MOS ai$ each other rather co!petin( with each other. 4hats the

reason wh" we nee$ not si6e the! lie in CMOS. In CMOS $esi(n we have -MOS an$ 8MOS co!petin(

which is the reason we tr" to si6e the! proportional to their !o*ilit".

,2'll of us now how an inverter wors. What happens when the 8MOS an$ -MOS are interchan(e$

with one another in an inverter?

I have seen si!ilar Js in so!e of the $iscussions. If the source K $rain also connecte$ properl"...it acts

as a *uffer. But suppose input is lo(ic 1 O/8 will *e $e(ra$e$ 1 Si!ilarl" $e(ra$e$ =

,5' (oo$ question on La"outs. Dive 7 i!portant )esi(n techniques "ou woul$ follow when $oin( a

La"out for )i(ital Circuits?

a'In $i(ital $esi(n% $eci$e the hei(ht of stan$ar$ cells "ou want to la"out.It $epen$s upon how *i( "our

transistors will *e.Have reasona*le wi$th for A)) an$ D-) !etal paths.Maintainin( unifor! Hei(ht for

all the cell is ver" i!portant since this will help "ou use place route tool easil" an$ also incase "ou want

to $o !anual connection of all the *locs it saves on lot of area.

*'se one !etal in one $irection onl"% 4his $oes not appl" for !etal 1. Sa" "ou are usin( !etal , to $o

hori6ontal connections% then use !etal 2 for vertical connections% !etal5 for hori6ontal% !etal 7 vertical

etc...

c'8lace as !an" su*strate contact as possi*le in the e!pt" spaces of the la"out.

$')o not use pol" over lon( $istances as it has hu(e resistances unless "ou have no other choice.

e'se fin(ere$ transistors as an$ when "ou feel necessar".

f'4r" !aintainin( s"!!etr" in "our $esi(n. 4r" to (et the $esi(n in BI4 Slice$ !anner.


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,7'What is !etasta*ilit"? When/wh" it will occur?)ifferent wa"s to avoi$ this?

Metasta*le state: unnown state in *etween the two lo(ical nown states.4his will happen if the O/8

cap is not allowe$ to char(e/$ischar(e full" to the require$ lo(ical levels.

One of the cases is: If there is a setup ti!e violation% !etasta*ilit" will occur%4o avoi$ this% a series of @@s

is use$ #nor!all" , or 2' which will re!ove the inter!e$iate states.

,9'Let an$ B *e two inputs of the --) (ate. Sa" si(nal arrives at the --) (ate later than si(nal B.

4o opti!i6e $ela" of the two series -MOS inputs an$ B which one woul$ "ou place near to the

output?

4he late co!in( si(nals are to *e place$ closer to the output no$e ie shoul$ (o to the n!os that is

closer to the output.

)i(ital $esi(n interview questions K answers.

1' +3plain a*out setup ti!e an$ hol$ ti!e% what will happen if there is setup ti!e an$ hol$ tine

violation% how to overco!e this?

Set up ti!e is the a!ount of ti!e *efore the cloc e$(e that the input si(nal nee$s to *e sta*le to

(uarantee it is accepte$ properl" on the cloc e$(e.

Hol$ ti!e is the a!ount of ti!e after the cloc e$(e that sa!e input si(nal has to *e hel$ *efore

chan(in( it to !ae sure it is sense$ properl" at the cloc e$(e.

Whenever there are setup an$ hol$ ti!e violations in an" flipflop% it enters a state where its output is

unpre$icta*le: this state is nown as !etasta*le state #quasi sta*le state' at the en$ of !etasta*le

state% the flipflop settles $own to either 1 or =. 4his whole process is nown as !etasta*ilit"


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,' What is sew% what are pro*le!s associate$ with it an$ how to !ini!i6e it?

In circuit $esi(n% cloc sew is a pheno!enon in s"nchronous circuits in which the cloc si(nal #sent fro!

the cloc circuit' arrives at $ifferent co!ponents at $ifferent ti!es.

4his is t"picall" $ue to two causes. 4he first is a !aterial flaw% which causes a si(nal to travel faster or

slower than e3pecte$. 4he secon$ is $istance: if the si(nal has to travel the entire len(th of a circuit% it

will liel" #$epen$in( on the circuits si6e' arrive at $ifferent parts of the circuit at $ifferent ti!es. Cloc

sew can cause har! in two wa"s. Suppose that a lo(ic path travels throu(h co!*inational lo(ic fro! a

source flipflop to a $estination flipflop. If the $estination flipflop receives the cloc tic later than the

source flipflop% an$ if the lo(ic path $ela" is short enou(h% then the $ata si(nal !i(ht arrive at the

$estination flipflop *efore the cloc tic% $estro"in( there the previous $ata that shoul$ have *eencloce$ throu(h. 4his is calle$ a hol$ violation *ecause the previous $ata is not hel$ lon( enou(h at the

$estination flipflop to *e properl" cloce$ throu(h. If the $estination flipflop receives the cloc tic

earlier than the source flipflop% then the $ata si(nal has that !uch less ti!e to reach the $estination

flipflop *efore the ne3t cloc tic. If it fails to $o so% a setup violation occurs% socalle$ *ecause the new

$ata was not set up an$ sta*le *efore the ne3t cloc tic arrive$. hol$ violation is !ore serious than a

setup violation *ecause it cannot *e fi3e$ *" increasin( the cloc perio$.

Cloc sew% if $one ri(ht% can also *enefit a circuit. It can *e intentionall" intro$uce$ to $ecrease the

cloc perio$ at which the circuit will operate correctl"% an$/or to increase the setup or hol$ safet"

!ar(ins. 4he opti!al set of cloc $ela"s is $eter!ine$ *" a linear pro(ra!% in which a setup an$ a hol$

constraint appears for each lo(ic path. In this linear pro(ra!% 6ero cloc sew is !erel" a feasi*le point.

Cloc sew can *e !ini!i6e$ *" proper routin( of cloc si(nal #cloc $istri*ution tree' or puttin(

varia*le $ela" *uffer so that all cloc inputs arrive at the sa!e ti!e

2' What is slac?

Slac is the a!ount of ti!e "ou have that is !easure$ fro! when an event actuall" happens an$

when it !ust happen.. 4he ter! actuall" happens can also *e taen as *ein( a pre$icte$ ti!e for

when the event will actuall" happen.


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When so!ethin( !ust happen can also *e calle$ a $ea$line so another $efinition of slac woul$ *e

the ti!e fro! when so!ethin( actuall" happens #call this 4act' until the $ea$line #call this 4$ea$'.

Slac > 4$ea$ 4act.

-e(ative slac i!plies that the actuall" happen ti!e is later than the $ea$line ti!e...in other wor$s

its too late an$ a ti!in( violation...."ou have a ti!in( pro*le! that nee$s so!e attention.

5' What is (litch? What causes it #e3plain with wavefor!'? How to overco!e it?

4he followin( fi(ure shows a s"nchronous alternative to the (ate$ cloc usin( a $ata path. 4he flipflop is

cloce$ at ever" cloc c"cle an$ the $ata path is controlle$ *" an ena*le. When the ena*le is Low% the

!ultiple3er fee$s the output of the re(ister *ac on itself. When the ena*le is Hi(h% new $ata is fe$ to

the flipflop an$ the re(ister chan(es its state

7' Diven onl" two 3or (ates one !ust function as *uffer an$ another as inverter?

4ie one of 3or (ates input to 1 it will act as inverter.

4ie one of 3or (ates input to = it will act as *uffer.

9' What is $ifference *etween latch an$ flipflop?

4he !ain $ifference *etween latch an$ @@ is that latches are level sensitive while @@ are e$(e sensitive.

4he" *oth require the use of cloc si(nal an$ are use$ in sequential lo(ic. @or a latch% the output tracs


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the input when the cloc si(nal is hi(h% so as lon( as the cloc is lo(ic 1% the output can chan(e if the

input also chan(es. @@ on the other han$% will store the input onl" when there is a risin(/fallin( e$(e of

the cloc.

' Buil$ a 5:1 !u3 usin( onl" ,:1 !u3?

)ifference *etween heap an$ stac?

4he Stac is !ore or less responsi*le for eepin( trac of whats e3ecutin( in our co$e #or whats *een

calle$'. 4he Heap is !ore or less responsi*le for eepin( trac of our o*Fects #our $ata% well... !ost of

it well (et to that later.'.

4hin of the Stac as a series of *o3es stace$ one on top of the ne3t. We eep trac of whats (oin( on

in our application *" stacin( another *o3 on top ever" ti!e we call a !etho$ #calle$ a @ra!e'. We can

onl" use whats in the top *o3 on the stac. When were $one with the top *o3 #the !etho$ is $one

e3ecutin(' we throw it awa" an$ procee$ to use the stuff in the previous *o3 on the top of the stac.4he Heap is si!ilar e3cept that its purpose is to hol$ infor!ation #not eep trac of e3ecution !ost of

the ti!e' so an"thin( in our Heap can *e accesse$ at an" ti!e. With the Heap% there are no constraints

as to what can *e accesse$ lie in the stac. 4he Heap is lie the heap of clean laun$r" on our *e$ that

we have not taen the ti!e to put awa" "et we can (ra* what we nee$ quicl". 4he Stac is lie the

stac of shoe *o3es in the closet where we have to tae off the top one to (et to the one un$erneath it.


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s"ste!s are usuall" *est reali6e$ as Moore !o$els' an$ personal preferences of a $esi(ner or

pro(ra!!er

B' Meal" !achine has outputs that $epen$ on the state an$ input #thus% the @SM has the output written

on e$(es'

Moore !achine has outputs that $epen$ on state onl" #thus% the @SM has the output written in the

state itself.

$v an$ )isa$v

In Meal" as the output varia*le is a function *oth input an$ state% chan(es of state of the state varia*les

will *e $ela"e$ with respect to chan(es of si(nal level in the input varia*les% there are possi*ilities of

(litches appearin( in the output varia*les. Moore overco!es (litches as output $epen$ent on onl"

states an$ not the input si(nal level.

ll of the concepts can *e applie$ to Moore!o$el state !achines *ecause an" Moore state !achine

can *e i!ple!ente$ as a Meal" state !achine% althou(h the converse is not true.

Moore !achine: the outputs are properties of states the!selves... which !eans that "ou (et the output

after the !achine reaches a particular state% or to (et so!e output "our !achine has to *e taen to a

state which provi$es "ou the output.4he outputs are hel$ until "ou (o to so!e other state Meal"

!achine:

Meal" !achines (ive "ou outputs instantl"% that is i!!e$iatel" upon receivin( input% *ut the output is

not hel$ after that cloc c"cle.

1=' )ifference *etween onehot an$ *inar" enco$in(?

Co!!on classifications use$ to $escri*e the state enco$in( of an @SM are Binar" #or hi(hl" enco$e$'

an$ One hot.

*inar"enco$e$ @SM $esi(n onl" requires as !an" flipflops as are nee$e$ to uniquel" enco$e thenu!*er of states in the state !achine. 4he actual nu!*er of flipflops require$ is equal to the ceilin( of

the lo(*ase, of the nu!*er of states in the @SM.

onehot @SM $esi(n requires a flipflop for each state in the $esi(n an$ onl" one flipflop #the flipflop

representin( the current or hot state' is set at a ti!e in a one hot @SM $esi(n. @or a state !achine

with


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@8D ven$ors frequentl" reco!!en$ usin( a onehot state enco$in( st"le *ecause flipflops are plentiful

in an @8D an$ the co!*inational lo(ic require$ to i!ple!ent a onehot @SM $esi(n is t"picall" s!aller

than !ost *inar" enco$in( st"les. Since @8D perfor!ance is t"picall" relate$ to the co!*inational lo(ic

si6e of the @8D $esi(n% onehot @SMs t"picall" run faster than a *inar" enco$e$ @SM with lar(er

co!*inational lo(ic *locs

11' What are $ifferent wa"s to s"nchroni6e *etween two cloc $o!ains?

1,' How to calculate !a3i!u! operatin( frequenc"?

12' How to fin$ out lon(est path?

Nou can fin$ answer to this in ti!in(.ppt of presentations section on this site

15' )raw the state $ia(ra! to output a 1 for one c"cle if the sequence =11= shows up #the lea$in(=s cannot *e use$ in !ore than one sequence'?

17'How to achieve 1;= $eree e3act phase shift?

-ever tell usin( inverter

a' $c!s an in*uilt resource in !ost of fp(a can *e confi(ure$ to (et 1;= $e(ree phase shift.

*' Buf($s that is $ifferential si(nalin( *uffers which are also in*uilt resource of !ost of @8D can *e

use$.

19' What is si(nificance of ras an$ cas in S)&M?

S)&M receives its a$$ress co!!an$ in two a$$ress wor$s.

It uses a !ultiple3 sche!e to save input pins. 4he first a$$ress wor$ is latche$ into the )&M chip with

the row a$$ress stro*e #&S'.

@ollowin( the &S co!!an$ is the colu!n a$$ress stro*e #CS' for latchin( the secon$ a$$ress wor$.

Shortl" after the &S an$ CS stro*es% the store$ $ata is vali$ for rea$in(.

1' 4ell so!e of applications of *uffer?

a'4he" are use$ to intro$uce s!all $ela"s

*'4he" are use$ to eli!inate cross tal cause$ $ue to inter electro$e capacitance $ue to close routin(.

c'4he" are use$ to support hi(h fanout%e(:*uf(

1;' I!ple!ent an -) (ate usin( !u3?


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4his is the *asic question that !an" interviewers as. for an$ (ate% (ive one input as select line%incase if

u r (ivin( * as select line% connect one input to lo(ic = an$ other input to a.

1 frequenc"#cl0B' / 5

,' perio$#en0B' > perio$#cl0' 1==

2' $ut"0c"cle#en0B' > ,7

ssu!e cl0B > 1==MH6 #1=ns'

@ro! #1'% cl0 > ,7MH6 #5=ns'

@ro! #,'% perio$#en0B' > 5=ns 5== > 5===ns% *ut we onl" output for

1===ns%$ue to #2'% so 2===ns of the ena*le we are $oin( no output wor. 4herefore% @I@O si6e >

2===ns/5=ns > 7 entries

,1' )esi(n a fourinput --) (ate usin( onl" twoinput --) (ates.

:Basicall"% "ou can tie the inputs of a --) (ate to(ether to (et an inverter% so...

,,')ifference *etween S"nchronous an$ s"nchronous reset.?

S"nchronous reset lo(ic will s"nthesi6e to s!aller flipflops% particularl" if the reset is (ate$ with the

lo(ic (eneratin( the $input. But in such a case% the co!*inational lo(ic (ate count (rows% so the overall

(ate count savin(s !a" not *e that si(nificant.


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4he cloc wors as a filter for s!all reset (litches however% if these (litches occur near the active cloc

e$(e% the @lipflop coul$ (o !etasta*le. In so!e $esi(ns% the reset !ust *e (enerate$ *" a set of

internal con$itions. s"nchronous reset is reco!!en$e$ for these t"pes of $esi(ns *ecause it will filter

the lo(ic equation (litches *etween cloc.

)isa$vanta(es of s"nchronous reset:

8ro*le! with s"nchronous resets is that the s"nthesis tool cannot easil" $istin(uish the reset si(nal fro!

an" other $ata si(nal.

S"nchronous resets !a" nee$ a pulse stretcher to (uarantee a reset pulse wi$th wi$e enou(h to ensure

reset is present $urin( an active e$(e of the cloc if "ou have a (ate$ cloc to save power% the cloc

!a" *e $isa*le$ coinci$ent with the assertion of reset. Onl" an as"nchronous reset will wor in this

situation% as the reset !i(ht *e re!ove$ prior to the resu!ption of the cloc.

)esi(ns that are pushin( the li!it for $ata path ti!in(% can not affor$ to have a$$e$ (ates an$

a$$itional net $ela"s in the $ata path $ue to lo(ic inserte$ to han$le s"nchronous resets.

s"nchronous reset :

4he *i((est pro*le! with as"nchronous resets is the reset release% also calle$ reset re!oval. sin( an

as"nchronous reset% the $esi(ner is (uarantee$ not to have the reset a$$e$ to the $ata path. nother

a$vanta(e favorin( as"nchronous resets is that the circuit can *e reset with or without a cloc present.

)isa$vanta(es of as"nchronous reset: ensure that the release of the reset can occur within one cloc

perio$. if the release of the reset occurre$ on or near a cloc e$(e such that the flipflops went

!etasta*le.

,2' Wh" are !ost interrupts active low?

4his answers wh" !ost si(nals are active low

If "ou consi$er the transistor level of a !o$ule% active low !eans the capacitor in the output ter!inal

(ets char(e$ or $ischar(e$ *ase$ on low to hi(h an$ hi(h to low transition respectivel". when it (oes

fro! hi(h to low it $epen$s on the pull $own resistor that pulls it $own an$ it is relativel" eas" for the

output capacitance to $ischar(e rather than char(in(. hence people prefer usin( active low si(nals.

,5'Dive two wa"s of convertin( a two input --) (ate to an inverter?


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#a' short the , inputs of the nan$ (ate an$ appl" the sin(le input to it.

#*' Connect the output to one of the input an$ the other to the input si(nal.

,7' What are set up ti!e K hol$ ti!e constraints? What $o the" si(nif"? Which one is critical for

esti!atin( !a3i!u! cloc frequenc" of a circuit?

set up ti!e: the a!ount of ti!e the $ata shoul$ *e sta*le *efore the application of the cloc si(nal%

where as the hol$ ti!e is the a!ount of ti!e the $ata shoul$ *e sta*le after the application of the

cloc. Setup ti!e si(nifies !a3i!u! $ela" constraints hol$ ti!e is for !ini!u! $ela" constraints.

Setup ti!e is critical for esta*lishin( the !a3i!u! cloc frequenc".

,9' )ifferences *etween )Latch an$ ) flipflop?

)latch is level sensitive where as flipflop is e$(e sensitive. @lipflops are !a$e up of latches.

,' What is a !ultiple3er?

Is co!*inational circuit that selects *inar" infor!ation fro! one of !an" input lines an$ $irects it to a

sin(le output line. #,n >En'.

,;'How can "ou convert an S& @lipflop to a GP @lipflop?

B" (ivin( the fee$ *ac we can convert% i.e QJ>ES an$ J>E&.Hence the S an$ & inputs will act as G an$ P

respectivel".


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,


16/45

22' Convert )@@ into $ivi$e *" ,. #not latch' What is the !a3 cloc frequenc" the circuit can han$le%

(iven the followin( infor!ation?

40setup> 9nS 40hol$ > ,nS 40propa(ation > 1=nS

Circuit: Connect J*ar to ) an$ appl" the cl at cl of )@@ an$ tae the O/8 at J. It (ives freq/,. Ma3.

@req of operation: 1/ #propa(ation $ela"setup ti!e' > 1/19ns > 9,.7 MH6

25'Du"s this is the *asic question ase$ !ost frequentl". )esi(n all the *asic

(ates#-O4%-)%O&%--)%-O&%RO&%R-O&' usin( ,:1 Multiple3er?

sin( ,:1 Mu3% #, inputs% 1 output an$ a select line'

#a' -O4

Dive the input at the select line an$ connect I= to 1 K I1 to =. So if is 1% we will (et I1 that is = at the

O/8.

#*' -)

Dive input at the select line an$ = to I= an$ B to I1. O/p is K B

#c' O&

Dive input at the select line an$ 1 to I1 an$ B to I=. O/p will *e T B

#$' --)

-) -O4 i!ple!entations to(ether

#e' -O&

O& -O4 i!ple!entations to(ether

#f' RO&

at the select line B at I= an$ UB at I1. UB can *e o*taine$ fro! #a' #(' R-O&

at the select line B at I1 an$ UB at I=


17/45

27'- nu!*er of R-O& (ates are connecte$ in series such that the - inputs #=%1%,......' are (iven in

the followin( wa": = K 1 to first R-O& (ate an$ , K O/8 of @irst R-O& to secon$ R-O& (ate an$ so

on..... -th R-O& (ates output is final output. How $oes this circuit wor? +3plain in $etail?

If ->O$$% the circuit acts as even parit" $etector% ie the output will 1 if there are even nu!*er of 1s in

the - input...4his coul$ also *e calle$ as o$$ parit" (enerator since with this a$$itional 1 as output the

total nu!*er of 1s will *e O)).

If ->+ven% Fust the opposite% it will *e O$$ parit" $etector or +ven 8arit" Denerator.

29'n asse!*l" line has 2 fail safe sensors an$ one e!er(enc" shut$own switch.4he line shoul$ eep

!ovin( unless an" of the followin( con$itions arise:

#i' If the e!er(enc" switch is presse$

#ii' If the senor1 an$ sensor, are activate$ at the sa!e ti!e.

#iii' If sensor , an$ sensor2 are activate$ at the sa!e ti!e.

#iv' If all the sensors are activate$ at the sa!e ti!e

Suppose a co!*inational circuit for a*ove case is to *e i!ple!ente$ onl" with --) Dates. How !an"

!ini!u! nu!*er of , input --) (ates are require$?

-o of ,input --) Dates require$ > 9 Nou can tr" the whole i!ple!entation.

2')esi(n a circuit that calculates the square of a nu!*er? It shoul$ not use an" !ultiplier circuits. It

shoul$ use Multiple3ers an$ other lo(ic?

4his is interestin(....

1V,>=1>1

,V,>12>5


18/45

2V,>57>19

7V,>19,7

an$ so on

See a pattern "et?4o (et the ne3t square% all "ou have to $o is a$$ the ne3t o$$ nu!*er to the previous

square that "ou foun$.See how 1%2%7% an$ finall" < are a$$e$.Woul$nt this *e a possi*le solution to

"our question since it onl" will use a counter%!ultiple3er an$ a couple of a$$ers?It see!s it woul$ tae

n cloc c"cles to calculate square of n.

2;' How will "ou i!ple!ent a @ull su*tractor fro! a @ull a$$er?

all the *its of su*trahen$ shoul$ *e connecte$ to the 3or (ate. Other input to the 3or *ein( one.4he

input carr" *it to the full a$$er shoul$ *e !a$e 1. 4hen the full a$$er wors lie a full su*tractor

2


19/45

51'4he question is to $esi(n !ini!al har$ware s"ste!% which encr"pts ;*it parallel $ata.

s"nchroni6e$ cloc is provi$e$ to this s"ste! as well. 4he output encr"pte$ $ata shoul$ *e at the sa!e

rate as the input $ata *ut no necessaril" with the sa!e phase.

4he encr"ption s"ste! is centere$ aroun$ a !e!or" $evice that perfor! a L4 #Loop 4a*le'

conversion. 4his !e!or" functionalit" can *e achieve$ *" usin( a 8&OM% +8&OM% @LSH an$ etc. 4he

$evice contains an encr"ption co$e% which !a" *e *urne$ into the $evice with an e3ternal pro(ra!!er.

In encr"ption operation% the $ata0in is an a$$ress pointer into a !e!or" cell an$ the co!*inatorial

lo(ic (enerates the control si(nals. 4his creates a rea$ access fro! the !e!or". 4hen the !e!or"

$evice (oes to the appropriate a$$ress an$ outputs the associate $ata. 4his $ata represent the $ata0in

after encr"ption. 51' What is an L@S& .List a few of its in$ustr" applications.?

L@S& is a linear fee$*ac shift re(ister where the input *it is $riven *" a linear function of the overall

shift re(ister value. co!in( to in$ustrial applications% as far as I now% it is use$ for encr"ption an$$ecr"ption an$ in BIS4#*uiltinselftest' *ase$ applications..

5,'what is false path?how it $eter!ine in ct? what the effect of false path in ct?

B" ti!in( all the paths in the circuit the ti!in( anal"6er can $eter!ine all the critical paths in the circuit.

However% the circuit !a" have false paths% which are the paths in the circuit which are never e3ercise$

$urin( nor!al circuit operation for an" set of inputs.

n e3a!ple of a false path is shown in fi(ure *elow. 4he path (oin( fro! the input of the first MR

throu(h the co!*inational lo(ic out throu(h the B input of the secon$ MS is a false path. 4his path can

never *e activate$ since if the input of the first MR is activate$% then Sel line will also select the

input of the secon$ MR.

S4 #Static 4i!in( nal"sis' tools are a*le to i$entif" si!ple false paths however the" are not a*le to

i$entif" all the false paths an$ so!eti!es report false paths as critical paths. &e!oval of false paths

!aes circuit testa*le an$ its ti!in( perfor!ance pre$icta*le #so!eti!es faster'


20/45

52'Consi$er two si!ilar processors% one with a cloc sew of 1==ps an$ other with a cloc sew of 7=ps.

Which one is liel" to have !ore power? Wh"?

Cloc sew of 7=ps is !ore liel" to have cloc power. 4his is *ecause it is liel" that lowsew processor

has *etter $esi(ne$ cloc tree with !ore powerful an$ nu!*er of *uffers an$ overhea$s to !ae sew

*etter.

55'What are !ultic"cle paths?

Multic"cle paths are paths *etween re(isters that tae !ore than one cloc c"cle to *eco!e sta*le.

@or e3. nal"6in( the $esi(n shown in fi( *elow shows that the output SI-/COS requires 5 clocc"cles

after the input -DL+ is latche$ in. 4his !eans that the co!*inatorial *loc #the nrolle$ Cor$ic' can

tae up to 5 cloc perio$s #,7MH6' to propa(ate its result. 8lace an$ &oute tools are capa*le of fi3in(

!ultic"cle paths pro*le!.

57'Nou have two counters countin( upto 19% *uilt fro! ne(e$(e )@@ % @irst circuit is s"nchronous an$

secon$ is ripple #casca$in('% Which circuit has a less propa(ation $ela"? Wh"?

4he s"nchronous counter will have lesser $ela" as the input to each flop is rea$il" availa*le *efore the

cloc e$(e. Whereas the casca$e counter will tae lon( ti!e as the output of one flop is use$ as cloc to

the other. So the $ela" will *e propa(atin(. @or +(: 19 state counter > 5 *it counter > 5 @lip flops Let

1=ns *e the $ela" of each flop 4he worst case $ela" of ripple counter > 1= 5 > 5=ns 4he $ela" of

s"nchronous counter > 1=ns onl".#)ela" of 1 flop'

59' what is $ifference *etween &M an$ @I@O?

@I@O $oes not have a$$ress lines

&a! is use$ for stora(e purpose where as fifo is use$ for s"nchroni6ation purpose i.e. when two

peripherals are worin( in $ifferent cloc $o!ains then we will (o for fifo.


21/45

5'4he circle can rotate clocwise an$ *ac. se !ini!u! har$ware to *uil$ a circuit to in$icate the

$irection of rotatin(.?

, sensors are require$ to fin$ out the $irection of rotatin(. 4he" are place$ lie at the $rawin(. One of

the! is connecte$ to the $ata input of ) flipflop%an$ a secon$ one to the cloc input. If the circle

rotates the wa" cloc sensor sees the li(ht first while ) input #secon$ sensor' is 6ero the output of the

flipflop equals 6ero% an$ if ) input sensor fires first the output of the flipflop *eco!es hi(h.

5;' )raw ti!in( $ia(ra!s for followin( circuit.?

5


22/45

2 input -O&:

Sa!e as a*ove Fust interchan(e --) with -O& ## -O& B' -O& # -O& B'' -O& C

2 input R-O&:

Sa!e as a*ove e3cept the inputs for the secon$ R-O& (ate% Output of the first R-O& (ate is one of the

inputs an$ connect the secon$ input to (roun$ or lo(ical =

## R-O& B' R-O& ='' R-O& C

7=' Is it possi*le to re$uce cloc sew to 6ero? +3plain "our answer ?

+ven thou(h there are cloc la"out strate(ies #Htree' that can in theor" re$uce cloc sew to 6ero *"

havin( the sa!e path len(th fro! each flipflop fro! the pll% process variations in & an$ C across the

chip will cause cloc sew as well as a pure H4ree sche!e is not practical #consu!es too !uch area'.

71')esi(n a @SM #@inite State Machine' to $etect a sequence 1=11=?

7,'Convert )@@ into $ivi$e *" ,. #not latch'? What is the !a3 cloc frequenc" of the circuit % (iven the

followin( infor!ation?

40setup> 9nS

40hol$ > ,nS

40propa(ation > 1=nS

Circuit:

Connect J*ar to ) an$ appl" the cl at cl of )@@ an$ tae the O/8 at J. It (ives freq/,.

Ma3. @req of operation:

1/ #propa(ation $ela"setup ti!e' > 1/19ns > 9,.7 MH6


23/45

72'Dive the circuit to e3ten$ the fallin( e$(e of the input *" , cloc pulses?4he wavefor!s are shown in

the followin( fi(ure.

75' @or the Circuit Shown *elow% What is the Ma3i!u! @requenc" of Operation?re there an" hol$ ti!e

violations for @@,? If "es% how $o "ou !o$if" the circuit to avoi$ the!?

4he !inu!u! ti!e perio$ > 2,#111' > ;ns Ma3i!u! @requenc" > 1/;n> 1,7MH6.

n$ there is a hol$ ti!e violation in the circuit%*ecause of fee$*ac% if "ou o*serve% tcq,-) (ate

$ela" is less than thol$,%4o avoi$ this we nee$ to use even nu!*er of inverters#*uffers'. Here we nee$

to use , inverters each with a $ela" of 1ns. then the hol$ ti!e value e3actl" !eets.

77')esi(n a )latch usin( #a' usin( ,:1 Mu3 #*' fro! S& Latch ?

79'How to i!ple!ent a Master Slave flip flop usin( a , to 1 !u3?

7'how !an" , input 3ors are nee$e$ to inple!ent 19 input parit" (enerator ?

It is alwa"s n1 Where n is nu!*er of inputs.So 19 input parit" (enerator will require 17 two input 3ors .

7;')esi(n a circuit for fin$in( the


24/45

cache arent copie$ to !ain !e!or" until a*solutel" necessar". In contrast% a writethrou(h cache

perfor!s all write operations in parallel $ata is written to !ain !e!or" an$ the L1 cache

si!ultaneousl". Write*ac cachin( "iel$s so!ewhat *etter perfor!ance than writethrou(h cachin(

*ecause it re$uces the nu!*er of write operations to !ain !e!or". With this perfor!ance

i!prove!ent co!es a sli(ht ris that $ata !a" *e lost if the s"ste! crashes.

write*ac cache is also calle$ a cop"*ac cache.

9=')ifference *etween S"nchronous%s"nchronous K Is"nchronous co!!unication?

Sen$in( $ata enco$e$ into "our si(nal requires that the sen$er an$ receiver are *oth usin( the sa!e

encon$in(/$eco$in( !etho$% an$ now where to loo in the si(nal to fin$ $ata. s"nchronous s"ste!s

$o not sen$ separate infor!ation to in$icate the enco$in( or clocin( infor!ation. 4he receiver !ust

$eci$e the clocin( of the si(nal on its own. 4his !eans that the receiver !ust $eci$e where to loo inthe si(nal strea! to fin$ ones an$ 6eroes% an$ $eci$e for itself where each in$ivi$ual *it stops an$

starts. 4his infor!ation is not in the $ata in the si(nal sent fro! trans!ittin( unit.

S"nchronous s"ste!s ne(otiate the connection at the $atalin level *efore co!!unication *e(ins.

Basic s"nchronous s"ste!s will s"nchroni6e two clocs *efore trans!ission% an$ reset their nu!eric

counters for errors etc. More a$vance$ s"ste!s !a" ne(otiate thin(s lie error correction an$

co!pression.

4i!e$epen$ent. it refers to processes where $ata !ust *e $elivere$ within certain ti!e constraints.

@or e3a!ple% Multi!e$ia strea! require an isochronous transport !echanis! to ensure that $ata is

$elivere$ as fast as it is $ispla"e$ an$ to ensure that the au$io is s"nchroni6e$ with the vi$eo.

91' What are $ifferent wa"s Multipl" K )ivi$e?

Set quotient to 6ero

&epeat while $ivi$en$ is (reater than or equal to $ivisor

Su*tract $ivisor fro! $ivi$en$

$$ 1 to quotient


25/45

+n$ of repeat *loc

quotient is correct% $ivi$en$ is re!ain$er

S4O8

Binar" )ivision *" Shift an$ Su*tract

Basicall" the reverse of the !utlipl" *" shift an$ a$$.

Set quotient to =

li(n left!ost $i(its in $ivi$en$ an$ $ivisor

&epeat

If that portion of the $ivi$en$ a*ove the $ivisor is (reater than or equal to the $ivisor

4hen su*tract $ivisor fro! that portion of the $ivi$en$ an$

Concatentate 1 to the ri(ht han$ en$ of the quotient


26/45

+lse concatentate = to the ri(ht han$ en$ of the quotient

Shift the $ivisor one place ri(ht

ntil $ivi$en$ is less than the $ivisor

quotient is correct% $ivi$en$ is re!ain$er

S4O8

Binar" Multipl" &epeate$ Shift an$ $$

&epeate$ shift an$ a$$ startin( with a result of =% shift the secon$ !ultiplican$ to correspon$ with

each 1 in the first !ultiplican$ an$ a$$ to the result. Shiftin( each position left is equivalent to

!ultipl"in( *" ,% Fust as in $eci!al representation a shift left is equivalent to !ultipl"in( *" 1=.

Set result to =

&epeat

Shift ,n$ !ultiplican$ left until ri(ht!ost $i(it is line$ up with left!ost 1 in first !ultiplican$

$$ ,n$ !ultiplican$ in that position to result

&e!ove that 1 fro! 1st !ultiplican$


27/45

ntil 1st !ultiplican$ is 6ero

&esult is correct

S4O8

9,'What is a SoC #S"ste! On Chip'% SIC% full custo! chip% an$ an @8D?

4here are no precise $efinitions. Here is !" sense of it all. @irst% 17 "ears a(o% people were unclear on

e3actl" what ALSI !eant. Was it 7==== (ates? 1===== (ates? was is Fust an"thin( *i((er than LSI? M"

professor si!pl" tol$ !e that ALSI is a level of co!ple3it" an$ inte(ration in a chip that $e!an$s

+lectronic )esi(n uto!ation tools in or$er to succee$. In other wor$s% *i( enou(h that !anuall"

$rawin( lots of little *lue% re$ an$ (reen lines is too !uch for a hu!an to reasona*l" $o. I thin that%liewise% SoC is that level of inte(ration onto a chip that $e!an$s !ore e3pertise *e"on$ tra$itional

sills of electronics. In other wor$s% pullin( off a SoC $e!an$s Har$ware% Software% an$ S"ste!s

+n(ineerin( talent. So% triviall"% SoCs a((ressivel" co!*ine HW/SW on a sin(le chip. Ma"*e !ore

pra(!aticall"% SoC Fust !eans that SIC an$ Software fols are learnin( a little *it !ore a*out each

others techniques an$ tools than the" $i$ *efore. 4wo other interpretations of SoC are 1' a chip that

inte(rates various I8 #Intellectual 8ropert"' *locs on it an$ is thus hi(hl" centere$ with issues lie

&euse% an$ ,' a chip inte(ratin( !ultiple classes of electronic circuitr" such as )i(ital CMOS% !i3e$

si(nal $i(ital an$ analo( #e.(. sensors% !o$ulators% /)s'% )&M !e!or"% hi(h volta(e power% etc.


28/45

SIC stan$s for pplication Specific Inte(rate$ Circuit. chip $esi(ne$ for a specific application.

suall"% I thin people associate SICs with the Stan$ar$ Cell $esi(n !etho$olo(". Stan$ar$ Cell $esi(n

an$ the t"pical SIC flow usuall" !eans that $esi(ners are usin( Har$ware )escription Lan(ua(es%

S"nthesis an$ a li*rar" of pri!itive cells #e.(. li*raries containin( -)% --)% O&% -O&% -O4% @LI8@LO8%

L4CH% ))+&% B@@+&% 8) cells that are wire$ to(ether #real li*raries are not this si!ple% *ut "ou (et

the i$ea..'. )esi(n usuall" is -O4 $one at a transistor level. 4here is a hi(h reliance on auto!ate$ tools

*ecause the assu!ption is that the chip is *ein( !a$e for a S8+CI@IC 88LIC4IO- where ti!e is of the

essence. But% the chip is !anufacture$ fro! scratch in that no pre!a$e circuitr" is *ein( pro(ra!!e$

or reuse$. SIC $esi(ner !a"% or !a" not% even *e aware of the locations of various pieces of circuitr"

on the chip since the tools $o !uch of the construction% place!ent an$ wirin( of all the little pieces.

@ull Custo!% in contrast to SIC #or Stan$ar$ Cell'% !eans that ever" (eo!etric feature (oin( onto the

chip *ein( $esi(ne$ #thin of those prett" chip pictures we have all seen' is controlle$% !ore or less% *"

the hu!an $esi(n. uto!ate$ tools are certainl" use$ to wire up $ifferent parts of the circuit an$

!a"*e even !anipulate #repeat% rotate% etc.' sections of the chip. But% the hu!an $esi(ner is activel"

en(a(e$ with the ph"sical features of the circuitr". Hi(her hu!an craftin( an$ less reliance on stan$ar$

cells taes !ore ti!e an$ i!plies hi(her -&+ costs% *ut lowers &+ costs for stan$ar$ parts lie

!e!ories% processors% uarts% etc.

@8Ds% or @iel$ 8ro(ra!!a*le Date rra"s are co!pletel" $esi(ne$ chips that $esi(ners loa$ a

pro(ra!!in( pattern into to achieve a specific $i(ital function. *it pattern #al!ost lie a software

pro(ra!' is loa$e$ into the alrea$" !anufacture$ $evice which essentiall" interconnects lots of

availa*le (ates to !eet the $esi(ners purposes. @8Ds are so!eti!es thou(ht of as a Sea of Dates

where the $esi(ner specifies how the" are connecte$. @8D $esi(ners often use !an" of the sa!e tools

that SIC $esi(ners use% even thou(h the @8D is inherentl" !ore fle3i*le. ll these thin(s can *e

inter!i3e$ in h"*ri$ sorts of wa"s. @or e3a!ple% @8Ds are now availa*le that have !icroprocessor

e!*e$$e$ within the! which were $esi(ne$ in a full custo! !anner% all of which now $e!an$s SoC

t"pes of HW/SW inte(ration sills fro! the $esi(ner.

92'What is Scan ?

Scan Insertion an$ 48D helps test SICs #e.(. chips' $urin( !anufacture. If "ou now what G4D

*oun$ar" scan is% then Scan is the sa!e i$ea e3cept that it is $one insi$e the chip instea$ of on the

entire *oar$. Scan tests for $efects in the chips circuitr" after it is !anufacture$ #e.(. Scan $oes not

help "ou test whether "our )esi(n functions as inten$e$'. SIC $esi(ners usuall" i!ple!ent the scan


29/45

the!selves an$ occurs Fust after s"nthesis. 48D #uto!ate$ 4est 8attern Deneration' refers to the

creation of 4est Aectors that the Scan circuitr" ena*les to *e intro$uce$ into the chip. Heres a *rief

su!!ar":

X Scan Insertion is $one *" a tool an$ results in all #or !ost' of "our $esi(ns flipflops to *e replace$ *"

special Scan @lipflops. Scan flops have a$$itional inputs/outputs that allow the! to *e confi(ure$ into

a chain #e.(. a *i( shift re(ister' when the chip is put into a test !o$e.

X 4he Scan flipflops are connecte$ up into a chain #perhaps !ultiple chains'

X 4he 48D tool% which nows a*out the scan chain "ouve create$% (enerates a series of test vectors.

X 4he 48D test vectors inclu$e *oth Sti!ulus an$ +3pecte$ *it patterns. 4hese *it vectors are

shifte$ into the chip on the scan chains% an$ the chips reaction to the sti!ulus is shifte$ *ac out a(ain.

X 4he 4+ #uto!ate$ 4est +quip!ent' at the chip factor" can put the chip into the scan test !o$e% an$

appl" the test vectors. If an" vectors $o not !atch% then the chip is $efective an$ it is thrown awa".

X Scan/48D tools will strive to !a3i!i6e the covera(e of the 48D vectors. In other wor$s% (iven

so!e !easure of the total nu!*er of no$es in the chip that coul$ *e fault" #shorte$% (roun$e$% stuc

at 1% stuc at ='% what percenta(e of the! can *e $etecte$ with the 48D vectors? Scan is a (oo$

technolo(" an$ can achive hi(h covera(e in the


30/45

X Chec out the S"nops"s WWW site for !ore info.

1' Write a verilo( co$e to swap contents of two re(isters with an$ without a te!porar" re(ister?

With te!p re(

alwa"s Y #pose$(e cloc'

*e(in

te!p>*

*>a

a>te!p

en$

Without te!p re(


*e(in

a Z> * * Z> a en$ ,' )ifference *etween *locin( an$ non*locin(?#Aerilo( interview questions that is

!ost co!!onl" ase$'


31/45

4he Aerilo( lan(ua(e has two for!s of the proce$ural assi(n!ent state!ent: *locin( an$ non*locin(.

4he two are $istin(uishe$ *" the > an$ Z> assi(n!ent operators. 4he *locin( assi(n!ent state!ent #>

operator' acts !uch lie in tra$itional pro(ra!!in( lan(ua(es. 4he whole state!ent is $one *efore

control passes on to the ne3t state!ent. 4he non*locin( #Z> operator' evaluates all the ri(hthan$

si$es for the current ti!e unit an$ assi(ns the lefthan$ si$es at the en$ of the ti!e unit. @or e3a!ple%

the followin( Aerilo( pro(ra! // testin( *locin( an$ non*locin( assi(n!ent !o$ule *locin( re( =

% B initial *e(in: init1 > 2 [1 > 1 // *locin( proce$ural assi(n!ent B > 1

\$ispla"#Blocin(: > * B> *% % B ' > 2 [1 Z> 1 // non*locin( proce$ural assi(n!ent

B Z> 1 [1 \$ispla"#-on*locin(: > * B> *% % B ' en$ en$!o$ule pro$uces the followin(

output: Blocin(: > =====1== B> =====1=1 -on*locin(: > =====1== B> =====1== 4he effect is for

all the non*locin( assi(n!ents to use the ol$ values of the varia*les at the *e(innin( of the currentti!e unit an$ to assi(n the re(isters new values at the en$ of the current ti!e unit. 4his reflects how

re(ister transfers occur in so!e har$ware s"ste!s. *locin( proce$ural assi(n!ent is use$ for

co!*inational lo(ic an$ non*locin( proce$ural assi(n!ent for sequential

Clic to view !ore

)ifference *etween tas an$ function?

@unction:

function is una*le to ena*le a tas however functions can ena*le other functions.

function will carr" out its require$ $ut" in 6ero si!ulation ti!e. # 4he pro(ra! ti!e will not *e

incre!ente$ $urin( the function routine'

Within a function% no event% $ela" or ti!in( control state!ents are per!itte$

In the invocation of a function their !ust *e at least one ar(u!ent to *e passe$.

@unctions will onl" return a sin(le value an$ can not use either output or inout state!ents.

4ass:


32/45

4ass are capa*le of ena*lin( a function as well as ena*lin( other versions of a 4as

4ass also run with a 6ero si!ulation however the" can if require$ *e e3ecute$ in a non 6ero si!ulation

ti!e.

4ass are allowe$ to contain an" of these state!ents.

tas is allowe$ to use 6ero or !ore ar(u!ents which are of t"pe output% input or inout.

4as is una*le to return a value *ut has the facilit" to pass !ultiple values via the output an$ inout

state!ents .

5' )ifference *etween inter state!ent an$ intra state!ent $ela"?

//$efine re(ister varia*les

re( a% *% c

//intra assi(n!ent $ela"s

initial

*e(in

a > = c > =

* > [7 a c //4ae value of a an$ c at the ti!e>=% evaluate

//a c an$ then wait 7 ti!e units to assi(n value

//to *.

en$

//+quivalent !etho$ with te!porar" varia*les an$ re(ular $ela" control

initial

*e(in

a > = c > =


33/45

te!p0ac > a c

[7 * > te!p0ac //4ae value of a c at the current ti!e an$

//store it in a te!porar" varia*le. +ven thou(h a an$ c

//!i(ht chan(e *etween = an$ 7%

//the value assi(ne$ to * at ti!e 7 is unaffecte$.

en$

7' What is $elta si!ulation ti!e?

9' )ifference *etween \!onitor%\$ispla" K \stro*e?

4hese co!!an$s have the sa!e s"nta3% an$ $ispla" te3t on the screen $urin( si!ulation. 4he" are

!uch less convenient than wavefor! $ispla" tools lie cwaves?. \$ispla" an$ \stro*e $ispla" once ever"

ti!e the" are e3ecute$% whereas \!onitor $ispla"s ever" ti!e one of its para!eters chan(es.

4he $ifference *etween \$ispla" an$ \stro*e is that \stro*e $ispla"s the para!eters at the ver" en$ of

the current si!ulation ti!e unit rather than e3actl" where it is e3ecute$. 4he for!at strin( is lie that in

C/C% an$ !a" contain for!at characters. @or!at characters inclu$e $ #$eci!al'% h #he3a$eci!al'%

* #*inar"'% c #character'% s #strin(' an$ t #ti!e'% ! #hierarch" level'. 7$% 7* etc. woul$ (ive

e3actl" 7 spaces for the nu!*er instea$ of the space nee$e$. ppen$ *% h% o to the tas na!e to chan(e

$efault for!at to *inar"% octal or he3a$eci!al.

S"nta3:

\$ispla" #for!at0strin(% par01% par0,% ... '

\stro*e #for!at0strin(% par01% par0,% ... '

\!onitor #for!at0strin(% par01% par0,% ... '

' What is $ifference *etween Aerilo( full case an$ parallel case?


34/45

full case state!ent is a case state!ent in which all possi*le casee3pression *inar" patterns can *e

!atche$ to a case ite! or to a case $efault. If a case state!ent $oes not inclu$e a case $efault an$ if it

is possi*le to fin$ a *inar" case e3pression that $oes not !atch an" of the $efine$ case ite!s% the case

state!ent is not full.

parallel case state!ent is a case state!ent in which it is onl" possi*le to !atch a case e3pression to

one an$ onl" one case ite!. If it is possi*le to fin$ a case e3pression that woul$ !atch !ore than one

case ite!% the !atchin( case ite!s are calle$ overlappin( case ite!s an$ the case state!ent is not

parallel.

;' What is !eant *" inferrin( latches%how to avoi$ it?

Consi$er the followin( :

alwa"s Y#s1 or s= or i= or i1 or i, or i2'

case #]s1% s=^'

,$= : out > i=

,$1 : out > i1

,$, : out > i,

en$case

in a case state!ent if all the possi*le co!*inations are not co!pare$ an$ $efault is also not specifie$

lie in e3a!ple a*ove a latch will *e inferre$ %a latch is inferre$ *ecause to repro$uce the previous value

when unnown *ranch is specifie$.

@or e3a!ple in a*ove case if ]s1%s=^>2 % the previous store$ value is repro$uce$ for this storin( a latch is

inferre$.

4he sa!e !a" *e o*serve$ in I@ state!ent in case an +LS+ I@ is not specifie$.

4o avoi$ inferrin( latches !ae sure that all the cases are !entione$ if not $efault con$ition is provi$e$.


35/45

+3ecution of *locin( assi(n!ents can *e viewe$ as a onestep process:

1. +valuate the &HS #ri(hthan$ si$e equation' an$ up$ate the LHS #lefthan$ si$e e3pression' of the

*locin( assi(n!ent without interruption fro! an" other Aerilo( state!ent. *locin( assi(n!ent

*locs trailin( assi(n!ents in the sa!e alwa"s *loc fro! occurrin( until after the current assi(n!ent

has *een co!plete$

+3ecution of non*locin( assi(n!ents can *e viewe$ as a twostep process:

1. +valuate the &HS of non*locin( state!ents at the *e(innin( of the ti!e step. ,. p$ate the LHS of

non*locin( state!ents at the en$ of the ti!e step.

1=' Aaria*le an$ si(nal which will *e p$ate$ first?

Si(nals

11' What is sensitivit" list?

4he sensitivit" list in$icates that when a chan(e occurs to an" one of ele!ents in the list chan(e%

*e(in_en$ state!ent insi$e that alwa"s *loc will (et e3ecute$.

1,' In a pure co!*inational circuit is it necessar" to !ention all the inputs in sensitivit" $is? if "es%

wh"?

Nes in a pure co!*inational circuit is it necessar" to !ention all the inputs in sensitivit" $is other wise it

will result in pre an$ post s"nthesis !is!atch.

12' 4ell !e structure of Aerilo( co$e "ou follow?


36/45

(oo$ te!plate for "our Aerilo( file is shown *elow.

// ti!escale $irective tells the si!ulator the *ase units an$ precision of the si!ulation

`ti!escale 1 ns / 1= ps

!o$ule na!e #input an$ outputs'

// para!eter $eclarations

para!eter para!eter0na!e > para!eter value

// Input output $eclarations

input in1

input in, // sin(le *it inputs

output !s* out // a *us output

// internal si(nal re(ister t"pe $eclaration re(ister t"pes #onl" assi(ne$ within alwa"s state!ents'. re(

re(ister varia*le 1

re( !s* re(ister varia*le ,

// internal si(nal. net t"pe $eclaration #onl" assi(ne$ outsi$e alwa"s state!ents' wire net varia*le 1

// hierarch" instantiatin( another !o$ule

reference na!e instance na!e #

.pin1 #net1'%

.pin, #net,'%

.

.pinn #netn'

'

// s"nchronous proce$ures


*e(in

.


37/45

en$

// co!*inatinal proce$ures

alwa"s Y #si(nal1 or si(nal, or si(nal2'

*e(in

.

en$

assi(n net varia*le > co!*inational lo(ic

en$!o$ule

15' )ifference *etween Aerilo( an$ vh$l?

Co!pilation

AH)L. Multiple $esi(nunits #entit"/architecture pairs'% that resi$e in the sa!e s"ste! file% !a" *e

separatel" co!pile$ if so $esire$. However% it is (oo$ $esi(n practice to eep each $esi(n unit in its own

s"ste! file in which case separate co!pilation shoul$ not *e an issue.

Aerilo(. 4he Aerilo( lan(ua(e is still roote$ in its native interpretative !o$e. Co!pilation is a !eans of

spee$in( up si!ulation% *ut has not chan(e$ the ori(inal nature of the lan(ua(e. s a result care !ust

*e taen with *oth the co!pilation or$er of co$e written in a sin(le file an$ the co!pilation or$er of

!ultiple files. Si!ulation results can chan(e *" si!pl" chan(in( the or$er of co!pilation.

)ata t"pes

AH)L. !ultitu$e of lan(ua(e or user $efine$ $ata t"pes can *e use$. 4his !a" !ean $e$icate$

conversion functions are nee$e$ to convert o*Fects fro! one t"pe to another. 4he choice of which $ata

t"pes to use shoul$ *e consi$ere$ wisel"% especiall" enu!erate$ #a*stract' $ata t"pes. 4his will !ae

!o$els easier to write% clearer to rea$ an$ avoi$ unnecessar" conversion functions that can clutter the


38/45

co$e. AH)L !a" *e preferre$ *ecause it allows a !ultitu$e of lan(ua(e or user $efine$ $ata t"pes to *e

use$.

Aerilo(. Co!pare$ to AH)L% Aerilo( $ata t"pes a re ver" si!ple% eas" to use an$ ver" !uch (eare$

towar$s !o$elin( har$ware structure as oppose$ to a*stract har$ware !o$elin(. nlie AH)L% all $ata

t"pes use$ in a Aerilo( !o$el are $efine$ *" the Aerilo( lan(ua(e an$ not *" the user. 4here are net

$ata t"pes% for e3a!ple wire% an$ a re(ister $ata t"pe calle$ re(. !o$el with a si(nal whose t"pe is

one of the net $ata t"pes has a correspon$in( electrical wire in the i!plie$ !o$ele$ circuit. O*Fects%

that is si(nals% of t"pe re( hol$ their value over si!ulation $elta c"cles an$ shoul$ not *e confuse$ with

the !o$elin( of a har$ware re(ister. Aerilo( !a" *e preferre$ *ecause of its si!plicit".

)esi(n reusa*ilit"

AH)L. 8roce$ures an$ functions !a" *e place$ in a paca(e so that the" are avail a*le to an" $esi(n

unit that wishes to use the!.

Aerilo(. 4here is no concept of paca(es in Aerilo(. @unctions an$ proce$ures use$ within a !o$el !ust

*e $efine$ in the !o$ule. 4o !ae functions an$ proce$ures (enerall" accessi*le fro! $ifferent !o$ule

state!ents the functions an$ proce$ures !ust *e place$ in a separate s"ste! file an$ inclu$e$ usin(

the inclu$e co!piler $irective.

17' What are $ifferent st"les of Aerilo( co$in( I !ean (atelevel%continuous level an$ others e3plain in

$etail?

19' Can "ou tell !e so!e of s"ste! tass an$ their purpose?

\$ispla"% \$ispla"*% \$ispla"h% \$ispla"o% \write% \write*% \writeh% \writeo.

4he !ost useful of these is \$ispla".4his can *e use$ for $ispla"in( strin(s% e3pression or values of

varia*les.

Here are so!e e3a!ples of usa(e.

\$ispla"#Hello oni'

output: Hello oni


39/45

\$ispla"#\ti!e' // current si!ulation ti!e.

output: 59=

counter > 5*1=

\$ispla"# 4he count is *% counter'

output: 4he count is ==1=

\reset resets the si!ulation *ac to ti!e = \stop halts the si!ulator an$ puts it in interactive !o$e

where the

user can enter co!!an$s \finish e3its the si!ulator *ac to the operatin( s"ste!

1' Can "ou list out so!e of enhance!ents in Aerilo( ,==1?

In earlier version of Aerilo( %we use or to specif" !ore than one ele!ent in sensitivit" list . In Aerilo(

,==1% we can use co!!a as shown in the e3a!ple *elow.

// Aerilo( , e3a!ple for usa(e of co!!a

alwa"s Y #i1%i,%i2%i5'

Aerilo( ,==1 allows us to use star in sensitive list instea$ of listin( all the varia*les in &HS of co!*o

lo(ics . 4his re!oves t"po !istaes an$ thus avoi$s si!ulation an$ s"nthesis !is!atches%

Aerilo( ,==1 allows port $irection an$ $ata t"pe in the port list of !o$ules as shown in the e3a!ple

*elow

!o$ule !e!or" #

input r%

input wr%

input $ata0in%

input 2 a$$r%

output $ata0out


40/45

'

1;'Write a Aerilo( co$e for s"nchronous an$ as"nchronous reset?

S"nchronous reset% s"nchronous !eans cloc $epen$ent so reset !ust not *e present in sensitivit" $is

e(:

alwa"s Y #pose$(e cl '

*e(in if #reset'

. . . en$

s"nchronous !eans cloc in$epen$ent so reset !ust *e present in sensitivit" list.

+(

lwa"s Y#pose$(e cloc or pose$(e reset'

*e(in

if #reset'

. . . en$

1


41/45

,=' 4here is a trian(le an$ on it there are 2 ants one on each corner an$ are free to !ove alon( si$es of

trian(le what is pro*a*ilit" that the" will colli$e?

nts can !ove onl" alon( e$(es of trian(le in either of $irection% lets sa" one is represente$ *" 1 an$

another *" =% since there are 2 si$es ei(ht co!*inations are possi*le% when all ants are (oin( in sa!e

$irection the" wont colli$e that is 111 or === so pro*a*ilit" of collision is ,/;>1/5

,1' 4ell !e a*out file I/O?

,1'What is $ifference *etween free6e $eposit an$ force?

\$eposit#varia*le% value'

4his s"ste! tas sets a Aerilo( re(ister or net to the specifie$ value. varia*le is the

re(ister or net to *e chan(e$ value is the new value for the re(ister or net. 4he value

re!ains until there is a su*sequent $river transaction or another \$eposit tas for the

sa!e re(ister or net. 4his s"ste! tas operates i$enticall" to the Mo$elSi!

force $eposit co!!an$.

4he force co!!an$ has free6e% $rive% an$ $eposit options. When none of these is

specifie$% then free6e is assu!e$ for unresolve$ si(nals an$ $rive is assu!e$ for resolve$

si(nals. 4his is $esi(ne$ to provi$e co!pati*ilit" with force files. But if "ou prefer free6e

as the $efault for *oth resolve$ an$ unresolve$ si(nals.

Aerilo( interview Juestions

,,'Will case infer priorit" re(ister if "es how (ive an e3a!ple?

"es case can infer priorit" re(ister $epen$in( on co$in( st"le


42/45

re( r

// 8riorit" enco$e$ !u3%

alwa"s Y #a or * or c or select,'

*e(in

r > c

case #select,'

,*==: r > a

,*=1: r > *

en$case

en$


,2'Case3%6 $ifference%which is prefera*le%wh"?

CS+ :

Special version of the case state!ent which uses a lo(ic value to represent $ontcare *its. CS+R :

Special version of the case state!ent which uses or R lo(ic values to represent $ontcare *its.

CS+ shoul$ *e use$ for case state!ents with wil$car$ $ont cares% otherwise use of CS+ is require$

CS+R shoul$ never *e use$.

4his is *ecause:

)ont cares are not allowe$ in the case state!ent. 4herefore case3 or case6 are require$. Case3 will

auto!aticall" !atch an" 3 or 6 with an"thin( in the case state!ent. Case6 will onl" !atch 6s 3s

require an a*solute !atch.


,5'Diven the followin( Aerilo( co$e% what value of a is $ispla"e$?


43/45

alwa"s Y#cl' *e(in

a > =

a Z> 1 \$ispla"#a' en$ 4his is a tric" oneQ Aerilo( sche$ulin( se!antics *asicall" i!pl" a fourlevel

$eep queue for the current si!ulation ti!e: 1: ctive +vents #*locin( state!ents' ,: Inactive +vents #[=

$ela"s% etc' 2: -onBlocin( ssi(n p$ates #non*locin( state!ents' 5: Monitor +vents #\$ispla"%

\!onitor% etc'. Since the a > = is an active event% it is sche$ule$ into the 1st queue. 4he a Z> 1 is a

non*locin( event% so its place$ into the 2r$ queue. @inall"% the $ispla" state!ent is place$ into the 5th

queue. Onl" events in the active queue are co!plete$ this si! c"cle% so the a > = happens% an$ then

the $ispla" shows a > =. If we were to loo at the value of a in the ne3t si! c"cle% it woul$ show 1. ,7'

What is the $ifference *etween the followin( two lines of Aerilo( co$e?

[7 a > *

a > [7 *

[7 a > * Wait five ti!e units *efore $oin( the action for a > *.

a > [7 * 4he value of * is calculate$ an$ store$ in an internal te!p re(ister%fter five ti!e units% assi(n

this store$ value to a.

,9'What is the $ifference *etween:

c > foo ? a : *

an$

if #foo' c > a

else c > *

4he ? !er(es answers if the con$ition is 3% so for instance if foo > 1*3% a > *1=% an$ * > *11% "ou$ (et

c > *13. On the other han$% if treats Rs or s as @LS+% so "ou$ alwa"s (et c > *.

,'What are Intertial an$ 4ransport )ela"s ??


44/45

,;'What $oes `ti!escale 1 ns/ 1 ps si(nif" in a verilo( co$e?

ti!escale $irective is a co!piler $irective.It is use$ to !easure si!ulation ti!e or $ela" ti!e. sa(e :

`ti!escale

25'what is verilo( case #1' ?

wire 2 3

alwa"s Y#...' *e(in

case #1*1'

3=: SOM+4HI-D1

31: SOM+4HI-D,

3,: SOM+4HI-D2

32: SOM+4HI-D5

en$case

en$

4he case state!ent wals $own the list of cases an$ e3ecutes the first one that !atches. So here% if the

lowest 1*it of 3 is *it ,% then so!ethin(2 is the state!ent that will (et e3ecute$ #or selecte$ *" the

lo(ic'.

27' Wh" is it that if #,*=1 K ,*1='... $oesnt run the true case?

4his is a popular co$in( error. Nou use$ the *it wise -) operator #K' where "ou !eant to use the

lo(ical -) operator #KK'.

29'What are )ifferent t"pes of Aerilo( Si!ulators ?


45/45

4here are !ainl" two t"pes of si!ulators availa*le.

+vent )riven

C"cle Base$

+vent*ase$ Si!ulator:

4his )i(ital Lo(ic Si!ulation !etho$ sacrifices perfor!ance for rich functionalit": ever" active si(nal is

calculate$ for ever" $evice it propa(ate .........

SO&C+:

http://vlsiques.*lo(spot.co!/

I hope "ou lie$

Documents

Core Interview Quesns