core generator guide

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CORE GeneratorGuide


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CORE Generator Guide www.xilinx.com 1-800-255-7778

"Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved.

CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are

registered trademarks of Xilinx, Inc.

The shadow X shown above is a trademark of Xilinx, Inc.

ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator,CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...andBeyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia,MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, RocketIO, SelectIO, SelectRAM, SelectRAM+,Silicon Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap, UIM, VectorMaze,VersaBlock, VersaRing, Virtex-II Pro, Virtex-II EasyPath, Wave Table, WebFITTER, WebPACK, WebPOWERED, XABEL, XACT-Floorplanner, XACT-Performance, XACTstep Advanced, XACTstep Foundry, XAM, XAPP, X-BLOX +, XC designated products, XChecker,

XDM, XEPLD, Xilinx Foundation Series, Xilinx XDTV, Xinfo, XSI, XtremeDSP and ZERO+ are trademarks of Xilinx, Inc.

The Programmable Logic Company is a service mark of Xilinx, Inc.

All other trademarks are the property of their respective owners.

Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it conveyany license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at anytime, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility forthe use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, orinformation shown or described herein "as is." By providing the design, code, or information as one possible implementation of a feature,application, or standard, Xilinx makes no representation that such implementation is free from any claims of infringement. You areresponsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever withrespect to the adequacy of any such implementation, including but not limited to any warranties or representations that the implementationis free from claims of infringement, as well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devicesand products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shownor products described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation tocorrect any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume anyliability for the accuracy or correctness of any engineering or software support or assistance provided to a user.

Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications withoutthe written consent of the appropriate Xilinx officer is prohibited.

The contents of this manual are owned and copyrighted by Xilinx. Copyright 1994-2003 Xilinx, Inc. All Rights Reserved. Except as statedherein, none of the material may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any formor by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consentof Xilinx. Any unauthorized use of any material contained in this manual may violate copyright laws, trademark laws, the laws of privacy andpublicity, and communications regulations and statutes.

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http://www.xilinx.com/http://www.xilinx.com/


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Preface

About This Guide

This manu al describes the Xilinx CORE Generator, a design t ool that d elivers

para meterizable cores optimized for Xilinx FPGAs.

Before using this manual, you should be familiar with the operations that are common to

all Xilinx software tools: how to bring up the system , select a tool for use, specify

operations, and manage d esign d ata.

Guide ContentsThis book contains the following chap ters.

Chapter 1, Introduction

Chap ter 2, Getting Started

Chap ter 3, Using the CORE Generator

Chap ter 4, Batch Mode and Polling Mode

Chap ter 5, Schem atic and H DL Design Flows

Chapter 6, The Memory Editor

Chap ter 7, The Upd ates Installer

App endix A, Get Models Appendix B, Configuration Files and Global Preferences

Appendix C, Troubleshooting th e CORE Generator System

Additional Resources

For add itional informa tion, go to http :/ / suppor t.xilinx.com. The following table lists

some of th e resources you can access from this w ebsite. You can also d irectly access these

resources using the provided URLs.

Resource Description/URL

Tutorials Tutorials covering Xilinx design flows, from design entry toverification and debugging

http:/ / support.xilinx.com/ support/ techsup/ tutorials/ index.htm

Answer Browser Database of Xilinx solution records

http:/ / support.xilinx.com/ xlnx/ xil_ans_browser.jsp
http://www.xilinx.com/http://support.xilinx.com/http://support.xilinx.com/support/techsup/tutorials/index.htmhttp://www.support.xilinx.com/xlnx/xil_ans_browser.jsphttp://www.support.xilinx.com/xlnx/xil_ans_browser.jsphttp://support.xilinx.com/support/techsup/tutorials/index.htmhttp://support.xilinx.com/http://www.xilinx.com/


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4 www.xilinx.com CORE Generator Guide1-800-255-7778

Preface: About This GuideR

ConventionsThis documen t uses the following conven tions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:

App lication N otes Descriptions of device-specific design techniques and app roaches

http:/ / su pp ort.xilinx.com/ app s/ app sweb.htm

Data Book Pages from The Programmable Logic Data Book, which contains

device-specific information on Xilinx device characteristics,

including readback, bound ary scan, configuration, length coun t,

and d ebugging

http:/ / support.xilinx.com/ partinfo/ databook.htm

Problem Solvers Interactive tools that allow you to troubleshoot your design issues

http:/ / support.xilinx.com/ support/ troubleshoot/ psolvers.htm

Tech Tips Latest news, design tips, and patch information for the Xilinx

design environment

http :/ / w ww.supp ort.xilinx.com/ xlnx/ xil_tt_hom e.jsp

Resource Description/URL

Convention Meaning or Use Example

Courier font

Messages, prompts, and

program files that the system

displays

speed grade: - 100

Courier boldLiteral commands that you

enter in a syn tactical statementngdbuilddesign_name

Helvetica bold

Command s that you select

from a m enuFile Open

Keyboard shortcuts Ctrl+C

Italic font

Variables in a syntax

statement for which you m ust

supp ly values

ngdbuilddesign_name

References to other manu als

See the Development System

Reference Guide for more

information.

Emph asis in text

If a wire is draw n so that it

overlaps the p in of a symbol,

the two nets are notconnected.
http://www.xilinx.com/http://support.xilinx.com/apps/appsweb.htmhttp://support.xilinx.com/partinfo/databook.htmhttp://www.support.xilinx.com/support/troubleshoot/psolvers.htmhttp://www.support.xilinx.com/xlnx/xil_tt_home.jsphttp://www.support.xilinx.com/xlnx/xil_tt_home.jsphttp://www.support.xilinx.com/support/troubleshoot/psolvers.htmhttp://support.xilinx.com/partinfo/databook.htmhttp://support.xilinx.com/apps/appsweb.htmhttp://www.xilinx.com/


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ConventionsR

Online Document

The following conventions are used in this docum ent:

Square brackets [ ]

An op tional entry or

parameter. However, in bu s

specifications, such as

bus[7:0], they are required.

ngdbuild [option_name]

design_name

Braces { } A list of items from w hich youmust choose one or more

lowpwr ={on|off}

Vertical bar |Separa tes items in a list of

choiceslowpwr ={on|off}

Vertical ellipsis

.

.

.

Repetitive material that has

been omitted

IOB #1: Name = QOUT

IOB #2: Name = CLKIN

.

.

.

Horizontal ellipsis . . .Repetitive material that has

been omitted

allow blockblock_name

loc1 loc2 ... locn;



Blue text

Cross-reference link to a

location in th e current file or

in another file in the cur rent

document

See the section Additional

Resources for details.

Refer to Title Formats in

Chapter 1 for details.

Red text Cross-reference link to alocation in another d ocument See Figure 2-5 in the Virtex-IIHandbook.

Blue, und erlined text Hyp erlink to a w ebsite (URL)Go to http :/ / www.xilinx.com

for the latest speed files.


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Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Online Docum ent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 1: Introduction

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

New Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Xilinx Smart-IP Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14CORE Version Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Obsolete and Removed Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 2: Getting Started

System Requirements and Installation Information . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Starting the CORE Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Starting th e CORE Generator From the Windows Environment . . . . . . . . . . . . . . . . . 18

Starting the CORE Generator From the UN IX Workstation Environmen t . . . . . . . . . 18

Starting the CORE Generator from Xilinx ISE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Setting Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Command Line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Using the Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Main Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Menu Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Standard Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23View Catalog Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Cores Catalog Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Generated Modu les Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Console Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Using Dialog Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Using Comm on Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Browse Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Accessing Core Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Chapter 3: Using the CORE Generator

Using the Cores Catalog Brow ser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Sorting th e Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Adjusting Column s and Pan els . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Using the Generated Mod ules Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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Accessing New and Updated Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Installing New Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Working With Licensed Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Creating a N ew Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Opening an Existing Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Changing Project Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Outp ut Op tions Flow Vendor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Target Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Overwrite Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Netlist Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Design Flows Supp orted by th e CORE Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Output Options Outpu t Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Target Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Overwrite Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Output Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Forma l Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Elaboration Op tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Netlist Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Creating a Customized Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Recustomizing a Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Regenerating a Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Selecting Target XILINX FPGA Family Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Using the Web Brow ser and the PDF Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Setting Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Location of Web Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Location of PDF Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Use Proxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Proxy Host and Proxy Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Automa tically open last pr oject . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Automatically overwrite output files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Only d isplay su pp orted cores for target architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Display obsolete cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Close IP Customization Dialog after Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

CORE Generator Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Accessing Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Configuring the Cores Catalog Brow ser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Add ing Core Customizers to the Cores Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Visibility Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Removing Cores from View in the Cores Catalog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Copying a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Input and Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Using Core Customization GUIs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Core Customization GUI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Nam ing CORE Generator Modu les . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Using Customization GUI Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Illegal or Invalid Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Using the Core Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Setting Op tions Using the Core Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

COE Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60


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Generating Cores i n Batch Mod e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Performing CORE Generator Operations in Xilinx ISE . . . . . . . . . . . . . . . . . . . . . . . 65

Integrating CORE Generator into Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

ASY and XSF Symbol Information Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Chapter 4: Batch Mode and Polling Mode

Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Batch Mode Command Line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Command Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67coregen.ini/ coregen_user_name.ini . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

User-Generated Com mand Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

XCO Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

XCO File Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

XCP files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

coregen.log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

CORE Generator Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Supported Commands in XCO and XCP Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

CORE Generator Global Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Project Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Output Polling Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Inpu t Polling Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Chapter 5: Schematic and HDL Design Flows

Understanding Schematic Design Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77ISE Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Mentor Design Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Mentor eProd uct (Formerly Innov eda) Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Mentor Design Architect Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Cadence Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Introduction to HDL Design Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79HD L Behavioral Simulation Flow Featur es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Creating Verilog Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Verilog HDL Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Verilog Design Flow Procedu re . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Verilog m yadd er8.veo Instantiation Temp late File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Verilog Parent Design File: myad der8_top.v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

add er_tb.v File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Synplicity Verilog Black Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Creating VHD L Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

VHD L HD L Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92VHDL Design Flow Procedu re . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

VHDL Template File myad der8.vho . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

VHDL Parent Design File myad der8_top.vhd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96VHDL Test Bench File myad der_tb.vhd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

VHDL Black Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99


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Using Instantiation Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Using a VEO Instan tiation Template File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Verilog Instantiation Temp late for an 8-Bit Add er . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Verilog Wrapp er file for ad der8: add er8.v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Using a VHO Instantiation Template File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

VHDL Instantiation Temp late for ad der8. (adder8.vho) . . . . . . . . . . . . . . . . . . . . . . . . 103VHDL Wrapp er File for add er8: add er8.vhd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Chapter 6: The Memory Editor

Memory Editor Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107The Memory Editor GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Creating a Memory wi th a Single Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Adding Additional Memory Blocks to a Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Specify ing COE File Keyw ords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Importing a CSV File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Generating a CSV File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

CGF File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Sample CGF and COE Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Sample CGF and COE Files Single Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Sample CGF File Specifying a Single Mem ory Block (single.cgf) . . . . . . . . . . . . . . . . . 117COE File Generated from single.cgf (single_tiger.coe) . . . . . . . . . . . . . . . . . . . . . . . . . 118

Sample CGF and COE Files Multiple Mem ory Blocks . . . . . . . . . . . . . . . . . . . . . . . 118Sample CGF File Defining 3 Memory Blocks (mu ltiple.cgf) . . . . . . . . . . . . . . . . . . . . . 118

COE file generated for block #1 of the memory specified by the CGF file multiple.cgf

(multiple_block1.coe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120COE File Generated for Block #2 of the Memory Specified by th e CGF File mu ltiple.cgf

(multiple_block2.coe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121COE File Generated for Block #3 of the Memory Specified by th e CGF File mu ltiple.cgf

(multiple_block3.coe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Chapter 7: The Updates Installer

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Install Package D efinition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Setting Up your Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Proxy Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Web Browser Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

User Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Required Inputs for IP Upd ate Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Installing Cores usin g the Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . 130

The Selection Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130Selecting Packages to Install . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Running Get Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Appendix A: Get Models

GetModels Ove rview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Command line Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134


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Required Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Optional Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Appendix B: Configuration Files and Global PreferencesCORE Generator Configuration Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

coregen.prj File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

.coregen.prf File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Supported Preference File Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138Preference File Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Global Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Appendix C: Troubleshooting the CORE Generator System

Finding Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

AllianceCORE Modu les . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142Obtaining Customer Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
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Chapter 1

Introduction

This chap ter provid es an overview of the CORE Generator System. The chapter contains

the following sections:

Overview

New Features

Design Flow

CORE Version Managem ent

Overview

The CORE Generator System is a design tool that delivers param eterized cores optimized

for Xilinx FPGAs. It provid es you with a catalog of ready-mad e fun ctions ranging in

complexity from simple arithmetic operators such as adders, accumulators, and

mu ltipliers, to system-level building blocks such as filters, transforms, FIFOs, and

memories.

New Features

The major new and improved features for this release includ e the following.

More CORE Generator operations are integrated into Project Nav igator.

The following CORE Generator operations can now be performed from within Project

Navigator, without opening the CORE Generator GUI:

Adding a customized core to a Project Navigator p roject

Recustomizing a core

Regenerating a core

Regenerating all of the cores in a p roject

Viewing th e HDL fun ctional m odel for a core

Viewing th e CORE Generator log

You can also open the CORE Generator w indow from w ithin ISE to manage th e coresin a project.

All of these operations are described in th e ISE Guide, the ISE online help system. The

core related h elp topics are grouped und er FPGA DesignUsing IntellectualProperty (Cores) in the h elp Table of Contents.

AllianceCORE cores are n o longer listed in the core catalog. Refer to the IP Cen ter

page on xilinx.com (http :/ / ww w.xilinx.com/ ipcenter) for the most u p-to-date

information on th ird par ty AllianceCOREs.
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The CORE Generator main m enu structure has been enhanced to p resent m enu

selections in a mann er wh ich is more logically organized and consistent with other

Xilinx applications.

New global preferences.

A global pr eference lets you close core custom ization GUIs autom atically after a

core has been generated.

A global preference controls whether cores which are schedu led to be obsoleted

are displayed in the core catalog or not.

Memory Editor improvements.

Supp ort for reading and wr iting CSV (Comm a delimited) format da ta files. These

file are typically expor ted from or im ported into Microsoft Excel spread sheets.

The Memory Editor now disp lays the ASCII equivalent of the data va lue in each

mem ory location. The ASCII equivalents are displayed in the rightm ost colum n of

the Memory Contents Panel.

If your m emory d ata has a d ata width of 8, you can now enter an ASCII character

in the ASCII column of the Memory Contents Panel and the equivalent data value

will be placed in the correspond ing memory add ress.

Xilinx Smart-IP Technology

The CORE Generator System creates customized cores which d eliver high levels of

performance and area efficiency. This is accomp lished by taking advan tage of Xilinxs core-

friend ly FPGA architectures and Xilinx Smart-IP technology.

Xilinx Smart-IP technology prov ides FPGA architectural advantages such as look-up

tables (LUTs), distributed and b lock RAM, embed ded mu ltipliers, and segmented routing.

This technology also enables relative location constraints, and expert logic map ping and

floorplanning t o optim ize performan ce of a given core instance in a given Xilinx FPGA

architecture.

Smart-IP technology benefits designers by provid ing the following features:

Physical layout optimized for high performance

Predictable performance and resource utilization

Redu ced pow er requirements achieved through comp act design and interconnect

minimization

Performance independent of target device size

Ability to use mu ltiple instances of the same core on the sam e device withou t

deterioration in performance

Reduced compile time compared to competing architectures

Ability to make d esign size and perform ance trade-offs

Design flexibility

Design Flow

For each core it generates, the CO RE Generator System p rodu ces an Electronic Data

Interchange Format (EDIF) netlist (EDN file), a Verilog temp late (VEO) file with a

Verilog (V) wr app er file, and / or a VH DL template (VHO) file with a VHDL (VHD)

wr app er file. It may also create one or m ore NGC an d N DF files. NGC files are prod uced

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The Electronic Data N etlist (EDN) and NGC files contain th e information requ ired to

implem ent the mod ule in a Xilinx FPGA. Since NGC files are in bina ry forma t, ASCII

NDF files may also be produ ced to comm un icate resource and timing inform ation for

NGC files to 3rd par ty syn thesis tools. The ASY and XSF symbo l information files allow

you t o integrate th e CORE Generator mod ule into a schem atic design for ISE (using ECS)

or for third party schema tic captu re tools. VEO and VHO temp late files contain code that

can be used a s a mod el for instantiating a CORE Generator m odu le in a Verilog or VHDL

design. Finally, V and VHD w rapper files are provided t o suppor t functional simu lation.

These files contain simu lation model custom ization data th at is passed to a param eterized

simulation m odel for the core. In the case of Verilog designs, the V w rapper file also

provid es the port inform ation requ ired to integrate the core into a Verilog design for

synthesis.

Note: The V and VHD wrapper files generated by CORE Generator cores are provided mainly to

support simulation and are not synthesizable.

Figure 1-1show s the complete CORE Generator design flow. The grayed areas in the figu re

indicate the por tions of the design flow d irectly associated w ith the CORE Generator. The

left-side gr ay area show s the EDN , VEO, VHO, and schematic symbol files produ ced by the

CORE Generator System. NGC and NDF files may also be p rodu ced for some cores. The

right-side gray area sh ows the XilinxCoreLib and CoreLib sou rce libraries thatare created or up dated du ring CORE Generator and IP m odu le upd ate installation. These

libraries contain the behavioral simulation models for the CORE Generator cores.

CORE Version Management

The CORE Generator is capable of hand ling m ultiple versions of any core or core

customizer. The ability to generate new versions of a core wh ile continuing to main tain

existing versions in a d esign allows you to add newer cores with new functionality w ithoutdisrupting the rest of the design. IP providers can also make fixes in an existing core and

pu blish the fixes in a new version w ithout requiring designers to use the new er version.

Each p roject maintains a list of cores visible to the project, each w ith its own version

nu mber. The cores available to the current p roject are displayed in the right han d p anel of

the m ain CORE Generator window and are specific to that p roject. This listing can be

customized by the designer. When a n ew p roject is created, the latest versions of all

installed cores are mad e visible to that p roject.

Figure 1-1: CORE Generator Design Flow

X9832

Simulation

HDL Editor

COREGenerator

Schematic Editor

Schematic Simulation Tools

Implementation Tools

Symbol

Synthesizer

VHOVEO

EDIF

EDIF

NGCEDN EDIF

CORE Generator

s imprim Unified

XilinxCoreLib

CoreLib

Unisim

VITAL & Verilog

simprim

VITAL, Verilog,

Gate-level

HDL

Test Bench

VHDL

Verilog

VHDL

Verilog

EDIF

SDF

VHDL

Verilog

VHDL

Verilog

SDF

Behavioral Simulation Models

Timing

Simulation

Flow

Functional

Simulation

Flow

Verilog & VHDL

Instantiation

NDF

NGC

NGC
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By d efault, only one version of each core is visible at any on e time w ithin a p roject,

how ever mu ltiple versions of the sam e core can also be made av ailable to a project by

mod ifying the Cores Catalog d isplay. All cores residing in th e repository are a lso available

through batch mode.

Obsolete and Removed Cores

Some IP cores and versions of cores previou sly marked To Be Obsoleted have been

removed in the 6.1i release of the CORE Generator. This includ es all XC4000 and

Spar tan cores and selected older versions of other IP.

If you n eed to generate or recustomize one of the removed cores, you mu st use the 4.2i

software. A comp lete list of removed cores and versions of cores is available at

http :/ / w ww.xilinx.com/ ip center/ coregen/ removed _cores/ index.htm .
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Chapter 2

Get t ing Started

This chap ter describes how to start an d exit the CORE Generator. It also explains the

basic elements and operations of the CORE Generator interface.

The chapter contains th e following sections:

System Requirements and Installation Information

Starting the CORE Generator

Comman d Line Options

Using the Interface


System Requirements and Installation Information

The CORE Generator is installed as part of the ISE 6.1i software from the ISE 6.1i main

Xilinx software release CDs.

The required environment variable settings are:

XILINX var iable: Set th is to you r Xilinx installation d irectory.

PATH variable: Add $XILINX/ bin/ or %XILINX%/ bin /

(depending on platform) to your PATH variable.

Adobe Acrobat v 4.05 or later is needed to launch and view the core data sheets.

Some cores may require more memory than the amount specified for a particular target

FPGA device in the ISE Release Notes and Installation Guide. See the d ata sheets for

individual cores to find their memory requirements.

For Mentor Grap hics eProdu ct (formerly Innoveda) users, you can invoke the

CORE Generator System interface (ePDCore) from w ithin eProd uct. This requ ires that both

eProdu ct and th e Xilinx implemen tation Tools be set up on you r system. Please refer to

Answer Record #11683 at the Answ ers Search web p age for details on this interface.

See the ISE Tutorial or ISE Release Notes and Installation Guide for add itional information on

system requ irements and in stallation instru ctions for the Xilinx software.
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Starting the CORE Generator

The CORE Generator runs on PCs an d w orkstations. You can start th e CORE Generator

from the installed ISE 6.1i software.

Starting the CORE Generator From the Windows Environment

To start the CORE Generator from your Wind ows environm ent, select StartPrograms

Xilinx ISE 6 Accessories CORE Generator System. You can also start the CORE

Generator from within Xilinx ISE (see Starting the CO RE Generator from Xilinx ISE) or

from the EDA environmen ts of Wind ows-based EDA tools. For example, in Innoved a

eProdu ct v2.x DxDesigner, you can create a new schematic, then click the Xilinx menu

in Viewdraw .

On a PC, you can also start the CORE Generator from a command prom pt. To start the

CORE Generator from a comman d promp t, select StartRun in Windows. At the comm and

prompt, type coregen.

Starting the CORE Generator From the UNIX Workstation Environment

At a UN IX shell promp t, type coregen. This starts the CORE Generator System.

Starting the CORE Generator from Xilinx ISE

The CORE Generator can be opened from w ithin Project Navigator in these ways:

If you have ad ded a core to an ISE project, you can then op en the CORE Generator

GUI from within the ISE Project Navigator. Project Navigator w ill run on a PC or a

UNIX workstation.

To op en th e CORE Generator GUI from w ithin Xilinx ISE:

a. In Project Nav igator, select an IP core nam e in the Sources in Project window.

b. Click the "+" icon next to the Coregen process in the Processes for CurrentSource window.

The Manage Cores process shows in the processes window.

c. Double-click on Manage Cores.

The CORE Generator wind ow d isplays.

A n um ber of CORE Generator operations can be performed within Project Navigator

without opening th e CORE Generator w indow. These operations are described in

Performing CORE Generator Op erations in Xilinx ISE in Chapter 3.


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Starting the CORE GeneratorR

Setting Preferences

Your preferences are set through th e Preference Op tions d ialog box (see Figure 2-1), wh ich

is opened by selecting FilePreferences. Preferences are maintained on a p er user basis.

The location at w hich preferences are saved on various platforms is as follows:

Windows Preferences are stored in the Windows r egistry.

UNIX workstation Preferences are stored in you r hom e directory in the.coregen.prf file.

For inform ation abou t how to set preferences, see Setting Preferences in Chap ter 3.

Figure 2-1: Preference Options Dialog Box
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Command Line Options

The CORE Generator System is invoked in batch mod e as follows:

coregen b p

Table 2-1: Command Line Options

Option Definition

-b Invokes the CORE Generator in batch

mod e and th e name of the comman d file

that should be executed du ring the batch

mode run . The command_file_name

argumen t specifies the path to the

comm and file to be executed .

XCO files are common ly specified as the

argumen t to the -b option, but you can

specify an y file containing v alid COREGenerator comman ds.

-i When the -i option is used , the CORE

Generator looks for the sp ecified INI file in

the current w orking directory if no path is

specified. If a different INI profile is

required , then the p ath can be explicitly

specified u sing either an explicit or relative

path nam e. The coregen_ini_file_nameis the

path to the CORE Generator INI file to be

loaded.

If the -i option is not specified, the CORE

Generator System looks for an IN I profile

in the current w orking directory by

default.

-p Specifies the CORE Generator project

directory. The project_path argumen t is the

path to the d esired CORE Generator

Project. This p ath can be specified relative

to the CORE Generator startu p d irectory.

-q This is an option for third p arty tools that

call the CORE Generator System in p olling

mod e. Do notuse in batch mod e. Thepolling_dir_path sup plied is the path to the

polling directory w here the polling m ode

comm unication files are written.


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Command Line OptionsR

-intstyle Determines the integration style in wh ich

the CORE Generator should ru n. The

ise an d xflow argum ents direct the

CORE Generator to run in a m odecompatible with ISE or XFLOW, with

limited messaging and application

identification out pu t. How ever, in the 6.1i

release this behavior has not been

implemented , so there is no d ifference

between the default operation of CORE

Generator and the operation when

invoked with -intstyle ise or

-intstyle xflow. The silent

argumen t opens the CO RE Generator GUI

without displaying a splash screen.

-h Displays the CO RE Generator batch mod e

command line help and version

information.

-d Invokes CORE Generator in d ebug m ode.

Directs the CORE Generator to generate

verbose runtime m essaging.

Table 2-1: Command Line Options

Option Definition


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Using the Interface

This section describes the CORE Generator grap hical user interface and how to use it.

Main Window

This section d escribes the CORE Generator m ain window (shown following).

1. Menu Bar

2. View Catalog Toolbar

3. and 4. Cores Catalog Browser

5. Standard Toolbar

6. Generated Modu les Window

7. Console Window


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Using the InterfaceR

Menu Bar

The menu bar is located u nd er the w indow s title bar (which says Xilinx CORE

Generator).

You can select menu comm and s with the mouse or the keyboard . With the mou se, click the

left mouse button on the comm and. With the keyboard, press the Alt key and type in theletter und erlined in the men u for that comm and .

Some m enu comman ds includ e an ellipsis (...). When you select one of these comman ds, a

dialog box appears.

Standard Toolbar

The Standard toolbar contains comman ds to p erform these common operations on your

designs: Creating a new project

Opening an existing project

Selecting the current project

Customizing a core

Viewing th e da ta sheet for a core

Recustom izing or regenerating a core

View Catalog Toolbar

The View Catalog toolbar allows you to choose how the available cores are displayed in th e

CORE Generator window.

Cores can be disp layed in the following ways:

by Function (default)Displays the cores in folder s, sorted according to fun ction.

Alphabetically

Displays the cores in a lphabetical order.

by Vendor

Displays the cores by vendor (IP prov ider).

Figure 2-2: Menu Bar Selections

Figure 2-3: Standard Toolbar

Figure 2-4: View Catalog Toolbar


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by Family

Displays the cores by d evice family.

by Type

Displays sepa rate listings for LogiCORE cores and Reference Designs

Cores Catalog BrowserThe Cores Catalog Browser d isplays the cores that can be customized and included in your

CORE Generator project.

The left han d portion of the Cores Catalog Browser, the Core Browser Navigation Pan el,

contains a set of folders arran ged hierarchically. The folders disp layed in the Core Browser

Navigation Pan el can be organized by core Function, by Type (LogiCORE or Reference

Design), by Vend or (IP p rovider), by dev ice Family, or Alphabetically (see View Catalog

Toolbar).

The right han d p ortion of the Cores Catalog Browser, the Core Browser Contents Pan el,

displays th e selection of core custom izers within th e folder selected in t he Core Brow serNavigation Panel. In the Core Browser Con tents Panel you can select a core to customize it,

view its data sh eet, or view version information for it.

For a comp lete description of the Cores Cata log Browser, see Using the Cores Catalog

Browser in Chapter 3 an d Configuring th e Cores Catalog Browser in Chap ter 3.

Generated Modules Window

The Generated Modu les wind ow displays the Component N ame, Core Name, Version,

Family, Vend or and date gen erated of each core generated.

Figure 2-5: Cores Catalog Browser

Figure 2-6: Generated Modules Window


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Using the InterfaceR

Console Window

The Console Wind ow displays command s and responses. All error m essages, warnings,

and comm and responses are written to th e Console Window.

Use the scroll bar located to the right of the console wind ow to view a ll the comm and s and

responses recorded d uring an editing session. The Console Window can be resized to show

more lines of messaging at on ce. Move your m ouse anyw here on the u pp er border of this

wind ow u ntil the cursor turns into a tw o-headed arrow, then resize the wind ow as d esired.

Using Dialog Boxes

Many men u comman ds d isplay dialog boxes in wh ich you can enter information and set

options.

Using Common Fields

The fields show n in the following table are common to most d ialog boxes.

Browse Buttons

Many d ialog boxes contain browse buttons to allow you to navigate through you rdirectory structure to find a particular file or to save a file to a specific location.

Figure 2-7: Console Window

Table 2-2: Common Dialog Box Fields

Dialog Box Field Function

OK Closes the d ialog box and implements the intend ed action

according to the settings in the d ialog box.

Dismiss Dismisses the core customization d ialog when you are finished

customizing cores with that GUI.

Apply Implements the intended action.

Cancel Closes the dialog box.

Select Displays va rious Target architectures.

Set Displays True, False, Default option for the O verw rite Files

category.

Reset Chan ges all settings back to their default values.


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The following section d etails additional online docum entation resources and how to access

the information.

Links to the IP Center are available from th e CORE Generator Help Menu with the

following path:

HelpHelp on the WebIP Center

Other op tions available from the Help on the Web menu are links to these locations:

The CORE Generator Examp les web page

Xilinx Support and Services

The main Xilinx corporate w eb page at w ww.xilinx.com


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Additional ResourcesR

Accessing Core Data Sheets

To view th e data sheet for a core:

1. Select a core by clicking the nam e of the core in the Core Browser Contents Panel.

2. Select CoreData Sheet or click the Data Sheet button on th e standard toolbar.

The Acrobat Reader d isplays the data sheet.

You can also access a d ata sheet by right clicking a core in the Core Browser Con tentsPanel. Data sheets can be viewed for any core listed in the Core Browser Contents Pan el

wh ether they are grayed out or n ot.

Figure 2-8: CORE Generator Data Sheet


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R

Chapter 3

Using the CORE Generat or

This chapter explains the major functions a designer performs when using the CORE

Generator. The chap ter contains the following sections:

Using the Cores Catalog Browser

Using the Generated Modu les Window

Accessing N ew and Upd ated Cores

Working With Licensed Cores

Creating a N ew Project

Op ening an Existing Project

Changing Project Options

Creating a Customized Core

Recustomizing a Core

Regenerating a Core

Selecting Target XILINX FPGA Family Options

Using th e Web Browser a nd the PDF Viewer

Setting Preferences

CORE Generator Data Sheets Accessing Cores

Configuring the Cores Catalog Browser

Copying a Project

Input and Outp ut Files

Using Core Customization GUIs

Generating Cores in Batch Mode

Performing CORE Generator Opera tions in Xilinx ISE

Integrating CORE Generator into Ap plications

ASY and XSF Symbol Inform ation Files

Using the Cores Catalog Browser

The Cores Catalog Browser is located in the upp er pan el of the CORE Generator main GU I.

Cores that fall into pa rticular fun ctional categories are grouped into folders in the Cores

Catalog Browser to assist you in locating the core approp riate to your needs. The left hand

pan el of the Cores Catalog Browser, the Core Browser N avigation Pan el, allows you to

browse th rough these folders. To select a folder, click once on the folder nam e in the Core


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Chapter 3: Using the CORE GeneratorR

Browser N avigation Pan el. To expand a folder, doub le-click the folder icon to the left of the

folder nam e. To close a folder, dou ble-click th e open folder icon. Some folders h ave a + icon

or a icon to th eir left. The + indicates the folder has su bfolders that are not disp layed, and

the - indicates the subfolders are d isplayed. You can open or close the folder w ith a single

click on those icons.

The cores in the selected folder d isplay in the right hand pan el of the Cores Catalog

Browser, the Core Browser Contents Panel. Within a folder, cores are listed alphabetically

by nam e and also have type, version, family and vendor information d isplayed in

columns.

Core status information is displayed in the far right column, an d m ay includ e one of the

following icons:

Some cores in the Core Browser Con tents Panel may be grayed ou t. This means that these

cores are not av ailable for the curren tly selected Xilinx FPGA family.

Figure 3-1: Cores Catalog Browser

Icon Meaning

Core is schedu led to be obsoleted.

If you d ont want to view the cores wh ich are schedu led to be obsoleted,

a global p reference (Display obsolete cores) allows you to selectwhether th ese cores are displayed or not (see Setting Preferences).

Core requires an ad ditional license before it can be used .

Figure 3-2: Example of Cores Catalog with Obsoleted Cores


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Using the Generated Modules WindowR

Sorting the Catalog

You can sort th e cores in the Cores Brow ser Nav igation Panel in a nu mber of d ifferent ways

by setting the View Catalog setting at the top of the Cores Catalog Browser. Cores may be

listed by Function, Alphabetically, by Vend or (IP prov ider), by Fam ily or by Type

(LogiCORE or Reference Design).

Adjusting Columns and Panels

The size of each colum n w ithin the Cores Catalog Browser can be adjusted by moving the

separator s between the colum n head ings. Panels can be resized in a similar way.

A panel will have a vertical or hor izontal scroll bar (or both) to allow na vigation if the

information displayed in the panel is larger than the current panel size.

Using the Generated Modules Window

Cores that have been generated in a project are displayed directly und er the Cores Catalog

Browser in the Gener ated Mod ules wind ow. When you d ouble click a core in this panel,

you can p erform either of these functions: Recustomize Allows you to call up a previously genera ted core with the original

param eters used to generate it, then mod ify these parameters and generate a new

version of the core. You can recustomize und er the original p roject settings or u nd er

the cu rrent project settings. See Recustom izing a Core.

Regenerate Allows you to regenerate a core to create a different set of outpu tprod ucts. You can regenerate u nd er the original project settings or und er the current

project settings. See Regenerating a Core.

Accessing New and Updated Cores

Up to d ate information on the full range of Xilinx IP Solut ions is available on th e Xilinx IP

Center page at http :/ / w ww.xilinx.com/ ipcenter.

On the IP Center page you can find information on th e latest general release IP up da tes

from Xilinx (dow nloadable free of charge), as well as information on more comp lex system

level IP wh ich you can evaluate and pu rchase. Also available are links to Reference Design

resources and third p arty consultants.

The IP Center web page is updat ed on a regu lar basis, so be sure to review it before starting

a new design to m ake sure you are aw are of the latest IP offerings available from Xilinx.
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Figure 3-3 shows h ow you can access the IP Center page directly from the H elp menu in

the CORE Generator GUI.

Installing New Cores

When you down load new cores and new versions of existing cores from the IP Center, theyare installed in the CORE Generators built-in IP repository hierarchy but are n ot visible to

existing p rojects. This capability exists to insu late existing p rojects from up da tes to th e

cores used in that p roject. Any chan ges in the functionality associated w ith new cores does

not imp act existing p rojects since new cores are not autom atically up dated for existing

projects. The m ultiple version supp ort capability exists to allow a new core or new version

of an existing core to be mad e available in an existing p roject.

The d irect link to new Xilinx stand ard release cores and their installation instru ctions is

available on th e Xilinx w ebsite at th is location:

http:/ / www.xilinx.com/ ipcenter/ coregen/ updates.htm.

After new cores have been add ed to you r CORE Generator IP repository and a project is

opened, a d ialog box appears, asking wh ether you wish to u pd ate your p rojects list of

visible cores (see Figure 3-6). You may choose:

All

Only th e latest version of all cores will be visible in th e Cores Catalog d isplay.

New

The latest version of all new cores will be visible in the Cores Cata log disp lay.

Custom

Allows you to customize w hich cores are mad e visible in the Cores Catalog display.

None

None of the new cores will be visible in the Cores Catalog d isplay.

Figure 3-3: Navigating to the Xilinx IP Center from the CORE Generator Window
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Working With Licensed CoresR

Working With Licensed Cores

In the 6.1i release, CORE Generator LogiCORE cores w hich requ ire an ad ditional

license may be includ ed in the release CD, or add ed via subsequ ent IP Upd ates. There are

two types of licenses that may be requ ired for these types of cores:

Full System Hardware Evaluation licenses

Full Release IP licenses

Full System H ardw are Evaluation licenses are offered on som e of the higher com plexity,

system level cores. This license enables you to perform a Full System H ardware Evaluation

of the core. A core which sup ports Full System H ardware Evaluation allow s you to:

Integrate the core into the rest of you r design

Process the d esign throu gh m ap, place and route

Generate a bitstream

Program the design into you r target Xilinx FPGA

Perform timing simu lation and static timing an alysis

Review all documentation found in the full product offering

If you gen erate a bitstream and th en progr am an FPGA using a core that has a Full System

Evaluation license, the core will stop w orking in the p rogram med dev ice after 2-8 hou rs,

depend ing on the core. To get the device working again you m ust reload the bitstream,

reprogramming th e device.

Full Release IP licenses allow you to access the full functionality of the official released

version of a licensed core.

In the CORE Generator, if you d oub le click on a core in the Cores Catalog Browser that

requires a license for evaluation or full functionality, a m essage box for th is core will

indicate that you can on ly generate functional models for the core, unless you obtain an

add itional license.

Licenses for evaluation and full fun ctionality access can be requ ested from the p rodu ct

lounge for the core on Xilinxs IP Center w eb page at th is location:

http :/ / w ww.xilinx.com/ ip center

To obtain a license you w ill typically need to register for the loun ge and fill out an on line

request form. For full release core licenses you will also need to p rovide a serial nu mber.

Consu lt the respective prod uct lounge in the IP Center for specific instru ctions, and follow

the instructions for installing the license. Once you h ave done this, you should be able to

use the core in either evaluation or full release mod e.

Creating a New Project

This section describes how to create a new project. When a new project is created th e cores

displayed in the CORE Generator Systems main w indow are the latest versions of thecores.

To create a new project in CORE Generator:

1. Select FileNew Project or click the New Project toolbar bu tton.
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The New Project dialog box app ears, as show n in the following figure.

2. In the New Project dialog box, type the path to the new project directory in theDirectory text field

OR

Click t he Browse but ton and nav igate to the project directory.

3. Select you r project options as directed in Changing Project Options.

Note: You cannot create a new CORE Generator project targeted to an ISE flow. If you select

ISE in the New Project dialog box, you will receive an error message directing you to create a

new project within ISE instead of within the CORE Generator.

4. ClickOK.

The Xilinx CORE Generator System initializes the n ew project. This initialization m ay

take several seconds. A coregen.prj file is written to th e new project d irectory. The

coregen.prj file contains a record of all installed cores at the time th e project w as

created and their latest versions.

5. Set the rest of your project options as directed in Changing Project Options.

Figure 3-4: New Project Dialog Box


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Opening an Existing ProjectR

Opening an Existing Project

To open an existing project from w ithin CORE Generator:

1. Select FileOpen Project or click the Open toolbar button .

The Open project box displays.

2. In the Op en Project dialog box, select a project from the Recent Projects list in the

dialog box

OR

Click t he Browse but ton and nav igate to the project directory.

You m ay also place a check mark in t he Always Open Last Project check box in the

following figur e. If you select this box, the CORE Generator System byp asses the Op en

Project dialog box at startup , and open s the last open p roject. If you deselect the Always

Open Last Project check box, CORE Generator prom pts you for a project at startup by

disp laying the Open Project dialog box.

3. ClickOK.

If the p roject has been locked by anoth er user, the CORE Generator g ives you the

option of Closing th e project, displaying More Info about th e project lock, or Removing

the lock. Displaying More Info gives you m ore informa tion on who has locked the

project and also gives you the op tion of removing the lock.

If new IP have been ad ded to the CORE Generator repository since you last accessedthe p roject, the following d ialog box appears.

Figure 3-5: Open Project Box


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The dialog box p resents options for u pd ating the list of visible cores in the CORES

Catalog for the p roject. The selections in th is dialog box are d escribed in Installing

New Cores.

Changing Project OptionsTo chan ge Project Options:

1. For an existing project, select ProjectProject Options. This opens the Project Options

dialog box for the project.

For a new project, a similar dialog box displays. The d ialog box is titled New Project,

and has an add itional field at the top allowing you to specify the p roject location.

2. Und er the Outp ut Options panel, select either the Flow Vendor or Output Products

view. The Flow Vend or view allows you to specify your Design Entry flow (Schem atic,

VHDL, or Verilog) and Design Entry vendor, and then determines the appropriate

output products for the cores you generate automatically.

The Outpu t Produ cts view is for more advan ced users. This view allows you to

explicitly specify the outp ut p roducts you w ish to be generated for each core you

create.

3. Mod ify the project options in the Project Op tions dialog box.

Project options for the Flow Vend or view are described in Output Op tions

Flow Vend or.

Project options for the Ou tput Prod ucts view are described in Output Options

Output Products.

4. When you hav e finished mod ifying the project options, clickOK.

Note: Changing the project options only affects new cores that you generate. Cores created

before making the project changes still reflect the old options. Regenerate any cores that need

to inherit the new project options.

Figure 3-6: Project Update Dialog Box


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Changing Project OptionsR

Output Options Flow Vendor

After you h ave selected th e Flow Vend or view, you can then set the Target Architecture,

Overw rite Files option, the Design Entry flow and Design Entry vend or.

Target Architecture

Select you r target architecture from th is list:

Figure 3-7: Project Options Flow Vendor

Table 3-1: Target Architecture

Design Specification

Virtex Virtex, VirtexE

Spartan2 Spartan2, Spartan2E

Virtex2 Virtex2

Vir tex2P Vir tex2P

Sp artan 3 Sp artan 3


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Overwrite Files

You can select these options for Overw rite Files:

True

Any p re-existing files associated w ith a previou sly generated core are overw ritten by

default with no w arning wh en a new core of the same name is generated.

False

The CORE Generator prom pts you for app roval before overw riting existing files.

Default

The Overw rite Files behavior follows the g lobal preference setting specified for all

projects as set in Preference Op tions d ialog box (accessed by selecting FilePreferences).

Design Entry

Specify your Electronic Design Automation (EDA) flow (Schematic, VHDL or Verilog)

and d esign entry vendor.

If you choose Schematic as the design flow, the following outp uts are generateddepend ing on your chosen vendor:

Cadence

The CORE Generator p rodu ces a Cadence compa tible EDN file.

ISE

The CORE Generator p rod uces an ASCII symbol (ASY) file, an ECS symbol (SYM) file

(for the Xilinx ECS schem atic editor), and th e un derlying EDN n etlist.

Innoveda

When ru n stand alone, the CORE Generator does not generate any schematic outpu t if

you select Innoveda, however it does create an eProdu ct compa tible EDN file. When

the CORE Generator is invoked th rough the Xilinx/ Innoved a interface (ePDCore),ePDCore au tomatically creates a .1 symbol file, which can be instantiated in a

Viewd raw schematic sheet. For more details on the Innoved a Xilinx flow, see

Answer Record #11683 at the Xilinx Answ ers Searchweb page.

Mentor Graphics (Schematic)

The CORE Generator p rodu ces an XSF file to support sym bol generation within th e

Mentor Design Architect environmen t, and a M entor comp atible EDN netlist.

Other

The CORE Generator p rodu ces an EDN netlist, with th e Netlist Bus Forma t you

specify.

When you choose VHDL as the design flow, a VHO instan tiation template file and a VHDwr app er file are created. The VHO tem plate file contains comm ented H DL examp le codethat can be used to instantiate a CORE Generator mod ule in an H DL design. The VHD

wr app er file is used to sup por t functional simulation of the core. Similarly if you choose

Verilog as the d esign flow, a VEO instan tiation temp late file and V wrap per file arecreated.

Note: If you select any vendor except Other, the CORE Generator automatically sets the Netlist

Bus Format setting in the output EDIF file to the correct value for that vendor. If you set the Design

Entry vendor to Other, you will also need to specify the Netlist Bus Format.
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Netlist Bus Format

Sets the format in which bus signals are written in the ou tpu t EDIF file. If you select Other

as your d esign entry vend or, you w ill have to set a Netlist Bus Format.

Bus form at can be specified (and will be written into th e EDIF file) in either of these ways:

As individual bus bits. For these options, B represents the nam e of the bus and I

represents the bus ind ex. Opt ions are B, B(I), B[I], and BI.

As a single array. For these options, B represents the name of the bu s and n:m

represent t he ran ge of the bu s index. Options are B, B(n:m), and B[n:m].

Design Flows Supported by the CORE Generator

The following table lists the design flows suppor ted by the CORE Generator on a ven dor

by vend or basis.

Table 3-2: Design Entry Vendors and Design Entry Flow Options

Schematic VHDL Verilog

Cadence X XInnoveda X X X

ISE X X X

Mentor Graphics (HDL) X X

Mentor Graphics (Schematic) X

Synopsys X X

Synplicity X X

Other X X X


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Output Options Output Products

The Outpu t Produ cts option in the Project Options dialog is geared toward the more

adv anced u ser. In ad dition to allowing you to select your target architecture and File

Overwrite options, it allows you to choose the exact outpu t prod ucts you n eed m ore

precisely. It also supp orts some ad ditional features such as formal verification ou tpu ts and

three special elaboration op tions.

Target Architecture

Select you r target architecture from th is list:

Figure 3-8: Project Options Output Products

Table 3-3: Target Architecture

Design Specification

Vir tex Vir tex, Vir texE

Spartan2 Spartan2, Spartan2E

Virtex2 Virtex2

Vir tex2P Vir tex2P

Sp artan 3 Sp artan 3


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Overwrite Files

You can select these options for Overw rite Files:

True

Any p re-existing files associated w ith a previou sly generated core are overw ritten by

default with no w arning wh en a new core of the same name is generated.

False

The CORE Generator p romp ts you for approval before overw riting existing files.

Default

The Overw rite Files behavior follows the g lobal preference setting specified for all

projects as set in Preference Op tions d ialog box (accessed by selecting FilePreferences).

Output Products

When you select the Outp ut Prod ucts view of the Project Options dialog, you can choose

from the following selections from the Output Products panel:

ASY Symbol File

An ASCII symbol information file used by the ISE tools and some th ird party interface

tools to create a sym bol representing th e core.

VHDL Simulation Model

Generates files for simulating a generated core in a VHD L simu lation environmen t.

Verilog Simulation Model

Generates files for simu lating a genera ted core in a Verilog simulation environm ent.

XSF

Symbol information file for Mentor.

Block RAM Memory Map File (.bmm)This option, wh ich ap plies to Block Memory cores, is cur rently d isabled and cannot

prod uce any BMM outpu t files. This feature m ay be enabled in a fu ture 6.1i IP up date.

EDIF implemen tation files are always gen erated by defau lt. For some cores, NGC files are

also generated.

The right han d p anel of the Outp ut Prod ucts dialog view lists these sup ported vend ors:

Cadence

Mentor Graphics (HDL)

Mentor Graphics (Schematic)

ISE

Innoveda

Synopsys

Synplicity

Other

Note: If you select any vendor except Other, the CORE Generator automatically sets the Netlist

Bus Format setting in the output EDIF file to the correct value for that vendor. If you set the Design

Entry vendor to Other, you will also need to specify the Netlist Bus Format (see Netlist Bus Format).


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Formal Verification

There are three options to choose.

Formality

Generates a Verilog model called _for.v to sup por t formal

verification using the Form ality tool from Synopsys.

Verplex

Generates a Verilog mod el called _for.v to sup port formal verification

using the Tuxedo-LEC Logic Equivalence Checker tool from Verplex.

None

No files are generated to sup por t formal verification.

Elaboration Options

There are three options to choose.

Generate netlist wrapper with IO pads

This option adds inpu t pad s and outp ut p ads to a core when the CORE Generatorgenerates the core and w rites out its EDIF imp lementation n etlist. Use this file if you

wan t to process the core standalone all the w ay through place and route to get p recise

timing and resou rce utilization information. You can d o this withou t having to

interface to any d esign entry tool.

IfGenerate netlist wrapper with IO pads is selected, the Core Gen erator creates anadditional file, a padd ed EDIF wrap per file. The pad ded EDIF file contains a

declaration of the core as a black box, with th e ports connected to app ropr iate

Input/ Ou pu t blocks.

For a core nam ed corename the EDIF describing the core is generated as usu al in a file

named corename.edn . The add itional file generated w hen Generate netlist wrapperwith IO pads is selected is nam ed corename_padd ed.edn. The mod ule defined in the

file is named corename_padded.

The corename_pad ded definition includ es a black box instantiation of the core,

according to the d efinition in corename.edn. Each strand of each port on th e core is

connected to an app ropr iate Input / Ou tpu t Block (IOB). Each IOB is connected to th e

corresponding p ort strand on the corename_padded modu le.

IOBs are add ed according to these ru les:

The IOB type connected to a port is shown in the following table:

Table 3-4: Port Connections for Generate netlist wrapper with IO pads Option

Port Type IOB(s)

Output OBUFInput Clock (Virtex derivatives) IBUFG connected to a BUFG

Inpu t Clock (a ll other families) BUFG

All other Input Ports IBUF

Bidirectional IOBUF


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A clock po rt is assumed if a por t is named clk or g, or starts or end s with clk or

_ck.

IPADs and OPADs are notadded.

The following figure gives an example of the pad ded file generated for a Virtex core.

Pad ded files are generated for EDIF outp ut on ly; they are not genera ted for VHDL and

Verilog outpu t.

Remove Placement Attributes

When selected, this option rem oves any RLOC and H U_SET attributes embedd ed in a

pa rameterized core before writing out its EDIF netlist.

The only EDIF netlists affected by this option are those tha t are generated bypa rameterized CORE Generator cores. EDIF netlists for fixed netlist cores are not

affected by th is option.

Note that this option does n ot determine w hether RLOCs and HU_SETs are generated

wh en a core is elaborated . The Remove Placemen t Attributes op tion simply p revents

RLOC an d H U_SET values from being outp ut to the EDIF netlist for a core by

removing them if they are present.

Some IP custom ization GUIs have a Create RPMs checkbox, which allows you toenable or d isable the creation of RLOCs and HU _SETs in the core you a re configu ring.

If the Remove Placement Attributes option is set, it overrides the Create RPMs

check box, and RLOC and HU _SET constrain ts will not ap pear in the EDIF netlists of

the cores for wh ich Create RPMs was enabled.

Create NDF Synthesis Optimization Interface for NGC cores

In pr ior releases of the ISE software, CORE Generator created a single

Documents

core generator guide