Copyright 2015 Tam LASIC

8/18/2019 Copyright 2015 Tam LASIC

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1278 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 34, NO. 8, AUGUST 2015

LASIC: Layout Analysis for Systematic IC-DefectIdentication Using Clustering

Wing Chiu (Jason) Tam, Student Member, IEEE, and Ronald D. (Shawn) Blanton, Fellow, IEEE

Abstract —Systematic defects within integrated circuits (ICs)are a signicant source of failures in nanoscale technologies.Identication of systematic defects is therefore very importantfor yield improvement. This paper discusses a diagnosis-drivensystematic defect identication methodology that we call layoutanalysis for systematic IC-defect identication using cluster-ing (LASIC). By clustering images of the layout locations thatcorrespond to diagnosed sites for a statistically large numberof IC failures, LASIC uncovers the common layout features. Toreduce computation time, only the dominant coefcients of a dis-crete cosine transform analysis of the layout images are usedfor clustering. LASIC is applied to an industrial chip and it isfound to be effective. In addition, detailed simulations reveal that

LASIC is both accurate and effective. Index Terms —Clustering, layout analysis, systematic defects,

test data mining, yield learning.

I. INTRODUCTION

D EFECTS caused by random contaminants were the mainyield detractor in integrated circuit (IC) manufacturingbefore the nanoscale era [ 1]. However, as CMOS technologycontinues to scale, the process complexity increases tremen-dously, which results in design-process interactions that aredifcult to predict and control. This, in turn, translates intoan increased likelihood of failure for certain layout featuresthat are sensitive to particular process corners. Unlike randomcontaminations, the defects that result from design-processinteractions are systematic in nature, i.e., they can lead toan increase in likelihood of failure in locations with simi-lar layout geometries (note that it does not mean that theymust lead to a drastic yield loss). Since a product IC typi-cally contains a diverse set of layout features, it is difcultto use test structures to completely characterize the design-process interactions because of their limited volume [ 1], [2].In other words, conventional test structures, while still veryuseful in characterizing the process and understanding defects,have somewhat diminished in applicability [ 1], [2].

To address these issues, volume diagnosis is increas-ingly deployed to improve/supplement yield-learning [ 3]–[14].

Manuscript received May 29, 2014; revised November 10, 2014; acceptedJanuary 16, 2015. Date of publication February 24, 2015; date of currentversion July 24, 2015. This work was supported by the SemiconductorResearch Corporation under Contract 1644.001. This paper was presented atthe International Test Conference [ 3] in 2010. This paper was recommendedby Associate Editor L.-C. Wang.

At the time this research was conducted, the authors were with theAdvanced Test Chip Laboratory, Electrical and Computer EngineeringDepartment, Carnegie Mellon University, Pittsburgh, PA 15213-3890 USA(e-mail: [email protected] ).

Color versions of one or more of the gures in this paper are availableonline at http://ieeexplore .ieee .org .

Digital Object Identier 10.1109/TCAD.2015.2406854

Volume diagnosis refers to the process of performing software-based diagnoses of a large amount of IC test fail data,which is further analyzed for a variety of purposes. Forexample, on-going diagnoses are used to identify systematicdefects [ 3]–[7] and derive design-feature failure rates [ 8], [9].In [10] and [11 ], the effectiveness of design for manufactura-bility (DFM) is evaluated using volume diagnosis results.Diagnosis is also used as a part of a yield-monitoringvehicle for estimating defect density and size distribu-tions (DDSDs) [ 12]. In [13]–[15], diagnosis is used to monitorand control IC quality. Finally, in [ 16], volume-diagnosis

is a key part of a methodology for evaluating test met-rics and fault models without performing conventional testexperiments.

Yield learning based on volume diagnosis has several advan-tages. First, since no manufacturing process is perfect, defectsinevitably occur. Therefore, test must be applied to the manu-factured ICs to screen out failures to ensure that bad parts donot escape to customers. The fail data generated by test canbe directly used in software-based diagnosis. In other words,an abundant amount of fail data is continuously being gen-erated. Thus, no additional effort is required to generate thefail data, and intrusion into the fabrication and test processis minimized. Second, unlike test structures, software-based

diagnosis consumes only CPU cycles and therefore does notconsume extra silicon real estate. The cost to perform vol-ume diagnosis is therefore comparatively lower. Third, volumediagnosis is performed on the actual product ICs, which con-tain the diverse geometries that may render conventional teststructures inadequate. Thus, using volume diagnosis can com-plement existing yield-learning techniques to help improveyield even further.

This paper is a step in this direction. Specically, thispaper attempts to identify systematic defects for yield improve-ment using volume diagnosis. By clustering layout imagesof diagnosis-implicated regions, layout-feature commonali-ties (if any) that underlie the failures are identied. Features

present in large clusters can then be analyzed further toconrm the existence of a systematic issue, or alternativelyphysical failure analysis (PFA) can be performed on oneor more of the actual failing chips that have the failingfeature. The methodology developed in this paper is calledlayout analysis for systematic IC-defect identication usingclustering (LASIC).

A. Prior Work

Because of the potential yield benets that can be derivedfrom systematic defect identication, a tremendous amount

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TAM AND BLANTON: LASIC 1279

of research effort has focused on this area. This is evi-dent in several recently published papers on this topic.Turakhia et al. [4] analyze design layout to identify locationsthat marginally pass the DFM constraints. The resulting layoutlocations are used as starting points for identifying sys-tematic issues. References [ 8] and [17] compute expectedfailure rates for layout features that are assumed to be dif-cult to manufacture. This information is combined withvolume diagnosis data to identify outliers (i.e., system-atic defects). Jahangiri and Abercrombie [ 18] used critical-area analysis [ 19] to compute the expected failure rate foreach net. The presence of systematic issues is investigatedby comparing the observed failure rates with those pre-dicted by critical-area analysis. Huisman et al . [5] appliedclustering techniques to test-response data collected froma large number of failing ICs to identify common failuresignatures, which may indicate the presence of systematicissues. References [ 20] and [21] performed extensive lithog-raphy simulation on the entire layout to identify hotspots.Layout snippets 1 containing these hotspots are extractedand clustered with the goal of formulating DFM rules.References [ 22] and [23] extracted layout features (such asthe number of vertices in a polygon, minimum-line width, andspacing, etc.) of suspect defect locations identied by bright-eld inspection. These locations are clustered based on thefeatures for characterizing each location. The resulting clus-ters are then used to eliminate suspect locations that are likelynot to result in a killer defect to better direct scanning electronmicroscope (SEM) review.

B. Our Contribution

Undeniably, all of the aforementioned work has a cer-tain degree of success in systematic defect identication, as

evidenced by their experiment results. Nonetheless, manyof the past approaches [ 4], [5], [8], [17], [18] fall short of automatically extracting similar layout features that may bea signicant source of yield loss. In addition, the approach thatuses critical area [ 19] requires a full-chip analysis, which istime-consuming to achieve. The approach in [ 5] used cluster-ing but at a high level of abstraction by analyzing scan-basedtest responses. Clustering failed ICs into groups based on testresponses provides a very useful starting point for identify-ing systematics that are location-based but this alone may notpinpoint the layout features that are potentially problematic.

LASIC attempts to address the aforementioned limi-tations by clustering portions of layout believed to be

the failing location. It should be clear, however, thatthe work yet-to-be-described complements the existingapproaches [ 4], [5], [8], [17], [18]. For example, suppose thecritical-area/DFM-based approaches of [ 4] and [18] are usedto identify nets with unexpectedly high failure rates. Layoutimages of these nets can be (automatically) extracted andclustered to identify commonalities. In addition, the layoutfeatures extracted using LASIC can be used as the inputsfor [8] and [17]. In fact, LASIC can be applied independently

1A layout “snippet” refers to a single region within a single layer of a design’s layout that can be easily described by two x - y coordinates thatindicate the upper-right and lower-left corners, respectively.

or used as a post-processing step for any systematic-defectidentication method whose output is a set of candidates thatare suspected to be the locations of systematic defects.

References [ 20] and [21] resemble LASIC but there areseveral important differences. First, [ 20] and [21] rely on sim-ulation, which can be inaccurate and too conservative, i.e.,it is likely to identify features that may never cause an ICto fail. Fixing most (if not all) of the hotspots might resultin over-correction which can adversely affect chip area andperformance. Relying on simulation alone also means thatsystematic defects that have failing mechanisms that are notmodeled will be missed. In contrast, LASIC uses diagnosis-implicated layout locations that are generated by diagnosingactual IC failures, and therefore does not suffer from these lim-itations. In addition, [ 20] and [21] require the entire designto be simulated. This limits the scalability of the method-ology, especially when many different process corners areconsidered. LASIC, on the other hand, may apply processsimulation (which is not required) to very small portions of the design for validation purposes only. Since only smallportions of the design are analyzed, a comprehensive andaccurate analysis (e.g., Monte Carlo analysis across processcorners) can be easily afforded. Most importantly, LASIC hasthe capability to provide failure rates for problematic lay-out features. In contrast, the identication of layout hotspotsvia process simulation (which likely does not account forresolution enhancement techniques, dummy ll, etc.) doesnot quantify the likelihood of a hotspot actually leading tofailure.

References [ 22] and [23] also closely resembled LASICbut again there are several subtle but important differences.First, LASIC analyzes layout images while the approachin [22] and [23] extracts user-dened layout features. In otherwords, LASIC makes no assumption on the importance of certain layout features but instead automatically discovers theimportant layout features. Second, analyzing layout snippetsas images has the added advantage that features from multi-ple layers can be easily represented in a single image. Third,a vast number of image processing techniques are immedi-ately available for analysis of layout. Finally, [ 22] and [23]use bright-eld inspection to nd potential defect locations,but these locations have not yet been shown to cause failure,which results in another source of uncertainty. LASIC insteaduses diagnosis-implicated regions that are generated by diag-nosing actual ICs that are known to have failed. However,because diagnosis is not perfect, LASIC too will also have todeal with some level of uncertainty.

The rest of this paper is organized as follows. Section IIdescribes the details of LASIC. This is followed by a siliconexperiment involving an industrial design and a simulationexperiment involving eight benchmarks [ 24], [25] presentedin Section III. Finally, the conclusions are presented inSection IV.

I I . S YSTEMATIC D EFECT IDENTIFICATION

In this section, the details of LASIC are described. We beginby giving an overview, which is then followed by detaileddescriptions of each step in LASIC.


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A. Overview

LASIC consists of four steps: 1) volume diagnosis;2) layout snippet extraction; 3) snippet clustering; and4) validation. Volume diagnosis is simply applying diagnosisto a sufciently-large number of IC failures. The outcome of diagnosis is a set of candidates, where each candidate consistsof the suspect net or cell where the defect is believed to reside.A layout region (i.e., a region involving one or more layers inthe layout that contains the features of interest, for example,a net and its surrounding nets) is extracted for each candidate.LASIC then partitions the extracted layout region into one ormore layout snippets, each of which is saved as an image.Clustering, such as K -means [ 26], is then applied to groupsimilar snippet images together to identify any commonalities.Finally, the identied layout feature is simulated using a pro-cess simulator (such as the lithography tool Optissimo [ 27])to conrm the existence of a systematic defect. As mentionedearlier, validation could take on other forms such as PFA.

B. Diagnosis

Our goal is to identify yield-limiting layout features. Onepossible approach is to grid the entire layout into many smallregions (i.e., layout snippets) and then perform clustering onthe resulting snippet images. The result of clustering can thenbe overlaid with volume-diagnosis data to identify any system-atic issues. This approach is possible but inefcient since manylayout features will be easily manufacturable. In other words,for the aforementioned approach, computational resources arespent on clustering a large number of “healthy” snippets,which is not the focus here. 2 Therefore, to narrow down thescope of investigation and to save computing resources, clus-tering is limited to the layout regions implicated by diagnosisof failed ICs since these regions are likely to contain anysystematic defects that may exist.

A variety of diagnosis approaches have been proposed(see [ 28]–[33]) and the question considered here is which oneis the most suitable for LASIC. A diagnosis approach thatcan exactly pinpoint the x - y- z location of the defect would beideal. However, this requirement is unrealistic because diag-nosis is not perfect and a diagnosis outcome typically consistsof multiple candidate locations. Diagnostic resolution [ 34] isa measure of the effectiveness of a diagnosis methodologyto logically localize the fault. A higher diagnostic resolutionis desired since there is less uncertainty concerning the fail-ure location. Diagnostic resolution is often used as a metricfor comparing different techniques and evaluating the merit of a particular diagnostic approach.

The diagnosis approach adopted here is calledDIAGNOSIX [ 29] since it uses a layout-based approachthat can distinguish logically-equivalent faults, leading to animproved diagnostic resolution. High diagnostic resolutionequates to fewer snippets used for the clustering step,resulting in a higher condence. It should be emphasized,however, that other diagnosis techniques can and have beenused instead of DIAGNOSIX.

2 Identication of easy-to-manufacture features, however, may be useful forforming a set of allowable patterns for DFM objectives.

Fig. 1. Flow diagram of the Carnegie Mellon layout analysis tool (LAT).

C. Layout Snippet Creation

An in-house layout analysis tool (LAT) is used to extractlayout snippets of diagnosis-implicated regions [ 35]. LATmakes use of three open-source C++ libraries, namely, the

OpenAccess library (OA) [ 36], the computational geometryalgorithm library (CGAL) [ 37], and the Cairo library [ 38]. TheOA library performs design-format conversion and provideshigh-performance database operations. The CGAL library con-tains geometric algorithms suitable for layout analysis. TheCairo library is used for image rendering and generation.Fig. 1 illustrates the ow implemented by LAT. Each can-didate reported by diagnosis is retrieved from an annotatedlayout database to nd its layout geometries, which are furtherprocessed to create snippet images.

1) Database Preparation: Since the typical descriptionof a design layout is graphic data system (GDS) [ 39], theGDS-to-OA translator provided in the OA package is used to

convert GDS to the format of the OA database. In addition,since GDS typically consists of purely geometric information,the resulting OA database will not contain any logical con-nectivity information, or any net, or cell names. Thus, theconverted database is further processed to add this informa-tion. This is a one-time task whose cost is amortized overrepeated use of the annotated OA database to extract snippetimages for each chip failure of interest.

2) Candidate Geometry Processing: The input to LAT isa set of candidates that have been identied by diagnosinga failed IC. Since the database has been annotated with con-nectivity information, the polygons associated with a givencandidate can be easily accessed. Clearly, different candidatesconsist of different polygons that reside in various layers,thus making their comparison nontrivial. Fig. 2 illustrates thisdiversity. Fig. 2(a) shows a net that is relatively long thatspans two layers (highlighted with a dashed boundary), whileFig. 2(b) shows a short net that resides in only one layer. If only a single snippet image is extracted for each net, thenthey would either have a very different scale (with a xedimage dimension) or have a very different image dimension(with a xed scale). In either case, it is difcult to directlycompare these two nets. Although nets are used as exampleshere, the argument also applies to other types of diagnosiscandidates, such as a cell defect.


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Fig. 2. Diagnosis-implicated layout region for (a) long net that spans twolayers and (b) a short net that spans only one layer. Both nets of interest areidentied with a dashed boundary.

Fig. 3. Snippets of a net polygon with (a) vertical alignment and(b) horizontal alignment.

To overcome this challenge, the layout region implicatedby a candidate is split into smaller regions of xed scale anddimension that are called layout snippets. This standardizes thescale and the dimension of the layout regions for easy com-parison. Unfortunately, snippet alignment remains an issue, asillustrated in Fig. 3. Alignment here refers to the proper choiceof the snippet-center location to facilitate snippet comparison.Fig. 3(a) shows three different snippets generated with dif-ferent vertical alignment while Fig. 3(b) shows three differentsnippets generated with different horizontal alignment. Clearly,all the snippets appear dissimilar, although the same polygonof interest (highlighted with a dashed boundary) is partiallycaptured by all. It is also clear that there are two degrees of freedom while aligning the snippets since a one-layer snippetis a 2-D object.

To address the snippet alignment issue, a snippet center isrequired to be on the center line of each polygon that belongsto the candidate. (The extraction of the polygon center linewill be described in detail in the next section.) For example,if the center line of a candidate polygon is a horizontal line,as shown in Fig. 3(a), then the snippet center is required tobe vertically aligned with this center line. The rationale foraligning in this manner stems from the fact that a systematicdefect is likely caused by layout features that are difcult tomanufacture. These features are dened by the polygons thatmake up the candidate as well as its neighboring polygons.Since we do not have prior knowledge of which polygons inthe neighborhood play a role in the systematic defect, it is bestto center the candidate polygons in the snippet and to ensurethat the radius of inuence is carefully chosen.

Requiring the snippet center to align with the center lineof a candidate polygon, however, only restricts one degree of freedom. The snippet center can be in an arbitrary position

Fig. 4. Illustration of splitting of (a) layout region into (b) layout snippets.

along the center line and therefore may still cause a mis-alignment issue. This is illustrated in Fig. 3(b). Specically,despite the vertical alignment of the snippet center with thehorizontal center line, horizontal misalignment of the snippetstill occurs. Thus, the snippet center is further restricted tospecic points on the center line of the candidate polygonas shown in Fig. 4. Again, the candidate polygon is high-lighted with a dashed boundary. The lines inside the polygonare the center lines. There are three types of locations that canserve as a snippet center: 1) endpoints (represented as dots) of the center line; 2) projection points (represented as triangles)from the center-line endpoints of the neighboring polygonsonto the center line of the candidate polygon; and 3) mid-points (represented as crosses) between the rst two types of points. (If there is no projection point, a midpoint will still becalculated between the endpoints of the candidate center line.)The rationale behind restricting the snippet center in this waystems from the fact that these locations dene a layout featureor a layout-feature interaction. Clearly, the endpoints denethe center line, which captures the topology of the routingpolygon. Projection points from neighboring polygons denethe interactions between the neighbors and the candidate. Themidpoints are of interest because they aid the capture of thelayout pattern between the rst two types of points. Here isanother interpretation of the rationale: if we imagine movingthe snippet center along the center line of a candidate poly-gon, starting at one of its endpoints, then the projection pointsdene changes in neighborhood (i.e., the entrance or exit of a neighboring polygon) and the midpoints dene the layoutpatterns before and after the neighborhood change.

3) Center Line Extraction: The image scale, dimension,and alignment requirements have motivated the use of the straight-skeleton algorithm [ 40] provided by the CGALlibrary. A straight skeleton of a polygon is dened as “theunion of the pieces of angular bisectors traced out by thepolygon vertices” when the polygon is being shrunk [ 40].Fig. 5(a) illustrates the straight skeleton (shown in dotted linesand built using the CGAL library) of a polygon. A vertexthat belongs to both the polygon and the straight skeleton iscalled a contour vertex, while a vertex that belongs only tothe straight skeleton is called a skeleton vertex. For LASIC,however, only the skeleton vertices are of interest since theyalone dene the center line of the polygon as illustrated inFig. 5(b). The skeleton vertices therefore form the endpointsof the center line.


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Fig. 5. Illustration of (a) a straight skeleton of a polygon and (b) the centerline of the same polygon.

Use of the straight-skeleton algorithm allows the center lineof a polygon to be extracted. Center lines are extracted for boththe candidate polygon and its neighboring polygons, as shownin Fig. 4. The center-line endpoints for the candidate polygonare immediately available after the center-line extraction (theyare in fact the skeleton vertices). The projection points canbe easily calculated once the center lines of the neighbors aredetermined. The midpoints can then be dynamically calculatedafter all the projection points are determined. If the extractedcenter line of the candidate polygon has multiple line segmentsas shown in Fig. 5, then each line segment will be processedseparately to extract the projection points and the midpoints.

4) Snippet Image Generation: The layout snippets aresaved as images using the Cairo library, which is an open-source graphics library that is widely used for image rendering.The Cairo library is platform-independent and is capable of producing an image in a variety of formats. C++ code usingthe OA library has also been written to support the GDS formatas well. For clustering, the portable network graphics imageformat is used. Once the yield-limiting layout features areidentied, the corresponding layout snippet can be saved inthe GDS format for further analysis (e.g., lithography simula-tion). It should be noted that the size of the layout snippet canbe easily adjusted to satisfy the requirements of the subsequentanalysis, if needed.

After the images are generated, the discrete cosine trans-form (DCT) [ 41] is performed on each image. Let A bea matrix of pixel values that represent a snippet image, B bethe coefcient matrix after the DCT, and D be the DCT matrix.Then, the image A can be written as A = D’BD . The advan-tage of using DCT representation lies in the fact that the dom-inant DCT coefcients are concentrated around the upper-leftcorner of B. In other words, the image matrix A can be approx-imated using only the dominant coefcients. This approxi-mation is a widely used technique in image processing; infact, it is the method used in the original JPEG standard [ 42].For LASIC, this approximation provides tremendous speed-upbecause only the dominant coefcients are kept for subse-quent analysis. For an image A that has 100-by-100 pixels,only ∼150 DCT coefcients are needed to ensure accu-racy for the analysis. Comparing with the original data sizeof a 10,000-pixel image (10 kilobytes), the approximation(150 bytes) has a reduction of 98.5%. It should be emphasizedthat DCT is not the only suitable transform, other transforms,such as the wavelet transform [ 43], can also be easily used.In fact, more general dimensionality reduction techniques(e.g., principal component analysis [ 44]) can be used as well.

D. Clustering

Clustering, a form of unsupervised learning [ 44], representsa class of data exploratory techniques that partitions objectsinto groups based on their similarity. Similar objects are ideallyput in the same cluster while dissimilar objects are placed indifferent clusters. The goal of clustering is to discover structurein the data by exploring similarity within the data. Employingclustering involves the following [ 45].

1) Representation of the object, which can involve featureextraction or selection.

2) A measure of similarity between objects.3) Selection and application of a clustering algorithm.Object representation is accomplished using the process

described in the previous section. More specically, the objectsto be clustered are center-aligned snippet images of xeddimension and scale, each of which is represented as a subsetof its DCT coefcients. There are a number of advantagesof using this type of representation. First, it allows directcomparison of snippet images (e.g., two images can becompared using their selected DCT coefcients). Second, itis easy to include geometries from different layers in thesame image by appropriately setting color transparency val-ues (also called the alpha channel) of the layers involved.This is important when the goal is to identify a system-atic defect caused by layout features that span multiplelayers (e.g., a bridge induced by chemical-mechanical polish-ing (CMP) [ 46]). Third, other image processing techniques(such as the distance transform [ 47]) can be readily applied if desired.

Before a clustering technique can be applied, a similaritydenition is required. Suppose the DCT coefcients of thetwo images are represented as two vectors X and Y , and let x i in X ( yi in Y ) be a component index in a vector, thena common metric for comparing/clustering the two vectorsis the summation of the Euclidean distances for each vectorcomponent

i ( x i − yi)2 .Two images are similar if they have a very small (total)

Euclidean distance in terms of their selected DCT coefcients.Conversely, two images are dissimilar if they have a largeEuclidean distance. It should be noted that Euclidean distanceis chosen because of its popularity. Other distance functions,such as the cosine distance [ 48], can also be easily used andhas been explored as well. It is found that they generally givesimilar results.

Having dened the object representation and the similar-ity metric, the third step is to choose a suitable clusteringalgorithm. Data clustering is an extensively researched eldand there are many clustering algorithms available [ 45]. TheK -means algorithm [ 26] is one of the most popular approachesbecause of its ease of implementation and high speed. Otherapproaches include mixture resolving [ 44] and various graph-theoretic approaches [ 49], [50]. Due to its simplicity, theK -means algorithm is employed which we describe next.

Let x 1 , x 2 , . . . , x N denote the N data points to be clustered,K be the desired number of clusters, µ 1 , µ 2 , . . . , µ K be the


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cluster centers, and r ij denote the potential assignment of theith data point to the jth cluster where

r ij =1 if the ith data point is assigned to the jth cluster0 if otherwise .

The objective of K -means is to minimize the following costfunction [ 44]:

C = N

i= 1

K

j= 1

r ij × dist ( x i , µ j)

where dist ( x i , µ j) is the distance function that measures sim-ilarity of data point x i and the cluster center µ j. The totalEuclidean distance dened earlier is used. From the expres-sion of the cost function C , it is clear that the goal is to choosecluster centers (i.e., µ j, 1 ≤ j ≤ K ) and data-point assignments(i.e., r ij) such that the distance sums (from the data points totheir assigned cluster centers) is minimized. This problem isNP-hard [ 51], so an approximate heuristic is typically used tond a solution. From the cost-function expression, it is alsoclear that the choice for K determines the number of clusters.It is nontrivial to choose an optimal K . In general, K is chosenempirically or by heuristics that penalize data fragmentation.For LASIC, K is chosen by using a simple heuristic

min K subject to r ij dist ( x i , µ j) < T ∀i, j.

In other words, we choose the smallest K such that all thedata-point-to-cluster-center distances are smaller than a prede-ned threshold T (for some T > 0). Intuitively, as long as eachdata point is reasonably close to its cluster center, increasingK is halted to avoid fragmentation of the data. To improveefciency, binary search is used to search for K . A hard limitis also used to restrict K to a reasonably small value. Findinga better and more efcient heuristic for identifying the opti-mal value of K is an open problem in the machine-learningcommunity.

There are several options for employing K -means for theproblem addressed in this paper. The simplest approach is tocreate snippet images for each candidate of interest and pro-vide the resulting images directly to the K -means algorithm.Unfortunately, this naïve approach unintentionally causes thelayout features from a single candidate that occupy a largelayout region to adversely bias the cluster centers, regardlessof the presence of systematic defects. Fig. 6 illustrates thissituation. Specically, Fig. 6(a) shows seven snippet imagesextracted from a long net while Fig. 6(b) shows three snippetimages extracted from a short net. It is clear that there existssimilarity for the images within the following groups: a1–a 7and b1–b3 . In other words, snippet images derived from thesame net tend to be strongly correlated (if not identical) andhave a small distance between each other. This is especiallythe case for a long net. If these images are provided as input tothe K -means algorithm, then images a 1–a7 may form a clustercenter, regardless of whether a systematic defect is present ina 1–a 7 . The same problem may occur for images b1–b3 as well.

A novel approach described here is to: 1) perform K -meanson the snippet images for each candidate rst; 2) select rep-resentative snippet images from each candidate using the

Fig. 6. Illustration of (a) correlated snippet images resulting from splittinga long net, and (b) the snippet image from a short net.

resulting clusters based on the cluster centers; and 3) per-form K -means again on the representative snippet imagesfrom all the candidates. This approach identies uniquerepresentative layout features from each candidate so thatrepeating/similar features from the same candidate will notbias the overall clustering process. In addition, this approachhas the advantage that the number of images to be clustered(in the second pass) is substantially reduced, thereby achievinga faster runtime. Using again the nets of Fig. 6, only snippetimages { a 1–a 4 , b1–b2} will be used as input to the second passof the K -means algorithm. The two-pass K -means algorithmis implemented in MATLAB [ 52].

Unfortunately, the distance metric adopted and many othercommonly used distance metrics (e.g., cosine distance) are notrotation- or reection-invariant with respect to the image ori-entation. Fig. 7 illustrates this problem. It may or may not beclear that the eight snippets shown are exactly the same, sincethey are shown with different orientations. The ideal distancemetric should give a distance of zero between any two of theseimages, but this is not the case because the Euclidean metric isnot immune to orientation. One possible solution is to denethe distance metric to be the minimum distance between twoimages A and B under all orientations of B (note that, we donot need to consider all orientations of A). This is the approachadopted in [ 20] and [21] for performing hotspot analysis. Thismethod is accurate, but would tremendously increase runtime(by up to a factor of 8 × ) since the distance-metric evaluation isa core step in all clustering algorithms [ 45]. A faster approachis to generate the clusters rst using the current distance met-ric, and then merge the resulting clusters afterwards using theimages at the cluster centers only, taking into account all pos-sible orientations of the cluster centers. This is advantageoussince the cluster centers are only used for the more expensivedistance metric calculation. The number of cluster centers istypically far less than the number of images. This is a heuris-tic, however, which means it is possible that two or more of the images in the merged cluster have a distance that is largerthan the threshold used in the second K -means pass since onlythe cluster centers are considered during the merging process.

To merge the clusters, the clustering outcome is representedusing a graph, where each vertex represents the snippet imageclosest to the cluster center and an edge exists between twovertices (i.e., images), if and only if the minimum distancebetween the two images, including their eight rotated and


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Fig. 7. Illustration of eight different orientations of a single layout pattern.

Fig. 8. Overall ow of the snippet image clustering process.

reected representations, is less than a certain threshold. (Thisthreshold should be chosen to have a similar value as thethreshold used in the second K -means pass.) Clearly, twoclusters should be merged if an edge exists between their cor-responding vertices in the graph. Thus, the cluster-mergingproblem is equivalent to identifying the connected componentsof the graph, i.e., clusters in the same connected compo-

nent should be merged. This problem can be easily solvedby using a depth-rst search in linear time [ 53]. It is possiblethat merged clusters have elements (i.e., snippets) that havea distance greater than the threshold but we have not foundthis to be an issue in this paper. Fig. 8 illustrates the overallow for clustering which typically only takes a few minutesof compute time for processing.

E. Simulation Validation

After clustering, each snippet image is assigned a label toindicate its cluster. For example, suppose 100 snippet imagesare grouped into six clusters, implying that each snippet image

will be labeled with an integer from 1 to 6. The clustersformed are sorted according to their sizes (i.e., the numberof data points assigned to a cluster) in decreasing order. Theresulting order is called the rank of the cluster. Specically,the largest cluster has rank one, the second largest cluster hasrank two, and so on. The dominant clusters are of particularinterest because they represent substantial commonalities inlayout features among the observed failures and are likely tocontain systematic defects (if any). Snippet images in the samecluster exhibit some degree of similarity and can be manuallyinspected. However, a more effective approach is to choosea few representatives from each cluster for further analysis.This is achieved by sampling several snippet images closestto the cluster centers. In this paper, lithography simulation of the layout snippets is performed to identify any lithography-induced hotspots. Hotspot investigation is performed sincesub-wavelength lithography is ubiquitously deployed in nano-scale technologies and is a major source of systematic issues.The software tool Optissimo [ 27] is used to perform thesimulation.

Analysis does not have to be limited to lithography, how-ever, for example, CMP simulation (using CMP analyzer [ 54]for instance) can be used to identify any yield-limiting hotspotsinduced by CMP. In fact, simulators for any yield-loss mech-anism can be employed to investigate the existence of anysystematic issues that may explain a large cluster of failures.Of course, each source of failure may require a different radiusof inuence for constructing the snippet images.

As stated earlier, although a simulation-based approach isinvoked in this paper for validating the existence of a system-atic defect, other more comprehensive and conclusive methodscan also be used including PFA.

Once the systematic defects are identied and understood,it is possible to tune the manufacturing process to minimizetheir occurrences to improve yield. In addition, it is possibleto describe yield-limiting layout features directly using designrule check tools such as calibre pattern matching [ 55]. Theserules can then be applied to the current design in produc-tion to estimate the failure rate of these features by notingtheir frequency of occurrence in diagnosis-implicated regionsto understand their yield impact. However, the details of thisanalysis are beyond the scope of this paper. If the system-atic defects identied have a signicant yield impact, thenthe corresponding DFM rules can be provided to the design-ers so that the systematic defects can be mitigated in futuredesigns [ 10], [56].

III . E XPERIMENTAL R ESULTS

In this section, experimental results involving both testdata from actual chip failures and simulation data arepresented.

A. Silicon-Data Experiment

An experiment was carried out using an industrial test chipfrom LSI Corporation to study the effectiveness of LASIC.The test chip, fabricated using 130-nm technology, consistsof 384 64-bit arithmetic logic units (ALUs). Each ALU has


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Fig. 9. Illustration of clustered snippet images from (a) one cluster and(b) second cluster.

approximately 3,000 gates and is tested using approximately 3

230 tests that achieve ∼100% stuck-at fault coverage. In thispaper, 6,980 failing ICs are used. Removal of non-ALU fail-ures, multiple-ALU failures, and failures with massive failingbits lead to 738 unique failing ICs that are used for furtheranalysis in LASIC. These failing ICs are successfully diag-nosed using DIAGNOSIX [ 29] resulting in 2,168 diagnosiscandidates. LASIC is applied to all 2,168 diagnosis candidates.In addition, in order to validate LASIC, two additional ICswith preexisting PFA results are also included in this experi-ment. Both ICs have two diagnosis candidates, both of whichare included in the experiment.

LAT (described in Section II-C) is applied to the 2,172 diag-nosis candidates using a 2-by-2 µ m area for dening thesnippet size. Both the width and height of the snippet sizeare more than 15 × larger than the minimum feature size(0.13 µ m) and therefore should be sufcient for capturingall optical interactions [ 57]. To ensure accuracy, each snippetimage is chosen to have a resolution of 100-by-100 pixels.Figs. 8 and 9 show LASIC-generated snippet images with thisresolution. It is clear that the layout features are sharply repre-sented with this resolution. A total of 291,249 snippet imagesare generated for the 2,172 diagnosis candidates. Column 5of Table I shows the number of extracted snippet images foreach layer (column 1).

The two-pass K -means clustering approach described earlieris applied to the snippet images for each layer separately since,in this paper, we are investigating lithography issues which isa function of one layer only. T 1 (column 2) and T 2 (column 3)are the thresholds for choosing K for the rst-pass and second-pass K -means, respectively. T 1 and T 2 indirectly specify thedesired cluster size and are empirically chosen. T 3 (column 4)is the threshold used when merging the clusters and is chosento have the same value as T 2 . Column 6 of Table I showsthe number of snippet images selected by the rst-pass of K -means. After the execution of the second-pass, the clustersare merged taking into account the different orientations of the cluster centers. The number of clusters before and afterthe merges are given in columns 7 and 8, respectively, of Table I. In addition, cluster size (i.e., the number of data pointsassigned to a cluster) is measured for all clusters and theirminimum, maximum, and average values are recorded incolumns 9–11, respectively. Cluster size is a measure of the

3The number of tests varies slightly for each ALU.

importance of a cluster (e.g., a cluster with 20 data points isnot as important as a cluster with 200 data points).

Table I reveals that the clustering outcome via the lay-ers consists of a small number of clusters. This is expectedbecause most of the images contain a single via in the centerof the image. Occasionally, neighboring vias are included inthe image, and sometimes the difference is large enough toresult in an extra partition. On the other hand, snippet imagesin the contact layer are partitioned into many more clusters.This too is expected since contacts are more densely placedthan vias in general and therefore the same 2-by-2 µ m bound-ing box captures a more diverse set of images in the contactlayer. A similar trend is observed for the polysilicon and metallayers. In other words, a more densely routed layer results inmore clusters since denser routes result in a more diverse setof snippets. The irregular geometries in the metal-1 layer alsocontribute to more clusters. As a result, it is worth exploringdifferent bounding-box sizes for each layer.

It is also informative to inspect the images in the samecluster as well as the images that are in different clusters.The clusters for metal-1 are chosen for illustration pur-poses since metal-1 contains a diverse set of geometries.Fig. 9(a) shows four snippet images from a cluster in metal-1,while Fig. 9(b) shows four snippet images from anothermetal-1 cluster. Fig. 9 shows that geometries in the same clus-ter resemble each other but are not exactly the same whilegeometries in different clusters exhibit substantial differences.This example clearly demonstrates that LASIC is able togroup images with similar layout features together for furtheranalysis.

The layout snippets that correspond to the snippet imagesare fed to Optissimo [ 27] for lithography simulation. Thesize of the snippets has been increased to ensure accuratesimulation. 4 Since the LSI test chip for this experiment isimplemented in 130-nm technology, the lithography parame-ters are chosen to coincide with that technology, as shown inTable II. (A more detailed explanation of the parameter valueschosen is given in [ 58].) For this part of the experiment, focusis again placed on the metal-1 layer only.

Fig. 10 shows an example of a lithography-induced hotspot(i.e., insufcient contact coverage) identied by the Optissimosimulation on one of the layout snippets. The simulation resultfor the contact layer is also shown so that the hotspot can berevealed. There are altogether 20 hotspots identied in themetal-1 layer. These hotspots may cause systematic defects.More conclusive analysis such as PFA can be used to inspectthe corresponding areas in the corresponding failing ICs todetermine if these hotspots are yield-limiting. If they arefound to be causing signicant yield loss, the process canbe adjusted to improve yield. In addition, DFM rules can beformulated to prevent occurrence of these hotspots in futuredesigns. For example, the insufcient coverage of the contactin Fig. 10 can be resolved by increasing the metal-1-to-contactenclosure requirement.

4The snippet size for an accurate simulation may not be the same as theimage size used in clustering. For example, CMP depends on a much largerarea depending on the type of model used for identifying CMP-susceptiblegeometries and metal densities.


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TABLE ISUMMARY OF THE T WO -PAS S K -M EANS C LUSTERING O UTCOME FOR EACH L AYER FOR 738 IC F AILURES

TABLE IIPROCESS PARAMETERS U SED FOR L ITHOGRAPHY S IMULATION

Fig. 10. Illustration of a hotspot (insufcient contact coverage) identiedthrough lithographic simulation of a layout snippet.

To validate LASIC, the clustering outcomes of the twoICs that have PFA results are examined in detail. Both ICshave snippet images of their corresponding defect locations(as identied by PFA) in highly-ranked clusters. Specically,the rst PFA result is a bridge between a polysilicon gateand its active region. The snippet image corresponding to thisdefect belongs to the second largest cluster (with size 348) inthe polysilicon layer (the maximum cluster size in thepolysilicon layer is 439). Fig. 11 shows the SEM imageof the PFA result and its corresponding layout region. Thelithography simulation from Fig. 11(b) does not show any

Fig. 11. (a) SEM image of a poly-to-active bridge and (b) its correspondinglayout snippet with its lithography simulation result.

Fig. 12. (a) SEM image of a bridge in the metal-2 layer and (b) its corre-sponding layout snippet with its lithography simulation result.

abnormalities, indicating that the systematic issue, if any, islikely due to other reasons.

The second PFA result is a bridge between two nets inmetal-2, and its SEM image and layout region are shownin Fig. 12. The snippet image corresponding to this defectbelongs to a cluster that is in the top 10.6% of all clusters.These results are strong evidence that LASIC is able to identifysystematic defects since PFA is a time-consuming process [ 6]and therefore is selectively performed on certain ICs when sys-tematic issues are suspected. In other words, because failuresdue to random defects are typically not selected to undergoPFA, we believe this is strong evidence that LASIC canidentify systematic defects.

From the clustering outcome in Table I, it is clear that otherhighly-ranked clusters are also present, suggesting the possiblepresence of additional systematic defects. Unfortunately, this


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TABLE IIICHARACTERISTICS OF THE D ESIGNS , TESTS , A ND D EFECTS U SED IN THE S IMULATION E XPERIMENTS

cannot be conrmed since further PFA results are unattainable.In addition, the point should be made that large cluster sizes arenot indicative of the existence of a systematic defect. Deeminga cluster large or small should not be based on raw elementcount but instead be based on a normalization that depends onthe total number of similar snippets within the design.

B. Simulation-Data Experiment

In this section, two sets of simulation experiments are con-ducted to examine how LASIC performs under the presence of:1) a single type of systematic defect and 2) multiple types of systematic defects.

In both experiments, the defect simulation framework SLIDER (simulation of layout-injected defects for electricalresponses) [ 59] is used to generate populations of virtualIC failures. SLIDER achieves fast and accurate defect sim-ulations using mixed-signal simulation. Specically, SLIDERinjects defects at the layout-level and extracts a circuit-levelnetlist of the defect-affected region(s). This ensures that thedefects are accurately represented. Circuit-level simulation isperformed using the extracted netlist of the defect-affectedregion(s) to ensure accuracy while logic-level simulation isperformed for the rest of the circuit to keep the runtimetractable. By using a mixed-signal simulator (such as CadenceAMS designer [ 60]), appropriate signal conversion can beautomatically performed at the interface that connects the dig-ital and analog domains. SLIDER can generate defects thatfollow a given DDSD distribution (i.e., random defects). Itcan also generate defects that share a common layout pattern(i.e., systematic defects). These two defect-generation modesare particularly useful for the validation of LASIC.

1) Experimental Setup: Table III summarizes the char-acteristics of the designs, tests, and defects injected forboth experiments. In both experiments, eight benchmark circuits [ 24], [25] are used whose names are shown in col-umn 1 of Table III . These circuits are placed and routed usingCadence First Encounter. The technology used is the TaiwanSemiconductorManufacturing Corporation 180-nm CMOSpro-cess from the publicly-accessible Metal Oxide SemiconductorImplementation Service webpage [ 62]. The tests for these cir-cuits are generated using Synopsys Tetramax [ 63] and havea 100% fault coverage. The corresponding number of gates,layout area, and number of tests for each circuit are shown incolumns 2–4 of Table III, respectively.

Five different systematic populations and one random popu-lation, each consisting of 100 defective chips, are generated foruse in both experiments. Both the systematic and random pop-ulations are generated using the systematic- and random-defectgeneration modes of SLIDER, respectively. This process isrepeated four times to inject four different types of defects(namely, metal-2 bridge, metal-2 open, metal-3 bridge, andmetal-3 open). Since LASIC uses logic-level diagnosis as thestarting point, two different defects are treated the same wayif they both affect the same net. Therefore, it is importantto know the number of distinct nets ( N distinct ) that are actu-ally affected by the defects. These counts are summarized incolumns 5, 6, 8, 10, 12, and 14 of Table III . Column 5 revealsthat the number of distinct nets in the random population ismore than 100. Interestingly, the number of distinct nets inall the systematic populations is less than 100, as shown incolumns 6, 8, 10, 12, and 14 of Table III. The former hap-pens since a random defect can occur anywhere in the circuitand can affect multiple nets. The latter occurs since, as shownin Fig. 7, snippets from the same net tend to be correlatedand this phenomenon also results in systematic defects beinginjected along the same net. In addition, it is of interest tounderstand the amount of overlap between the random andsystematic defects in terms of the number of common netsthat they both affect since this too will affect the accuracyof LASIC. For example, a random defect affecting the samenet as a systematic defect can “improve” the accuracy of LASIC since the affected net also contains the layout patternof the systematic defect. Therefore, the number of commonnets ( N overlap ) between each of the ve systematic populationsand the random population is recorded in columns 7, 9, 11, 13,and 15, respectively. Note that the entries in columns 5–15 arefractional because, as mentioned above, the experiment is per-formed four times to inject four different types of defects andtherefore the counts are averaged over the defect types.

From Table III, it is clear that as the circuit size increases,the chance of random and systematic defects affecting thesame net decreases, as expected. It is also clear that the amountof overlap is less than 20% in general (except for the smallercircuits C5315 and C6288). This is desirable since this pre-vents random defects from affecting the accuracy of LASICin systematic defect identication.

In both experiments, the systematic defects are carefullygenerated so that their underlying layout pattern is not a com-mon layout pattern. Otherwise, the pattern will be found in


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a dominant cluster regardless of whether a systematic issue ispresent. Specically, we identify layout patterns that occur atleast N times ( N >> 100) for each metal layer of interest, andrandomly select instances of the pattern for defect injection.

2) Single Systematic Defect Identication: In the rstexperiment, failure populations are created by randomly sam-pling from the “random” population and the “systematic 1”population, described in the experimental setup. This processis repeated to generate failure populations with a different pro-portion of random and systematic defects. For example, in therst iteration, the population has 100 systematic defects and0 random defects; in the second iteration, the population has90 systematic defects and 10 random defects; in the third iter-ation, the population has 80 systematic defects and 20 randomdefects, and so on. The goal is to evaluate how much random“noise” can be tolerated by LASIC. The experiment is per-formed using the eight benchmark circuits in Table III. Theexperiment is performed four times to inject four types of defects into these circuits: 1) metal-2 bridge; 2) metal-2 open;3) metal-3 bridge; and 4) metal-3 open. The results are aver-aged over the eight circuits. In addition, to isolate the noisethat can happen due to inaccuracies/ambiguities in diagnosis,this experiment is performed under two scenarios: ideal diag-nosis and “real” diagnosis. Ideal diagnosis here means thatthe outcome of diagnosis correctly pinpoints the site of theinjected defect with no ambiguity, while real diagnosis canbe inaccurate (i.e., diagnosis outcome does not contain theinjected-defect net) and/or low in resolution (i.e., additionalnets are reported along with the net with the injected defect).Since virtual failure data is used, ideal-diagnosis results can beeasily obtained by just nding the net whose geometry over-laps with the actual defect location. Real-diagnosis results areobtained by applying a commercial diagnosis tool to the vir-tual failure data, which results in inaccuracies/ambiguities dueto the inherent limitation of logic-level diagnosis. This can beviewed as another source of noise in the data. Comparing thetwo scenarios allows us to understand how LASIC performsunder the ideal and real scenarios. The cluster that containsthe underlying pattern of the injected systematic defect isdeemed the correct cluster. For each scenario, the averagedrank of the correct cluster is plotted against the percentageof systematic defects injected. The data is summarized inFig. 13(a) and (b) for the ideal and real diagnoses, respectively.

It is clear from Fig. 13 that the average rank of the correctcluster decreases (which of course is desirable since a lowerrank means the layout geometry associated with the injecteddefect resides in a larger cluster) as the percentage of sys-tematic defects increases for both ideal and real diagnoses. Itis also evident that the technique is effective for both idealand real diagnoses because the correct cluster is present in thetop 40 ranked clusters (top 3%) even when the population onlyconsists of 20% systematic defects. In addition, there is a steepincrease in the average rank of the correct clusters when theproportion of the systematic defect decreases from 10% to 0%.This is expected since the “correct pattern” becomes a ran-dom pattern when there is no systematic defect present andtherefore the correct pattern should go into a cluster of verysmall size with a very low rank. The performance of LASIC isexpectedly somewhat worse for real diagnosis due to inherent

Fig. 13. LASIC evaluation for (a) ideal and (b) real diagnoses.

TABLE IVM ULTIPLE S YSTEMATIC D EFECT C REATION FOR LASIC E VALUATION

ambiguities/inaccuracies associated with logic diagnosis. Theranks of the correct clusters increase by a factor of ∼2.4 onaverage in the real diagnosis scenario.

3) Multiple Systematic Defect Identication: By focusingon one systematic issue at a time, the previous experimentevaluates the performance of LASIC in the presence of ran-dom defects and diagnosis inaccuracy. However, in practicalsituations, there may be multiple systematic issues presentin different proportions. To understand the effectiveness of LASIC in practice, all the ve different systematic popula-tions described in the experimental setup are used. Precautionhas been taken to ensure that the underlying patterns are differ-ent for the ve systematic populations to mimic the presenceof ve different systematic issues for each benchmark circuit.The random population is also included to mimic the presenceof random defects. The defects from these populations are ran-domly sampled and mixed in different proportions. Table IVsummarizes the amount of sampling from each population foreach scenario. The same sampling procedure is performed foreach benchmark circuit.

Column 1 shows the name for each defect population,namely systematic 1–5 and random, corresponding to the vesystematic populations and the one random population. Theremaining four columns dene the four different scenariosconsidered in this experiment. Each numeric entry in Table IVdenes the amount of sampling from the corresponding pop-ulation (row) in the corresponding scenario (column). Forexample, in the scenario “Dom1,” 70 defects are sampled fromthe rst systematic population, 70 defects are sampled fromthe random population, and 20 defects are sampled from eachof the four remaining systematic populations.

Four different scenarios are considered in this experimentthat includes the following.

1) “Equal” (column 2) where the number of defects fromeach systematic population is equal.


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Fig. 14. LASIC evaluation for multiple systematic defects for (a) metal-2bridge, (b) metal-3 bridge, (c) metal-2 open, and (d) metal-3 open.

2) “Linear” (column 3) where the number of defects islinearly decreasing for each systematic population.

3) “Dom1” (column 4) where one systematic populationcontributes substantially more defects than the rest.

4) “Dom2” (column 5) where two of the systematic popula-tions contribute substantially more defects than the rest.

In each scenario, 70 random defects are included to mimicthe presence of random defects (row 7 of Table IV).

LASIC is applied to each of the four scenarios for eachbenchmark circuit. Here, the goal is to evaluate whetherLASIC is able to identify all ve systematic defect types.Therefore, the number of systematic issues correctly identiedis plotted against the number of top-ranked clusters consid-ered, which is varied from 5 to 55. In contrast to the previousexperiment, only real diagnosis is used in this experiment inorder to mimic how LASIC would be deployed in practice.Again, the experiment is repeated four times to inject fourtypes of defects into the benchmark circuits: 1) metal-2 bridge;2) metal-3 bridge; 3) metal-2 open; and 4) metal-3 open. Theresults for each of the four defect types are averaged over theeight circuits and are shown in Fig. 14(a)–(d).

It is clear from Fig. 14 that the number of systematic issuescorrectly identied increases rapidly to the ideal value of veas the number of top-ranked clusters considered increases. Asdemonstrated in Fig. 14, LASIC is able to identify over 90%(i.e., 4.5/5.0) systematic defects in the top 55 clusters for alldefect types considered under all four scenarios. The resultsclearly show that LASIC is effective even when there aremultiple systematic-defect types and random defects present.

IV. C ONCLUSION

In this paper, we described LASIC, a comprehensivemethodology for identifying yield-limiting layout features.

LASIC identies systematic defects by extracting and cluster-ing snippet images of the diagnosis-implicated layout regions.Further analyses, such as lithography simulation or PFA, canbe used to conrm the systematic issues. Silicon experimentresults have demonstrated that LASIC is effective in group-ing snippet images with similar features to identify systematicdefects. Moreover, several lithographic hotspots have beenidentied within the dominant clusters. Simulation experi-ments using SLIDER accurately quantify the effectiveness andaccuracy of LASIC for failure populations affected by eithersingle or multiple systematic-defect types. LASIC resolves themissing link in many systematic-defect identication method-ologies by providing an automatic method of discoveringfailure-causing layout features. LASIC can be integrated intoexisting systematic-defect identication methodologies or usedindependently. Integration into existing approaches can be eas-ily achieved by using LASIC as a post-processing step toautomatically identify and extract layout features that are prob-lematic. Finally, LASIC is also scalable since the number andsize of the snippets is independent of the design but insteaddepends on the failed-chip population size and the resolutionof diagnosis.

V. A CKNOWLEDGMENT

The authors would like to thank the LSI Corporation forproviding design and fail data.

R EFERENCES

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Conf., Charlotte, NC, USA, 2004, pp. 290–299.[3] W. C. Tam, O. Poku, and R. D. Blanton, “Systematic defect identicationthrough layout snippet clustering,” in Proc. Int. Test Conf. , Austin, TX,USA, 2010, pp. 1–10.

[4] R. Turakhia, M. Ward, S. K. Goel, and B. Benware, “Bridging DFManalysis and volume diagnostics for yield learning—A case study,” inProc. IEEE VLSI Test Symp. , Santa Cruz, CA, USA, 2009, pp. 167–172.

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[8] K. Martin et al. , “A rapid yield learning ow based on production inte-grated layout-aware diagnosis,” in Proc. Int. Test Conf. , Santa Clara,CA, USA, 2006, pp. 1–10.

[9] T. Huaxing, S. Manish, J. Rajski, M. Keim, and B. Benware, “Analyzingvolume diagnosis results with statistical learning for yield improvement,”in Proc. Eur. Test Symp. , Freiburg, Germany, 2007, pp. 145–150.

[10] W. C. Tam and R. D. Blanton, “To DFM or not to DFM?” in Proc. Design Autom. Conf. , New York, NY, USA, 2011, pp. 65–70.

[11] R. Kapur, M. Kapur, and M. Kapur, “Systemic diagnostics for increasingwafer yield,” U.S. Patent 20 110040 528, Feb. 17, 2011.

[12] J. E. Nelson, “Using integrated circuits as virtual test structures to extractdefect density and size distributions,” Ph.D. dissertation, Dept. Electr.Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA, 2010.

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