CONTROLLER MANUAL - Fujitsui PREFACE Objectives and Intended Readers Thank you for purchasing FUJITSU semiconductor products. The MB89170/170A/170L series products have been developed

FUJITSU SEMICONDUCTORCONTROLLER MANUAL

F2MC-8L8-BIT MICROCONTROLLER

MB89170/170A/170L SeriesHARDWARE MANUAL

CM25-10115-3E

F2MC-8L8-BIT MICROCONTROLLER

MB89170/170A/170L SeriesHARDWARE MANUAL

FUJITSU LIMITED

PREFACE

Objectives and Intended Readers

Thank you for purchasing FUJITSU semiconductor products.

The MB89170/170A/170L series products have been developed as general-purpose products in

the F2MC-8L series. The F2MC-8L series is made up of proprietary 8-bit, single-chipmicrocontrollers suitable for use as application specific ICs (ASIC). These devices are suitablefor a wide range of uses, from consumer electronics to industrial equipment and includingportable equipment.

This manual describes the functions and operation of the MB89170/170A/170L seriesmicrocontrollers and is written for engineers who are developing actual products using theMB89170/170A/170L. Read this manual before using the MB89170/170A/170L series models.

See the F2MC-8L Programming Manual for more information about the instruction set.

Trademarks

The system names and product names used in this manual are the trademarks of theirrespective companies or organizations.

The symbols TM and are sometimes omitted in the text.

Structure of This Manual

This manual consists of the following 13 chapters and appendixes.

CHAPTER 1 "MB89170/170A/170L SERIES FEATURES"

This chapter provides an overview of the features and basic specifications of the MB89170/170A/170L series.

CHAPTER 2 "HANDLING DEVICES"

This chapter describes precautions to observe when using the MB89170/170A/170L series.

CHAPTER 3 "CPU"

This chapter describes the functions and operation of the MB89170/170A/170L series CPU.

CHAPTER 4 "I/O PORTS"

This chapter describes the functions and operation of the MB89170/170A/170L series I/Oports.

CHAPTER 5 "TIMEBASE TIMER"

This chapter describes the functions and operation of the MB89170/170A/170L seriestimebase timer.

CHAPTER 6 "WATCHDOG TIMER"

This chapter describes the functions and operation of the MB89170/170A/170L serieswatchdog timer.

CHAPTER 7 "8/16-BIT TIMER/COUNTER"

This chapter describes the functions and operation of the MB89170/170A/170L series 8/16-bit timer/counter.

i

CHAPTER 8 "8-BIT SERIAL I/O"

This chapter describes the functions and operation of the MB89170/170A/170L series 8-bitserial I/O.

CHAPTER 9 "BUZZER OUTPUT"

This chapter describes the functions and operation of the MB89170/170A/170L series buzzeroutput.

CHAPTER 10 "EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)"

This chapter describes the functions and operation of the MB89170/170A/170L seriesexternal interrupt circuit 1 (edge).

CHAPTER 11 "EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)"

This chapter describes the functions and operation of the MB89170/170A/170L seriesexternal interrupt circuit 2 (level).

CHAPTER 12 "WATCH PRESCALER"

This chapter describes the functions and operation of the MB89170/170A/170L series watchprescaler.

CHAPTER 13 "DTMF GENERATOR"

This chapter describes the functions and operation of the MB89170/170A/170L series DTMFgenerator.

APPENDIX

The appendixes include the I/O map, instruction map, and others.

ii

©2001 FUJITSU LIMITED Printed in Japan

• The contents of this document are subject to change without notice. Customers are advised to consultwith FUJITSU sales representatives before ordering.

• The information and circuit diagrams in this document are presented as examples of semiconductordevice applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU isunable to assume responsibility for infringement of any patent rights or other rights of third partiesarising from the use of this information or circuit diagrams.

• The products described in this document are designed, and manufactured as contemplated for generaluse, including without limitation, ordinary industrial use, general office use, personal use, and householduse, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatalrisks or dangers that, unless extremely high safety is secured, could have a serious effect to the public,and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclearreaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medicallife support system, missile launch control in weapon system), or (2) for use requiring extremely highreliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damagesarising in connection with above-mentioned uses of the products.

• Any semiconductor devices have an inherent chance of failure. You must protect against injury,damage or loss from such failures by incorporating safety design measures into your facility andequipment such as redundancy, fire protection, and prevention of over-current levels and otherabnormal operating conditions.

• If any products described in this document represent goods or technologies subject to certainrestrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the priorauthorization by Japanese government will be required for export of those products from Japan.

iii

How to Use This Manual

Example of register and pin name notation

Example of register and bit name notation

Example notation for shared pins

P30/SCK pin

The functions of some pins (called shared pins) can be selected by using the program orusing another method. The notation for shared pins consists of names corresponding toeach of the pin functions separated by slashes "/."

By writing "1" to the sleep bit of the standby control register (STBC:SLP),...

Register abbreviation

Bit abbreviation

Disable the interrupt request output of the timebase timer (TBTC:TBIE = 0).

Set data


Interrupts can be accepted if interrupts are enabled (CCR:I = 1).

Current status

Bit name Register name

Bit abbreviation


Bit abbreviation

iv

CONTENTS

CHAPTER 1 MB89170/170A/170L SERIES FEATURES .................................................. 11.1 MB89170/170A/170L Series Features ................................................................................................... 21.2 MB89170/170A/170L Series Product Lineup ......................................................................................... 41.3 Differences between Models ................................................................................................................. 61.4 Block diagram of MB89170/170A/170L Series ...................................................................................... 81.5 Pin Assignment .................................................................................................................................... 101.6 Package Dimensions ........................................................................................................................... 131.7 Pin Descriptions ................................................................................................................................... 151.8 I/O Circuit Types .................................................................................................................................. 18

CHAPTER 2 HANDLING DEVICES ................................................................................. 212.1 Handling Devices ................................................................................................................................. 22

CHAPTER 3 CPU ............................................................................................................. 233.1 Memory Space ..................................................................................................................................... 24

3.1.1 Special-purpose areas .................................................................................................................... 263.1.2 Allocation of 16-bit data in memory ................................................................................................ 28

3.2 Dedicated Registers ............................................................................................................................ 293.2.1 Condition code register (CCR) ....................................................................................................... 323.2.2 Register bank pointer (RP) ............................................................................................................. 35

3.3 General-Purpose Registers ................................................................................................................. 363.4 Interrupts ............................................................................................................................................. 38

3.4.1 Interrupt level setting registers (ILR1, ILR2, and ILR3) .................................................................. 393.4.2 Processing during an interrupt ........................................................................................................ 413.4.3 Multiple interrupts ........................................................................................................................... 433.4.4 Interrupt processing time ................................................................................................................ 443.4.5 Stack operation during interrupt processing ................................................................................... 453.4.6 Stack area for interrupt processing ................................................................................................. 46

3.5 Reset ................................................................................................................................................... 473.5.1 External reset pin ............................................................................................................................ 493.5.2 Reset operation .............................................................................................................................. 503.5.3 Pin states during a reset ................................................................................................................. 52

3.6 Clock .................................................................................................................................................... 533.6.1 Clock generator .............................................................................................................................. 563.6.2 Clock controller .............................................................................................................................. 583.6.3 System clock control register (SYCC) ............................................................................................ 603.6.4 Clock modes ................................................................................................................................... 623.6.5 Oscillation stabilization delay time .................................................................................................. 65

3.7 Standby Modes (Low Power Consumption) ........................................................................................ 683.7.1 Operating states in standby modes ................................................................................................ 703.7.2 Sleep mode .................................................................................................................................... 723.7.3 Stop mode ...................................................................................................................................... 733.7.4 Watch mode ................................................................................................................................... 753.7.5 Standby control register (STBC) ..................................................................................................... 76

v

3.7.6 State transition diagram 1 (power-on reset, dual-clock) ................................................................ 783.7.7 State transition diagram 2 (no power-on, dual-clock) .................................................................... 803.7.8 State transition diagram 3 (single-clock) ........................................................................................ 833.7.9 Pin states in standby mode ............................................................................................................ 853.7.10 Notes on using standby modes ..................................................................................................... 87

3.8 Memory Access Mode ........................................................................................................................ 89

CHAPTER 4 I/O PORTS .................................................................................................. 934.1 Overview of the I/O Ports .................................................................................................................... 944.2 Port 0 .................................................................................................................................................. 96

4.2.1 Port 0 registers (PDR0, DDR0) ...................................................................................................... 984.2.2 Port 0 operation ............................................................................................................................. 99

4.3 Port 1 ................................................................................................................................................ 1014.3.1 Port 1 registers (PDR1, DDR1) ................................................................................................... 1034.3.2 Port 1 operation ........................................................................................................................... 104

4.4 Port 2 ................................................................................................................................................ 1064.4.1 Port 2 register (PDR2) ................................................................................................................. 1084.4.2 Port 2 operation ........................................................................................................................... 109

4.5 Port 3 ................................................................................................................................................ 1104.5.1 Port 3 registers (PDR3, DDR3) .................................................................................................... 1124.5.2 Port 3 operation ........................................................................................................................... 114

4.6 Port 4 ................................................................................................................................................ 1164.6.1 Port 4 register (PDR4) ................................................................................................................. 1184.6.2 Port 4 operation ........................................................................................................................... 119

4.7 I/O port program example ................................................................................................................. 120

CHAPTER 5 TIMEBASE TIMER .................................................................................... 1235.1 Overview of the Timebase Timer ...................................................................................................... 1245.2 Structure of the Timebase Timer ...................................................................................................... 1265.3 Timebase Timer Control Register (TBTC) ........................................................................................ 1285.4 Timebase Timer Interrupt .................................................................................................................. 1305.5 Operation of the Timebase Timer ..................................................................................................... 1315.6 Notes on Using the Timebase Timer ................................................................................................ 1335.7 Timebase Timer Program Example .................................................................................................. 135

CHAPTER 6 WATCHDOG TIMER ................................................................................. 1376.1 Overview of the Watchdog Timer ...................................................................................................... 1386.2 Structure of the Watchdog Timer ...................................................................................................... 1406.3 Watchdog Control Register (WDTC) ................................................................................................. 1426.4 Operation of the Watchdog Timer ..................................................................................................... 1446.5 Notes on Using The Watchdog Timer ............................................................................................... 1456.6 Watchdog Timer Program Example .................................................................................................. 146

CHAPTER 7 8/16-BIT TIMER/COUNTER ...................................................................... 1477.1 Overview of the 8/16-Bit Timer/Counter ............................................................................................ 1487.2 Structure of the 8/16-Bit Timer/Counter ............................................................................................ 1517.3 8/16-Bit Timer/Counter Pins .............................................................................................................. 1537.4 8/16-Bit Timer/Counter Registers ..................................................................................................... 155

vi

7.4.1 Timer 1 control register (T1CR) ................................................................................................... 1567.4.2 Timer 2 control register (T2CR) .................................................................................................... 1587.4.3 Timer 1 data register(T1DR) ......................................................................................................... 1607.4.4 Timer 2 data register (T2DR) ........................................................................................................ 162

7.5 8/16-Bit Timer/Counter Interrupts ...................................................................................................... 1647.6 Operation of the Interval Timer Function ........................................................................................... 1667.7 Operation of the Counter Function .................................................................................................... 1687.8 Operation of the Square Wave Output Initialization Function ............................................................ 1717.9 Halting and Restarting the 8/16-Bit Timer/Counter ............................................................................ 1737.10 State in Each Mode of 8/16-Bit Timer/Counter Operation ................................................................. 1747.11 Notes on Using the 8/16-Bit Timer/Counter ....................................................................................... 1757.12 8/16-Bit Timer/Counter Program Examples ....................................................................................... 177

CHAPTER 8 8-BIT SERIAL I/O ...................................................................................... 1818.1 Overview of the 8-Bit Serial I/O ......................................................................................................... 1828.2 Structure of the 8-Bit Serial I/O .......................................................................................................... 1838.3 8-Bit Serial I/O Pins ........................................................................................................................... 1858.4 8-Bit Serial I/O Registers ................................................................................................................... 187

8.4.1 Serial mode register (SMR) .......................................................................................................... 1888.4.2 Serial data register (SDR) ............................................................................................................ 191

8.5 8-Bit Serial I/O Interrupts ................................................................................................................... 1928.6 Serial Output Operation ..................................................................................................................... 1938.7 Serial Input Operation ........................................................................................................................ 1958.8 States in Each Mode of 8-Bit Serial I/O Operation ............................................................................ 1978.9 Notes on Using 8-Bit Serial I/O .......................................................................................................... 2008.10 8-Bit Serial I/O Connection Example ................................................................................................. 2018.11 8-Bit Serial I/O Program Example ...................................................................................................... 203

CHAPTER 9 BUZZER OUTPUT .................................................................................... 2079.1 Overview of the Buzzer Output .......................................................................................................... 2089.2 Structure of the Buzzer Output .......................................................................................................... 2109.3 Buzzer Output Pin .............................................................................................................................. 2119.4 Buzzer Output Register ..................................................................................................................... 212

9.4.1 Buzzer Register (BZCR) ............................................................................................................... 2139.5 Buzzer Output Program Example ...................................................................................................... 215

CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) .......................................... 21710.1 Overview of External Interrupt Circuit 1 (Edge) ................................................................................. 21810.2 Structure of External Interrupt Circuit 1 ............................................................................................. 21910.3 External Interrupt Circuit 1 Pins ......................................................................................................... 22110.4 External Interrupt Circuit 1 Registers ................................................................................................. 223

10.4.1 External interrupt 1 control register 1 (EIC1) ................................................................................ 22410.4.2 External interrupt 1 control register 2 (EIC2) ................................................................................ 226

10.5 External Interrupt Circuit 1 Interrupts ................................................................................................. 22810.6 Operation of External Interrupt Circuit 1 ............................................................................................ 22910.7 Sample Programs of External Interrupt Circuit 1 ............................................................................... 231

vii

CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) ........................................ 23311.1 Overview of External Interrupt Circuit 2 (Level) ................................................................................ 23411.2 Structure of External Interrupt Circuit 2 ............................................................................................. 23511.3 Pins of External Interrupt Circuit 2 .................................................................................................... 23711.4 Registers of External Interrupt Circuit 2 ........................................................................................... 239

11.4.1 External interrupt 2 control register (EIE2) ................................................................................... 24011.4.2 External interrupt 2 flag register (EIF2) ........................................................................................ 242

11.5 Interrupts from External Interrupt Circuit 2 ........................................................................................ 24311.6 Operation of External Interrupt Circuit 2 ........................................................................................... 24411.7 Sample Programs for External Interrupt Circuit 2 ............................................................................. 245

CHAPTER 12 WATCH PRESCALER .............................................................................. 24712.1 Overview of the Watch Prescaler ...................................................................................................... 24812.2 Structure of the Watch Prescaler ...................................................................................................... 25012.3 Watch Prescaler Control Register (WPCR) ...................................................................................... 25212.4 Watch Prescaler Interrupt ................................................................................................................. 25412.5 Operation of the Watch Prescaler ..................................................................................................... 25512.6 Notes on Using the Watch Prescaler ................................................................................................ 25712.7 Watch Prescaler Program Example .................................................................................................. 259

CHAPTER 13 DTMF GENERATOR ................................................................................. 26113.1 Overview of the DTMF Generator ..................................................................................................... 26213.2 Structure of the DTMF Generator ..................................................................................................... 26413.3 DTMF Generator Pin ......................................................................................................................... 26613.4 DTMF Generator Registers ............................................................................................................... 267

13.4.1 DTMF control register (DTMC) .................................................................................................... 26813.4.2 DTMF data register (DTMD) ........................................................................................................ 270

13.5 Operation of the DTMF Generator .................................................................................................... 27113.6 DTMF Generator Program Example ................................................................................................. 272

APPENDIX .......................................................................................................................... 273APPENDIX A I/O MAP ................................................................................................................................ 274APPENDIX B INSTRUCTION SUMMARY ................................................................................................. 278

B.1 Summary of F2MC-8L instructions ................................................................................................. 279B.2 Addressing ..................................................................................................................................... 282B.3 Special Instructions ........................................................................................................................ 286B.4 Bit Manipulation Instructions (SETB, CLRB) .................................................................................. 289B.5 F2MC-8L Instructions ..................................................................................................................... 290B.6 Instruction Map ............................................................................................................................... 296

APPENDIX C MASK OPTIONS .................................................................................................................. 297APPENDIX D PROM PROGRAMMING ..................................................................................................... 298

D.1 PROM Programming ..................................................................................................................... 299D.2 Programming the One-Time PROM ............................................................................................... 300D.3 Programming the EPROM on a Piggyback/Evaluation Chip .......................................................... 304

APPENDIX E PIN STATES FOR THE MB89170/170A/170L SERIES ...................................................... 305

INDEX...................................................................................................................................309

viii

CHAPTER 1 MB89170/170A/170L SERIES FEATURES

This chapter describes the features and basic specifications of the MB89170/170A/170L series.

1.1 "MB89170/170A/170L Series Features"

1.2 "MB89170/170A/170L Series Product Lineup"

1.3 "Differences between Models"

1.4 "Block diagram of MB89170/170A/170L Series"

1.5 "Pin Assignment"

1.6 "Package Dimensions"

1.7 "Pin Descriptions"

1.8 "I/O Circuit Types"

1


1.1 MB89170/170A/170L Series Features

In addition to a compact instruction set, the MB89170/170A/170L series products have a variety of peripheral functions including timers, a serial interface, a DTMF generator, and external interrupts. These series products are suitable for communication circuit control such as in telephones.

MB89170/170A/170L series features

Low-voltage, high-speed operation

• Minimum instruction execution time

• MB89170 series: 1.1 µs (at 3.58 MHz source oscillation)

• MB89170A/170L series: 0.6 µs (at 7.16 MHz source oscillation)

F2MC-8L CPU core

• Instruction set optimized for controllers

• Multiplication and division instructions

• 16-bit operations

• Bit-test branch instructions

• Bit manipulation and other instructions

Dual-clock control

• Main clock

• MB89170 series: 3.58 MHz maximum

• MB89170A/170L series: 7.16 MHz maximum

• Sub-clock

• 32.768 kHz (operating clock in sub-clock mode)

• For MB89170L series, only the main clock is used.

Three timer channels

• 8/16-bit timer/counter (8-bit x 2 channels or 16-bit x 1 channel)

• 21-bit timebase timer

• Watch prescaler (15-bit) (MB89170/170A series only)

Serial interface (serial I/O)

• Selectable transfer direction (MSB-first or LSB first) supports communication with a widerange of external devices.

External interrupts

• External interrupt 1 (3 channels)

2

1.1 MB89170/170A/170L Series Features

• Three inputs are independent and capable of using for wakeup from low-powerconsumption modes (with an edge detection function).

• External interrupt 2 (wakeup) (8 channels)

• Eight inputs are independent and can be used for wakeup from low-power consumptionmodes (with an "L" level detection function).

DTMF generator <MB89170/170A series only>

• Selectable source oscillation frequency (MB89170A series only)

Low power consumption (standby modes)

• Stop mode (Halts the oscillation to nearly eliminate current consumption.)

• Sleep mode (Halts the CPU to reduce current consumption to approximately one third ofnormal.)

• Watch mode (Halts all operations other than the watch prescaler operation to achieve verylow current consumption.)

• Sub-clock mode

• For MB89170L series, the stop mode and sleep mode only

Package

• QFP-48

Maximum of 37 I/O ports

• Output-only ports (N-channel open-drain): 5 ports

• Output-only ports (CMOS): 8 ports

• General-purpose I/O ports (CMOS): 24 ports

3


1.2 MB89170/170A/170L Series Product Lineup

The MB89170/170A/170L series product lineup consists of seven different models. Table 1.2-1 "MB89170/170A/170L series product lineup" lists the product lineup and Table 1.2-2 "CPU and peripheral functions of the MB89170/170A/170L series" lists the CPU and peripheral functions.

MB89170/170A/170L series product lineup

Table 1.2-1 MB89170/170A/170L series product lineup

ItemModel

MB89173 MB89P173 MB89174A MB89P175A MB89PV170A MB89173L MB89174L

Type Mass production product (mask ROM product)

One-time product (EPROM product)

Mass production product (mask ROM product)

One-time product (EPROM product)

Piggyback/evaluation product for evaluation and development

Mass production product (mask ROM product)

ROM size 8K x 8 bits (internal ROM)

8K x 8 bits (internal PROM, can be programmed by general-purpose programmer)

12K x 8 bit (internal ROM)

16K x 8 bit (internal PROM, can be programmed by general-purpose programmer)

32K x 8 bits (external ROM)

8K x 8 bits (internal ROM)

12K x 8 bit (internal ROM)

RAM size 384 x 8 bits 512 x 8 bits 1K x 8 bits 384 x 8 bits 512 x 8 bits

Low power consumption (standby modes)

Sleep mode, stop mode, watch mode, sub-clock mode Sleep mode, stop mode

Process CMOS

Operating voltage

2.2V to 6.0V *1 2.7V to 6.0V *1 2.2V to 6.0V *1 2.7V to 6.0V *1 2.2V to 6.0V *2 2.2V to 6.0V *2

*1 Depends on the operating frequency and DTMF warranty range.*2 Depends on the operating voltage of the EPROM. Use the MBM27C256A-20TVM EPROM.

4

1.2 MB89170/170A/170L Series Product Lineup

Table 1.2-2 CPU and peripheral functions of the MB89170/170A/170L series

ItemModel

MB89173 MB89P173 MB89174A MB89P175A MB89PV170A MB89173L MB89174L

CPU functions Number of basic instructions: 136Instruction bit length: 8 bitsInstruction length: 1 to 3 bytesData bit length: 1, 8, 16 bitsMinimum instruction execution time: 1.1 to 17.6 µs (at 3.58 MHz), 61 µs (at 32.768 kHz)Interrupt processing time: 10 to 160 µs (at 3.58 MHz), 562.5 µs (at 32.768 kHz)

Minimum instruction execution time: 0.6 to 9.6 µs (at 7.16 MHz), 61 µs (at 32.768 kHz)Interrupt processing time: 5.4 to 86.4 µs (at 7.16 MHz), 562.5 µs (at 32.768 kHz)

Minimum instruction execution time: 0.6 to 9.6 µs (at 7.16 MHz)Interrupt processing time: 5.4 to 86.4 µs (at 7.16 MHz)

Per

iphe

ral f

unct

ions

Ports Output ports (N-ch open-drain): 5 portsOutput ports (CMOS): 8 portsI/O ports (CMOS): 24 ports (16 ports are also used by resources.)Total: 37 ports

Timebase timer

21 bitsInterrupt period Main clock: 3.58 MHz (2.29 ms, 9.15 ms, 73.22 ms, 1171.59 ms)

Watchdog timer

Minimum reset generation period Main clock: 3.58 MHz (1171.6 ms)7.16 MHz (585.8 ms)Sub-clock: 32.768 kHz (500 ms)

Minimum reset generation period Main clock: 7.16 MHz (585.8 ms)

8/16-bit timer/counter

2/8-bit timer/counter channels (timer 1 and timer 2 have independent operating clocks) or 1/16-bit timer/counter channel (operating clock period = 2.23 µs to 572 µs at 3.58 MHz or 1.13 µs to 286 Éþs at 7.16 MHz)Timer 1 and the 16-bit timer/counter support event counter operation using an external clock and rectangular wave pulse output.

Serial I/O 8-bit operationLSB first/MSB first selectableTransfer clock (an external clock and three internal clocks available: 2.2 µs, 8.9 µs, or 35.8µs at 3.58 MHz or 1.1 µs, 4.5 µs, or 17.9 µs at 7.16 MHz)

Buzzer output

Output frequency Main clock: 3.58 MHz (437 Hz, 874 Hz, 1748 Hz, 3496 Hz)7.16 MHz (874 Hz, 1748 Hz, 3496 Hz, 6992 Hz)Sub-clock: 32.768 kHz (1024 Hz, 2048 Hz, 4096 Hz)

Output frequency Main clock: 7.16 MHz (874 Hz, 1748 Hz, 3496 Hz, 6992 Hz)

External interrupts 1

Three independent channels (edge selection, interrupt vector, request flag, request output enable)Leading edge/trailing edge/both edges selectableUsed also for wake-up from watch/stop/sleep mode. (Edge detection is also permitted in watch/stop mode.)

Three independent channelsLeading edge/trailing edge/both edges selectableUsed also for wake-up from watch/stop/sleep mode.

External interrupts 2 (wake-up)

Eight inputs on one channel ("L" level interrupts, inputs can be enabled independently)Used also for wake-up from watch/stop/sleep mode. (Edge detection is also permitted in watch/stop mode.)

Eight inputs on one channel ("L" level interrupts, inputs can be enabled independently)Used also for wake-up from watch/stop/sleep mode.

Watch prescaler

15 bitsInterrupt period Sub-clock: 32.768 kHz (31.25 ms, 0.25 s, 0.50 s, 1.00 s)

-

DTMF generator

All CCITT tones selectable as outputFixed oscillation frequency (3.58 MHz)

All CCITT tones selectable as outputSelectable oscillation frequency (3.58 MHz/7.16 MHz)

-

Note:Unless the operating clock is explicitly specified, values such as clock periods and conversion times are for a 3.58 MHz main clock operating at maximum speed.

5


1.3 Differences between Models

This section describes the differences between the five models in the MB89170/170A/170L series and points to consider when selecting a model.

Differences between models and the features to consider when selecting a model

Memory space

When evaluating piggyback products, check for differences with the product that will actually beused. (See Section 3.1 "Memory Space".)

Current consumption

• In the case of the MB89PV170A, include the current to be consumed by the EPROM whichis connected to the top socket.

• When operated at low speed, the current consumption of the one-time PROM and EPROMmodels exceeds that of the mask ROM products. However, these current consumptionvalues are similar in sleep and stop modes.

See the electrical characteristics in the Data Sheet for more information on currentconsumption.

Mask options

Functions that can be selected as options and how to designate these options vary with theproduct. Before using options, check APPENDIX C, "MASK OPTIONS."

Take particular note of the following points.

• A pull-up resistor cannot be set for P40 to P44 on the MB89P175A.

• Options are fixed on the MB89PV170A.

Table 1.3-1 Package and corresponding products

Model

Package

MB89173MB89P173MB89174A

MB89P175AMB89173LMB89174L

MB89PV170A

FPT-48P-P02 O X

MQP-48C-P01 X O

O : AvailableX : Not availableFor details on each of packages, see Section 1.6 "Package Dimensions".

6

1.3 Differences between Models

Difference between MB89170/170A and MB89170L series

Table 1.3-2 Difference between MB89170/170A and MB89170L series

Function MB89170/170A 89170L

DTMF generator Available Not available

Clock mode Single clock system/dual clock system selectable<When dual clock system is selected>• Watch mode• Sub-clock mode

Single clock system fixed• No watch mode• No Sub-clock mode

7


1.4 Block diagram of MB89170/170A/170L Series

Figure 1.4-1 "Overall block diagram of MB89170/170A series" shows the overall block diagram of the MB89170/170A series. Figure 1.4-2 "Overall block diagram of MB89170L series" shows the overall block diagram of the MB89170L series.

Overall block diagram of MB89170/170A series

Figure 1.4-1 Overall block diagram of MB89170/170A series

P00/INT20

to P07/INT27

F2MC-8L

R A M

MOD0, MOD1, Vcc, Vss 2Other pins

RST

R O M

Por

t 4

8-bit serial I/O

Buzzer output

N-ch open-drain output ports

P30/SCK

P34/TO/INT0

Inte

rnal

dat

a bu

s

C P U

8-bit timer/counter 1

CMOS I/O ports

Por

t 3



P33/EC

P32/SIP31/SO

P35/INT1

P36/INT2

P37/BZ

P40 to P44

Watch prescaler

5

Reset circuit(Watchdog timer)

DTMF generator DTMF

Oscillation circuitmax 3.58MHz

(A series: 7.16 MHz)

External interrupts 2(Wake-up)

CMOS I/O ports

CMOS I/O ports

Po

rt 0

/1

X0X1

8

P10 to P17

Low-power oscillator circuit(32.768 kHz)

8

Clock controller

Main clock

Sub-clock

16-bit timer/counterX0AX1A

P20 to P278

Timebase timer

Po

rt 2

8

1.4 Block diagram of MB89170/170A/170L Series

Overall block diagram of MB89170L series

Figure 1.4-2 Overall block diagram of MB89170L series

Timebase timer

F2MC-8L

R A M

MOD0, MOD1, Vcc, Vss 2, N.C. 3Other pins

RST

P00/INT20P07/INT27

R O M

Por

t 4

8-bit serial I/O

Buzzer output

N-ch open-drain output ports

P30/SCK

P34/TO/INT0

Inte

rnal

dat

a bu

s

C P U


CMOS I/O portsP

ort 3



P33/EC

P32/SIP31/SO

P35/INT1

P36/INT2

P37/BZ

P40 P445

Reset circuit (Watchdog timer)

Oscillation circuit(max. 3.58 MHz)

External interrupts 2(Wake-up)

CMOS I/O ports

CMOS I/O ports

Po

rt 0

/1

X0X1

8

P10 P178

Clock controller

Main clock

16-bit timer/counter

P20 P278

Po

rt 2

9


1.5 Pin Assignment

Figure 1.5-1 "FPT-48P-M16 pin assignment (MB89170/170A series)", Figure 1.5-2 "FPT-48P-M16 pin assignment (MB89170L series)", and Figure 1.5-3 "MQP-48C-P01 pin assignment (MB89PV170A)" show the pin assignment of the MB89170/170A/170L series.

FPT-48P-M16 pin assignment

Figure 1.5-1 FPT-48P-M16 pin assignment (MB89170/170A series)

123456789101112

DTMFRST

MOD0MOD1

X0X1

VccX0AX1AP27P26P25

363534333231302928272625

P36/INT2P37/BZP00/INT20P01/INT21P02/INT22P03/INT23P04/INT24P05/INT25P06/INT26P07/INT27P10P11

48 47 46 45 44 43 42 41 40 39 38 37

P40

P41

P42

P43

P44

Vss

P30

/SC

KP

31/S

OP

32/S

IP

33/E

CP

34/T

O/IN

T0

P35

/INT

1

13 14 15 16 17 18 19 20 21 22 23 24

P24

P23

P22

P21

P20

P17 Vss

P16

P15

P14

P13

P12

TOP VIEW

MB89170/170A Series

FPT-48P-M16

10

1.5 Pin Assignment

Figure 1.5-2 FPT-48P-M16 pin assignment (MB89170L series)

RSTMOD0MOD1

X0X1

Vcc

P27P26P25

123456789101112

363534333231302928272625


48 47 46 45 44 43 42 41 40 39 38 37

P40

P41

P42

P43

P44

Vss

P30

/SC

KP

31/S

OP

32/S

IP

33/E

CP

34/T

O/IN

T0

P35

/INT

1

13 14 15 16 17 18 19 20 21 22 23 24

P24

P23

P22

P21

P20

P17 Vss

P16

P15

P14

P13

P12

TOP VIEW

MB89170L Series

FPT-48P-M16

N.C.

N.C.N.C.

11


MQP-48C-P01 pin assignment

Figure 1.5-3 MQP-48C-P01 pin assignment (MB89PV170A)

123456789101112

DTMFRST

MOD0MOD1

X0X1

VccX0AX1AP27P26P25

363534333231302928272625


48 47 46 45 44 43 42 41 40 39 38 37

P40

P41

P42

P43

P44

Vss

P30

/SC

KP

31/S

OP

32/S

IP

33/E

CP

34/T

O/IN

T0

P35

/INT

1

13 14 15 16 17 18 19 20 21 22 23 24

P24

P23

P22

P21

P20

P17 Vss

P16

P15

P14

P13

P12

TOP VIEW

6970717273747576

6059585756555453

68 67 66 65 64 63 62 61

77 78 79 80 49 50 51 52

Pin No.

49

50

51

52

53

54

55

56

Pin No.

57

58

59

60

61

62

63

64

Pin No.

65

66

67

68

69

70

71

72

Pin No.

73

74

75

76

77

78

79

80

Name

VPP

A12

A7

A6

A5

A4

A3

N.C.

Name

N.C.

A2

A1

A0

O1

O2

O3

VSS

Name

O4

O5

O6

O7

O8

CE

A10

N.C.

Name

OE

N.C.

A11

A9

A8

A13

A14

VCC

Caution: Pin assignment on package top (MB89PV170A)

N.C. : Internal connection. Leave it open.

12

1.6 Package Dimensions

1.6 Package Dimensions

Two types of package are used by the MB89170/170A/170L series.Figure 1.6-1 "FPT-48P-M16 package dimensions" and Figure 1.6-2 "MQP-48C-P01 package dimensions" show the package dimensions.

FPT-48P-M16 package dimensions

Figure 1.6-1 FPT-48P-M16 package dimensions

48-pin plastic QFP Lead pitch 0.80 mm

Package width package length

12 12 mm

Lead shape Gullwing

Sealing method Plastic mold

48-pin plastic QFP(FPT-48P-M16)

(FPT-48P-M16)

C 2000 FUJITSU LIMITED F48026S-1C-2

Details of "A" part

17.20±0.40

0.30±0.06(.012±.002)

0.16(.006) M

13.60±0.408.80

(.535±.016)(.346)REF

0.15(.006)

INDEX

Details of "B" part

121

2536

37 24

1348

0.80(.0315)TYP

LEAD No.

(.677±.016)SQ

SQ

"A"

0.15(.006)

0.20(.008)

0.50(.020)MAX

0.15(.006)MAX

1.80±0.30(.071±.012)

"B"

(STAND OFF)0.05(.002)MIN

.472+.012

+0.3012.00

.006+.002

+0.050.15

2.70(.106)MAX(Mounting height)

Dimensions in mm (inches).

13


MQP-48C-P01 package dimensions

Figure 1.6-2 MQP-48C-P01 package dimensions

48-pin ceramic MQFP Lead pitch 0.8 mm

Lead shape Straight

Motherboard material

Ceramic

Mounted package material

Plastic

48-pin ceramic MQFP(MQP-48C-P01)

(MQP-48C-P01)

C 1994 FUJITSU LIMITED M48001SC-4-2

14.82±0.35(.583±.014)

15.00±0.25(.591±.010)

17.20(.677)TYP

PIN No.1 INDEX

.430 –0+.005

–0.0+0.13

10.92

1.02±0.13(.040±.005)

7.14(.281) 8.71(.343)TYPTYP

0.30(.012)TYP4.50(.177)TYP

PAD No.1 INDEX

0.15±0.05(.006±.002)

8.50(.335)MAX

0.60(.024)TYP1.10+0.45–0.25

+.018–.010.043

0.40±0.08(.016±.003)

0.80±0.22(.0315±.0087)

8.80(.346)REF

1.00(.040)TYP

1.50(.059)TYP

PIN No.1 INDEX

Dimensions in mm (inches).

14

1.7 Pin Descriptions


Table 1.7-1 "Pin descriptions ", Table 1.7-2 "Pin descriptions for the external EPROM connector (MB89PV170A only)" list the I/O pins and their functions.The letters listed in the "I/O circuit type" column of Table 1.7-1 "Pin descriptions " and Table 1.7-2 "Pin descriptions for the external EPROM connector (MB89PV170A only)" correspond to the letters in the "Type" column of Table 1.8-1 "I/O circuit types ".

I/O pins and their functions

Table 1.7-1 Pin descriptions

Pin No.

Pin nameI/O circuit

typeFunctionQFP *1

MQFP *2

5 X0

A

These pins are used to connect a crystal or other oscillator for the main clock.If using an external clock, input the clock to X0 and leave X1 open.

6 X1

8 X0A

B

These pins are used to connect a crystal or other oscillator for the sub-clock.If using an external clock (32.768 kHz low frequency clock), input the clock to X0A and leave X1A open.

9 X1A

3 M0D0C

Input pins for setting the memory access mode.Connect directly to Vss.

4 M0D1

2 RST D

Reset I/O pin. This pin is an N-ch open-drain output type with a pull-up resistor and a hysteresis input type. "L" is output from this pin with an internal reset request (option). The internal circuit is initialized by inputting "L."

34 to 27P00/INT20 to

P07/INT27E

General-purpose I/O ports. Also serve as external interrupt 2 input (wake-up input). These ports are hysteresis input types.

26 to 20,18 P10 to P17 F General-purpose I/O ports.

17 to 10 P20 to P27 H General-purpose output ports.

42 P30/SCK GGeneral-purpose I/O port. Also serves as the clock I/O pin for the serial I/O. This port is a hysteresis input type.

41 P31/S0 GGeneral-purpose I/O port. Also serves as the data output pin for the serial I/O. This port is a hysteresis input type.

40 P32/SI GGeneral-purpose I/O port. Also serves as the data input pin for the serial I/O. This port is a hysteresis input type.

39 P33/EC GGeneral-purpose I/O port. Also serves as the external clock output pin for the 8/16-bit timer/counter. This port is a hysteresis input type.

15


Caution:

In the case of the MB89170L series, the following pins are the N.C. pins.

- Pin 1 (DTM pin)

- Pin 8 (X0A pin)

- Pin 9 (X1A pin)

38 P34/T0/INT0 GGeneral-purpose I/O port. Also serves as the overflow output pin for the 8/16-bit timer/counter and an input pin for external interrupt 1. This port is a hysteresis input type.

3736

P35/INT1P36/INT2

GGeneral-purpose I/O ports. Also serves as the input pin for external interrupt 1. These ports are hysteresis input types.

35 P37/BZ GGeneral-purpose I/O port. Also serves as a buzzer output pin. This port is a hysteresis input type.

48 to 44 P40 to P44 I General-purpose N-ch open-drain output ports.

1 DTMF J DTMF signal output pin

7 Vcc - Power supply pin

19, 43 Vss - Power supply (GND) pins

*1 : FPT-48P-M16*2 : MQP-48C-P01

Table 1.7-1 Pin descriptions (Continued)

Pin No.

Pin nameI/O circuit

typeFunctionQFP *1

MQFP *2

Table 1.7-2 Pin descriptions for the external EPROM connector (MB89PV170A only)

Pin No. Pin name I/O Function

49 Vpp 0 "H" level output pin

505152535455585960

A12A7A6A5A4A3A2A1A0

0 Address output pins

616263

010203

I Data input pins

64 Vss 0 Power supply (GND) pin

16


6566676869

0405060708

I Data input pins

70 CE 0ROM chip enable pin.Outputs "H" during standby.

71 A10 0 Address output pin

73 OE 0ROM output enable pin.Outputs "L" at all times.

757677

A11A9A8

0

Address output pins78 A13 0

79 A14 0

80 Vcc 0 EPROM power supply pin

56, 5772, 74

N. C. -Internal connection pins.Be sure to leave them open.

Table 1.7-2 Pin descriptions for the external EPROM connector (MB89PV170A only) (Continued)

Pin No. Pin name I/O Function

17


1.8 I/O Circuit Types

Table 1.8-1 "I/O circuit types " list the I/O circuit types.The letters in the "Type" column of Table 1.8-1 "I/O circuit types " correspond to the letters listed in the "I/O circuit type" column of Table 1.7-1 "Pin descriptions ".

I/O circuit types

Table 1.8-1 I/O circuit types

Type Circuit Remarks

A

Used for the high speed clock (main clock source oscillation).• Oscillation feedback resistor

Approx. 1 MΩ (at 5V)

B

Used for the low speed clock (sub-clock source oscillation).• Oscillation feedback resistor Approx.

4.5 MΩ (at 5 V)• The switch is open when the single-

clock option is selected.

C

D

• Output pull-up resistor (P-ch) Approx. 50 kΩ (at 5 V)

• Hysteresis input

Nch

Nch

X1

X0 Pch

Pch

Main clock control signal

Nch

Nch

X1A

X0A

Pch

Sub-clock control signal

Nch

R

Pch

Nch

18

1.8 I/O Circuit Types

E

• CMOS output• CMOS input• Hysteresis input• A pull-up resistor is optional.

Approx. 50 kΩ (at 5 V) (Excluding MB89PV170A)

F

• CMOS output• CMOS input• A pull-up resistor is optional.


G

• CMOS output• Hysteresis input• A pull-up resistor is optional.


H

• CMOS output

Table 1.8-1 I/O circuit types (Continued)


Pch

Pch

NchPort

Resource

R

Pch

R

Pch

Nch

Pch

R

Pch

Nch

Pch

Nch

19


I

• N-ch open-drain output• A pull-up resistor is optional.


J

• DTMF analog output

Table 1.8-1 I/O circuit types (Continued)


Nch

Pch

R

OPAMP

20

CHAPTER 2 HANDLING DEVICES

This chapter describes precautions to observe when handling the general-purpose single-chip microcontroller.

2.1 "Handling Devices"

21

CHAPTER 2 HANDLING DEVICES

2.1 Handling Devices

This section describes points to note such as the power supply voltage of devices and treatment of pins.

Notes on handling devices

Maximum rated voltage (latch-up prevention).

Do not exceed the maximum rated voltage.

The latch-up phenomenon occurs if a voltage higher than Vcc, lower than Vss, or between Vccand Vss but still in excess of the rated voltage is applied to the input or output pins of a CMOSIC, other than those rated for a medium- or high-withstand voltage.

When latch-up occurs, the supply current spikes up rapidly to the point where circuit elementsmay be damaged with heat; therefore, when using CMOS ICs, it is important not to exceed themaximum ratings.

Supply voltage

Ensure that the supply voltage is as stable as possible.

Sudden changes in the Vcc supply voltage may cause misoperation, even if the voltage remainswithin the operation assurance range.

As criteria for operational stability, Fujitsu recommends that the Vcc ripple fluctuation (peak topeak value) at line frequencies (50 to 60 Hz) be kept to 10% or less of the standard Vcc level,and that during momentary variations, such as when the power is turned on or off, the powersupply be suppressed so that the rate of transient fluctuation rate is 0.1 V/ms or less.

Treatment of unused input pins

Misoperation may occur if input pins that are not used are left open; therefore, connect pull-upor pull-down resistors to unused input pins.

Treatment of N.C. pins

Always leave N.C. (internal connection) pins open.

Note on use of an external clock

When an external clock is used, time is allowed for oscillation stabilization delay time in theevent of a power-on reset (optional) or wake-up from sub-clock mode or stop mode.

Booting up supply voltage (MB89P175A only)

After the start of oscillation, within 13 clocks, boot up the power supply abruptly to the voltage (2V) where optional operation is available.

22

CHAPTER 3 CPU

This chapter describes the functions and operation of the CPU.

3.1 "Memory Space"

3.2 "Dedicated Registers"

3.3 "General-Purpose Registers"

3.4 "Interrupts"

3.5 "Reset"

3.6 "Clock"

3.7 "Standby Modes (Low Power Consumption)"

3.8 "Memory Access Mode"

23

CHAPTER 3 CPU

3.1 Memory Space

The MB89170/170A /170L series has a 64-K byte memory space which consists of the I/O area, RAM area, ROM area, and external area. The memory space also includes areas with special uses such as the general-purpose registers and vector table.

Structure of the memory space

I/O area (address: 0000 H to 007FH)

• It is allocated for the control registers, data registers, etc., for internal peripheral functions.

• Because the I/O area is a part of the memory space, it can be accessed in the same manneras memory. It can also be accessed at high speed via direct addressing.

RAM area

• Static RAM is built in for an internal data area.

• Internal RAM size differs with the model.

• The area from 80H to FFH can be accessed at high speed by direct addressing. (Usableareas are restricted for each model.)

• The area from 100H to 1FFH can be used as a general-purpose register area.

• The RAM data becomes undefined after a reset.

ROM area

• ROM is built in for an internal program area.

• Internal ROM size differs with the model.

• The area from FFC0H to FFFFH is used for the vector table.

24

3.1 Memory Space

Memory map

Figure 3.1-1 Memory map

Vector table (resets, interrupts, vector call instruction)

0000 H

0080 H

0100 H

8000 H

MB89PV170A

I/O

RAM

Registers

External ROM

0000 H

0080 H

0100 H

0200 H

C000 H

FFFF H

MB89P175A

I/O

RAM

Registers

ROM

FFFF H

0200 H

Registers

0200 H

Registers

Access disabled

Access disabled

Access disabled

0280 H

BFF0 H

0280 H

0200 H

FFC0 HFFC0 H

0480 H

0000 H

0080 H

0100 H

D000 H

FFFF H

MB89174AMB89174L

I/O

RAM

Access disabled

ROM

FFC0 H

0000 H

0080 H

0100 H

E000 H

FFFF H

MB89P173MB89173MB89173L

I/O

RAM

Access disabled

ROMFFC0 H

25

CHAPTER 3 CPU

3.1.1 Special-purpose areas

In addition to the I/O area, the device contains two other special-purpose areas: the general-purpose register area and the vector table area.

General-purpose register area (address: 0100 H to 01FFH)

• Used for 8-bit arithmetic and transfer operations as auxiliary registers.

• As the area is allocated to a part of the RAM area, it can also be used as the ordinary RAMarea.

• If this area is used for general-purpose registers, general-purpose register addressingenables the area to be accessed at high speed using short instructions.

See Sections 3.2.2 "Register bank pointer (RP)" and 3.3 "General-Purpose Registers" for moreinformation.

Vector table area (address: FFC0 H to FFFFH)

• Used as the vector table for the vector call instruction, interrupts, and resets.

• The area is assigned to the top of the ROM area. Set the start addresses of the associatedprocessing routines as data at their respective vector table addresses.

Table 3.1-1 "Vector table" lists the corresponding vector table addresses to be referenced forthe vector call instruction, interrupts, and resets.

See Sections 3.4 "Interrupts" and 3.5 "Reset", and Item (6), "CALLV #vct" in Appendix B.2,"Special Instructions" for more information.

Table 3.1-1 Vector table

Vector call instructionVector table address

Upper Lower

CALLV #0 FFC0H FFC1H





CALLV #5 FFCAH FFCBH

CALLV #6 FFCCH FFCDH

CALLV #7 FFCEH FFCFH

26

3.1 Memory Space

Mode dataVector table address

Upper Lower

IRQB FFE4H FFE5H

IRQA FFE6H FFE7H

IRQ9 FFE8H FFE9H

IRQ8 FFEAH FFEBH

IRQ7 FFECH FFEDH

IRQ6 FFEEH FFEFH

IRQ5 FFE0H FFE1H

IRQ4 FFE2H FFE3H

IRQ3 FFE4H FFE5H

IRQ2 FFE6H FFE7H

IRQ1 FFE8H FFE9H

IRQ0 FFEAH FFEBH

Mode data - (*1) FFEDH

Reset vector FFEEH FFEFH

*1 Use of FFFCH is prohibited. (Set FFH.)

27

CHAPTER 3 CPU

3.1.2 Allocation of 16-bit data in memory

The upper data of the 16-bit data and stack is stored in the smaller address on memory.

Storage of 16-bit data on RAM

When 16-bit data is written to memory, the upper byte of the data is stored in the lower addressand the lower byte is stored in the next higher address. This data is read in the same manner.

Figure 3.1-1 "Allocation of 16-bit data in memory" shows how 16-bit data is allocated in memory.

Figure 3.1-2 Allocation of 16-bit data in memory

Storage of 16-bit data on RAM

When a 16-bit specification is made for an operand in an instruction, the upper byte is stored inthe address closer to the operation code (instruction), and the lower byte is stored in the nexthigher address.

The same allocation applies when the operand represents a memory address or 16-bitimmediate data.

Figure 3.1-3 "Allocation of 16-bit data in instruction" shows how 16-bit data is stored ininstructions.

Figure 3.1-3 Allocation of 16-bit data in instruction

Storing 16-bit data on the stack

In the same manner, when data of a 16-bit register is saved in the stack due to an interrupt, theupper byte is stored in the smaller address.

Before execution

A 1 2 3 4 H

Memory

0080H

0081H

0082H

0083H

After execution

A 1 2 3 4 H

Memory

0080H

0081H

0082H

0083H

12H

34H

MOVW 0081H, A

[Example] MOV A, 5678H ; Extended address MOVW A, #1234H ;16-bit immediate data

After assembly

XXX0H XX XXXXX2H 60 56 78 ;Extended addressXXX5H E4 12 34 ;16-bit immediate dataXXX8H XX

28

3.2 Dedicated Registers


The dedicated registers in the CPU consist of the programmer counter (PC), two operation registers (A and T), three address pointers (IX, EP, and SP), and the program status (PS). All registers are 16 bits.

Structure of the dedicated registers

The dedicated registers in the CPU consist of seven 16-bit registers.

Only the lower 8 bits of some of these registers can also be used.

Figure 3.2-1 "Structure of dedicated registers" shows the structure of the dedicated registers.

Figure 3.2-1 Structure of dedicated registers

P C

A

T

I X

E P

S P

:

:

:

:

:

:

:

AccumulatorTemporary storage register for arithmetic and transfer operations

Program counterPoints to the address of the current instruction.

Temporary accumulatorUsed to perform operations with the accumulator.

Index registerRegister that holds the index address.Extra pointerMemory address pointer

Stack pointerPoints to the current stack position.

Program statusContains the register bank pointer and condition code.

16 bits

R P CCR

P S

I-flag = "0"IL1, IL0 = "11"Other bits: Undefined.

Undefined

Undefined

Undefined

Undefined

Undefined

FFFDH

Initial value

29

CHAPTER 3 CPU

Functions of dedicated registers

Program counter (PC)

The program counter is a 16-bit counter which points to the memory address of the instructioncurrently being executed by the CPU. The contents of the program counter are changed byinstruction execution, interrupts, resets, and other events. The initial value after a reset is theaddress (FFFDH) for reading the mode data.

Accumulator (A)

The accumulator is a 16-bit operation register used to perform arithmetic and transferoperations with data in memory or data in other registers such as the temporary accumulator(T). The data in the accumulator can be treated as word-length (16-bit) or byte-length (8-bit)data. Only the lower 8 bits (AL) of the accumulator are used for byte-length arithmetic ortransfer operations. In this case, the upper 8 bits (AH) remain unchanged. The initial valueafter a reset is undefined.

Temporary accumulator (T)

The temporary accumulator is an auxiliary 16-bit operation register used to perform a variety ofoperations on the data in the accumulator (A). The data in the temporary accumulator is treatedas word-length (16-bit) data for word-length operations on the accumulator (A), and as byte-length (8-bit) data for byte-length operations. If byte-length operations are performed, only thelower 8 bits (TL) of the temporary accumulator are used and the upper 8 bits (TH) are unused.

If one of the MOV instructions is used to transfer data to the accumulator (A), the previous dataof the accumulator is automatically transferred to the temporary accumulator. In this case also,the upper 8 bits (TH) of the temporary accumulator do not change for a byte-length transfer.The initial value after a reset is undefined.

Index register (IX)

The index register is a 16-bit register used to store the index address. The index register isused with a 1-byte offset value (-128 to +127). The memory address for data access isgenerated by adding the sign-extended offset to the index address. The initial value after areset is undefined.

Extra pointer (EP)

The extra pointer is a 16-bit register used to store the memory address for data access. Theinitial value after a reset is undefined.

Stack pointer (SP)

The stack pointer is a 16-bit register used to store the address referenced by operations such asinterrupts, subroutine calls, stack save and restore instructions. The value of the stack pointerduring program execution is the address at which the latest data is saved on the stack. Theinitial value after a reset is undefined.

Program status (PS)

The program status is a 16-bit control register. The upper 8 bits contain the register bankpointer (RP) used to specify the address of the general-purpose register bank.

The lower 8 bits contain the condition code register (CCR) which contains a variety of flagsrepresenting the state of the CPU. The two 8-bit registers are part of the program status andcannot be accessed independently. (Only the MOVW A, PS and MOVW PS, A instructions canbe used to access the program status.)

30


Refer to the "F2MC-8L MB89600 Series Programming Manual" for more information on how touse the dedicated registers.

31

CHAPTER 3 CPU

3.2.1 Condition code register (CCR)

The condition code register (CCR) comprises the lower 8 bits of the program status (PS). The CCR contains bits (C, V, Z, N, and H) that indicate operation results or the content of transfer data and bits that control whether interrupt requests are accepted (I, IL1, and IL0).

Structure of the condition code register (CCR)

Figure 3.2-2 Structure of the condition code register

Operation result indicator bits

Half-carry flag (H)

This flag is set to "1" when a carry from bit 3 to bit 4 or a borrow from bit 4 to bit 3 occurred asthe result of an operation, and is cleared to "0" at all other times.

This flag is used for decimal auxiliary instructions; do not use this flag for applications other thanadd and subtract operations.

Negative flag (N)

This flag is set to "1" when the most significant bit of the result of an operation is "1", and iscleared to "0" when the most significant bit is "0".

Zero flag (Z)

This flag is set to "1" when the result of an operation is "0", and is cleared to "0" in all othercases.

Overflow flag (V)

This flag is set to "1" when the result of an operation caused a two’s complement overflow, andis cleared to "0" when it did not.

Carry flag (C)

This flag is set to "1" when the result of an operation caused a carry from bit 7 or a borrow to bit

Negative flagInterrupt level bitsInterrupt enable flagHalf-carry flag

Carry flagOverflow flagZero flag

R4 R2 R1 R0R3

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8

H I IL1 IL0 N Z V C

CCR


PS

RP

X011XXXXB

CCR initial value

X: Undefined

32


7, and is cleared to "0" when it did not.

In the case of a shift instruction, the C flag assumes the value of the bit that was shifted out.Figure 3.2-3 "Carry flag change for shift instructions" shows how the carry flag changes for shiftinstructions.

Figure 3.2-3 Carry flag change for shift instructions

Caution:

The condition code register is part of the program status (PS) and cannot be accessedindependently.

Note:

The flag bits are not read and used directly. Instead, the flags are usually used indirectly insuch instructions as branch instructions (BNZ, etc.) and decimal adjustment instructions(DAA and DAS). The initial value of the flags after a reset is undefined.

Bits that control the acceptance of interrupts

Interrupt enable flag (I)

When this flag is "1", interrupts are enabled and the CPU accepts interrupts. When the flag is"0", interrupts are disabled and the CPU does not accept interrupts.

The initial value after a reset is "0".

The flag is usually set to "1" by the SETI instruction, and is cleared to "0" by the CLRIinstruction.

Interrupt level bits (IL1, IL0)

These bits specify the level of interrupts that the CPU is currently accepting. The bits arecompared to the values in the interrupt level setting registers (ILR1 to ILR3) which containsettings for each peripheral function interrupt request (IRQ0 to IRQB).

If the interrupt enable flag is enabled (I = 1), the CPU processes only interrupts with an interruptlevel value that is less than the value of these bits. Table 3.2-1 "Interrupt levels" lists theinterrupt priorities. The initial value after a reset is "11".

Note:

The interrupt lever bits (IL1, IL0) normally have the value "11" when the CPU is not

bit7 bit0

C

bit7 bit0

C

- Left shift (ROLC) - Right shift (RORC)

Table 3.2-1 Interrupt levels

IL1 IL0 Interrupt level Priority

0 01 High

Low (no interrupt)

0 1

1 0 2

1 1 3

33

CHAPTER 3 CPU

processing an interrupt (while executing the main program).

See Section 3.4 "Interrupts" for more information on interrupts.

34


3.2.2 Register bank pointer (RP)

The register bank pointer (RP) is located in the upper 8 bits of the program status (PS). The RP specifies the address of the general-purpose register bank currently in use. The RP is converted to an actual address when general-purpose register addressing is used.

Structure of the register bank pointer (RP)

Figure 3.2-4 "Structure of the register bank pointe" shows the structure of the register bankpointer.

Figure 3.2-4 Structure of the register bank pointer

The register bank pointer specifies the address of the register bank currently in use. Figure 3.2-5 "Actual address conversion rule for the general-purpose register area" shows the addressconversion rule that relates the content of the register bank pointer to the actual address.

Figure 3.2-5 Actual address conversion rule for the general-purpose register area

The register bank pointer specifies the memory block (register bank) in the RAM area that isused for the general-purpose registers. A total of 32 register banks are available. The value (0to 31) set in the upper 5 bits of the register bank pointer specifies which register bank to use.One register bank consists of eight 8-bit general-purpose registers. Individual registers can bespecified with the lower three bits of the operation code.

The register bank pointer enables the area between 0100Hand up to 01FFH to be used as thegeneral-purpose register area. However, depending on the model, the available memory areais restricted when only the internal RAM is used. The initial value after a reset is undefined.

Caution:

- Always set the register bank pointer (RP) before using the general-purpose registers.

- The register bank pointer is part of the program status (PS) and cannot be accessedindependently.

R4 R2 R1 R0R3


H I IL1 IL0 N Z V C

CCR


PS

RP

XXXXXXXXB

RP initial value

X: Undefined

"0" "0" "0" "1""0" "0" "0" "0" R0 b2 b1 b0R4 R3 R2 R1

A11 A10 A9 A8A15 A14 A13 A12 A3 A2 A1A7 A6 A5 A4 A0Generated addresses

Upper RP Low operation code

35

CHAPTER 3 CPU

3.3 General-Purpose Registers

The general-purpose registers are a memory block consisting of eight 8-bit registers per bank. Use the register bank pointer (RP) to specify the register bank.Functionally, all 32 register banks can be used. If the size of the internal RAM is too small to contain all banks, the external RAM can be used for the remaining banks. The register bank mechanism is useful in the processing of interrupts, vector calls, and subroutine calls.

Structure of the general-purpose registers

• The general-purpose registers are 8-bit registers and are located in register banks in thegeneral-purpose register area (in RAM).

• One bank contains eight registers (R0 to R7) and a total of 32 banks are available.However, depending on the model, the number of available banks is restricted when usingonly the internal RAM.

• The register bank pointer (RP) specifies the general-purpose register bank currently in useand the lower three bits of the operation code specify general-purpose register 0 (R0) togeneral-purpose register 7 (R7).

Figure 3.3-1 "Structure of the register banks" shows the structure of the register banks.

Figure 3.3-1 Structure of the register banks

*1 Top address of register bank = 0100H + 8x (upper 5 bits of RP)

000

001

010

011

100

101

110

111

000

:

111

:::

Bank 31(RP="11111---B")

32 banks (RAM area)

Bank 1(RP="00001---B")

Bank 0(RP="00000---B")

Bank2 toBank 30

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

R 0

:

R 7

:::

R 0

100H (*1)

108H(*1)

1F8H(*1)

1FFH

Lower 3 bits of operation code

The number of available banks is restricted by the size of available RAM.

R 7

000

111

::

36

3.3 General-Purpose Registers

See Section 3.1.1 "Special-purpose areas" for more information on available general-purposeregister area for each model.

General-purpose register features

The general-purpose registers have the following features:

• RAM can be accessed at high speed using short instructions (general-purpose registeraddressing).

• Registers are grouped into banks. This simplifies protecting register contents and groupingregisters by function.

A specific register can be permanently assigned as the general-purpose registers for eachinterrupt processing routine or vector call (CALLV #0 to #7) processing routine. For example,register bank 4 can be used for interrupt 2.

In the case of an interrupt, assume that the contents of the register bank used by the processingroutine for that interrupt are not unintentionally updated by other routines. In this case, thecontents of the general-purpose registers prior to the interrupt occurrence can be saved simplyby selecting the interrupt-specific register bank at the start of the interrupt processing routine.This eliminates the need to save the general-purpose registers on the stack or elsewhere andenables interrupts to be handled at high speed without interfering with other operations.

Also, in addition to protecting general-purpose register contents, it is also possible to useregister banks to write reentrant subroutine call programs (programs for which the addresses ofvariables are not fixed and which allow re-entry) which are usually written using the indexregister (IX).

Caution:

If the register bank pointer (RP) is written to specify the register bank in an interruptprocessing routine, ensure that the program is written such that the interrupt level bits of thecondition code register (CCR:IL1 and IL0) are not changed.

37

CHAPTER 3 CPU

3.4 Interrupts

The MB89170/170A/170L series has eight interrupt request inputs (MB89170/170A series) and seven interrupt request inputs (MB89170L series) from peripheral functions. Interrupt levels can be set independently for each interrupt.The interrupt controller compares the interrupt levels of interrupt requests generated by peripheral functions for which output of interrupt requests is enabled. The CPU performs the interrupt operation depending on the interrupt acceptance state. Interrupt requests can also be used to wake-up from standby modes and restore interrupt operation or normal operation.

Interrupt requests from peripheral functions

Table 3.4-1 "Interrupt requests and interrupt vectors" lists the interrupt requests from peripheralfunctions. If an interrupt is accepted, execution branches to the interrupt processing routine atthe branching address specified by the contents of the vector table address for that interruptrequest.

The interrupt level setting registers (ILR1, ILR2, and ILR3) set the interrupt processing priorityfor each interrupt request to one of three priority levels.

If, during execution of an interrupt processing routine, an interrupt request with a level that isequal or lower than that of the current interrupt occurs, the new interrupt is not processed untilafter the current interrupt processing routine is completed. IRQ0 has the highest priority ifinterrupt requests with the same level occur simultaneously.

Table 3.4-1 Interrupt requests and interrupt vectors

Interrupt request

Vector table addressBit names in the

interrupt level setting registers

Priority of interrupts of same level (when

interrupts occur simultaneously)

Upper Lower

IRQ0 (external interrupt 1-0) FFFAH FFFBH L01, L00 High

IRQ1 (external interrupt 1-1) FFF8H FFF9H L11, L10

IRQ2 (external interrupt 1-2) FFF6H FFF7H L21, L20

IRQ3 (8/16-bit timer/counter) FFF4H FFF5H L31, L30

IRQ4 (8-bit serial I/O) FFF2H FFF3H L41, L40

IRQ5 (unused) FFF0H FFF1H L51, L50

IRQ6 (timebase timer) FFFEH FFFFH L61, L60

IRQ7 (watch prescaler) FFFCH FFFDH L71, L70

IRQ8 (unused) FFFAH FFFBH L81, L80

IRQ9 (unused) FFF8H FFF9H L91, L90

Low

IRQA (external interrupt 2) FFF6H FFF7H LA1, LA0

IRQB (unused) FFF4H FFF5H LB1, LB0

Note:The interrupt request of IRQ7 (watch prescaler) becomes unused for the MB89170L series.

38

3.4 Interrupts

3.4.1 Interrupt level setting registers (ILR1, ILR2, and ILR3)

The interrupt level setting registers (ILR1, ILR2, and ILR3) contain twelve 2-bit data items. Each data item corresponds to an interrupt request from a peripheral function. The 2-bit data (interrupt level setting bits) is used to set the interrupt level for each interrupt request.

Structure of the interrupt level setting registers (ILR1, ILR2, and ILR3)

Figure 3.4-1 "Structure of the interrupt level setting registers" shows the structure of the interruptlevel setting registers.

Figure 3.4-1 Structure of the interrupt level setting registers

The interrupt level setting registers contain a 2-bit value for each interrupt request. The valuesof the interrupt level setting bits in these registers set the interrupt priorities (interrupt levels: 1to 3).

The interrupt level setting bits are compared with the interrupt level bits in the condition coderegister (CCR:IL1 and IL0).

The CPU does not accept an interrupt request if the interrupt is set to interrupt level 3.

Table 3.4-2 "Relationship between the interrupt level setting bits and interrupt levels" lists therelationship between the interrupt level setting bits and interrupt levels.

L31 L21 L20 L11 L10 L01 L00


0 0 7 CH

Address

11111111B

Initial value

L30

Register

ILR1

L71 L61 L60 L51 L50 L41 L400 0 7 DH 11111111BL70ILR2

LB1 LA1 LA0 L91 L90 L81 L800 0 7 EH 11111111BLB0ILR3

W: Write-only

WW W W W WWW

WW W W W WWW

WW W W W WWW

Table 3.4-2 Relationship between the interrupt level setting bits and interrupt levels

L01 to LB1 L00 to LB0 Request interrupt level Priority

0 01

High

Low (no interrupt)

0 1

1 0 2

1 1 3

39

CHAPTER 3 CPU

Note:

The value of the interrupt level bits in the condition code register (CCR:IL1 and IL0) isusually "11" during execution of the main program.

Caution:

As the ILR1, ILR2, and ILR3 registers are write-only, bit manipulation instructions (SETB andCLRB) cannot be used.

40

3.4 Interrupts

3.4.2 Processing during an interrupt

When an interrupt request from a peripheral function occurs, the interrupt controller passes the interrupt level to the CPU. If the CPU is able to accept the interrupt, the currently running program is temporarily halted and the interrupt processing routine is executed.

Processing during an interrupt

The procedure for interrupts is performed in the following order: an interrupt occurs in aperipheral function, the interrupt request flag bit (request FF) is set, the interrupt request enablebit (enable FF) is checked, the interrupt levels (ILR1, ILR2, ILR3, and CCR:IL1, IL0) arechecked, simultaneous requests of the same level are checked, and the interrupt enable flag(CCR:I) is checked.

Figure 3.4-2 "Processing during an interrupt" shows the processing when an interrupt occurs.

Figure 3.4-2 Processing during an interrupt

Inte

rnal

bus

IPLA

Register file

IR

Check Comparator

RAM

Enable FF

Request FFAND

Leve

l com

para

tor

PeripheralInterrupt controller

F2MC-8L.CPU

.

.

.

(4)

(4)

(3)

(7)

(5)

PS I IL

(6)

Condition code register (CCR)

START

Interrupt request from peripherals?

Evaluate interrupt priority order and pass interrupt level to CPU

Initialize peripherals

NO Is output of the interrupt request from

the peripheral enabled?

NO

YES

Compare interrupt level with IL bit in PS

Is priority of the interrupt level higher

than that of IL bits? I flag = 1?

YES

YES

NO

NO

Save PC and PS on stack

PC <--interrupt vector

Update IL in PS

YES(3)

(1)

(5)

(6)

Wake-up from stopWake-up from sleep

Interrupt processing routine

Clear interrupt request

Execute interrupt processing

RETI

Restore PC and PS(7)

Wake-up from watch mode

Execute main program

(2)

41

CHAPTER 3 CPU

1. After a reset, all interrupt requests are disabled. In the peripheral initialization program,initialize the peripheral functions that are to generate interrupts and set the interrupt level inthe corresponding interrupt level setting register (ILR1, ILR2, or ILR3) before startingoperation of the peripheral function. The interrupt level can be set to 1, 2, or 3. Level 1 isthe highest priority and level 2 is the next highest. Setting level 3 disables the correspondingperipheral function interrupt.

2. Execute the main program (or the interrupt processing routine in the case of multipleinterrupts).

3. When an interrupt occurs in the peripheral function, the interrupt request flag bit (request FF)of the peripheral function is set to "1". If the interrupt request enable bit for the peripheralfunction is enabled (enable FF = 1), the interrupt request is output to the interrupt controller.

4. The interrupt controller continuously monitors the interrupt requests from the peripheralfunctions. The interrupt controller selects the interrupt level with the highest priority amongthe interrupt levels corresponding to the currently present interrupt requests and passes thislevel to the CPU. The interrupt controller also evaluates the priority of any requests of thesame level that have occurred simultaneously.

5. Assume that the priority of the interrupt level received by the CPU is higher than the priorityof the level set in the interrupt level bits of the condition code register (CCR:IL1, IL0) (forcases where the received level value is lower). In this case, the CPU checks the value of theinterrupt enable flag (CCR:I) and accepts the interrupt if interrupts are enabled (CCR:I = 1).

6. The contents of the program counter (PC) and program status (PS) are saved on the stack.The start address of the interrupt processing routine is fetched from the correspondinginterrupt vector table. The value of the interrupt level bit of the condition code register(CCR:IL1, IL0) is changed to the value of the received interrupt level. Then, execution of theinterrupt processing routine starts.

7. Finally, the RETI instruction restores the values of the program counter (PC) and programstatus (PS) saved on the stack and continues execution from the next instruction followingthe instruction executed prior to the interrupt.

Caution:

The interrupt requests flag bits for peripheral functions are not automatically cleared whenthe interrupt request is accepted. Therefore, the flag must be cleared by a program in theinterrupt processing routine (usually by writing "0" to the interrupt request flag bit).

Standby mode (low-power consumption mode) is switched by an interrupt. See Section 3.7"Standby Modes (Low Power Consumption)" for more information.

Note:

If the interrupt request flag bit is cleared at the start of the interrupt processing routine, theperipheral function having generated the current interrupt is able to generate anotherinterrupt during execution of the interrupt processing routine (set the interrupt request flag bitagain). However, the new interrupt is not normally accepted until the current interruptprocessing routine is completed.

42

3.4 Interrupts

3.4.3 Multiple interrupts

Different interrupt levels for multiple interrupt requests from peripheral functions can be set in the interrupt level setting registers (ILR1, ILR2, ILR3). This enables multiple interrupt operation to be performed.

Multiple interrupts

Assume that an interrupt request for an interrupt with a higher priority interrupt level occursduring execution of an interrupt processing routine. In this case, the current interrupt processingis halted and the higher priority interrupt request is accepted. The available interrupt levels are1 to 3. However, the CPU does not accept interrupt requests set to level 3.

[Example: Multiple interrupts]

As an example of multiple interrupt processing, consider the case when an external interruptis set to a higher priority than the timer interrupt. The timer interrupt is set to level 2 andexternal interrupt set to level 1. Figure 3.4-3 "Example of multiple interrupts" shows theprocessing when the external interrupt occurs during timer interrupt processing.

Figure 3.4-3 Example of multiple interrupts

• During execution of the timer interrupt processing, the interrupt level bits of the conditioncode register (CCR:IL1, IL0) are set to the same value (in this example, 2) as the interruptlevel setting register (ILR1, ILR2, ILR3) for the timer interrupt. If an interrupt request with ahigher priority interrupt level (in this example, 1) occurs during execution of the timerinterrupt processing, the interrupt processing for the new interrupt has priority.

• Assume that you wish to temporarily disable multiple interrupts during execution of the timerinterrupt processing. Set the interrupt enable flag in the condition code register to disableinterrupts (CCR:I = 0) or set the interrupt level bits (IL1, IL0) to "00."

• Executing the interrupt return instruction (RETI) after interrupt processing ends restores thevalues of the program counter (PC) and program status (PS) saved on the stack and returnscontrol to the interrupted program.

Restoring the value of the program status (PS) also restores the condition code register (CCR)to its value prior to the interrupt.

(1)

(2)

(8)

(3)

(6)

(7)

(4)

(5)

Timer interrupt processingMain program External interrupt processing

Interrupt level 2(CCR:IL1, 0=10)

Peripheral initialization

Timer interrupt generated

Main program restart

Restart

External interrupt generated

Timer interrupt processingTimer interrupt restored

Interrupt level 1(CCR:IL1, 0=01)

External interrupt processing

External interrupt restored

Halted

43

CHAPTER 3 CPU

3.4.4 Interrupt processing time

The time from an interrupt request generation until control is passed to the interrupt processing routine is the sum of the time until execution of the current instruction is completed and the interrupt handling time (time required to prepare for interrupt processing). The maximum duration of this time is 30 instruction cycles.

Interrupt processing time

The time from generation of an interrupt request until the interrupt is accepted and the interruptprocessing routine starts includes the interrupt request sampling delay time and interrupthandling time.

Interrupt request sampling delay time

Whether an interrupt request has occurred is checked by sampling the interrupt requests duringthe last cycle of each instruction. Therefore, the CPU cannot detect interrupt requests duringexecution of an instruction. The maximum duration of this delay time takes place when aninterrupt request occurs immediately after execution of the DIVU instruction starts. Of all theinstructions, the DIVU instruction has the longest instruction cycles (21 instruction cycles).

Interrupt handling time

The CPU requires nine instruction cycles after receiving an interrupt to perform the followinginterrupt processing preparation.

• Save program counter (PC) and program status (PS).

• Set start address (interrupt vector) of interrupt processing routine in the PC.

• Update the interrupt level bits (PS:CCR:IL1, IL0) in the program status (PS).

Figure 3.4-4 "Interrupt processing time" shows the interrupt processing time.

Figure 3.4-4 Interrupt processing time

A total of 21 + 9 = 30 instruction cycles are required for the interrupt processing time if aninterrupt request occurs immediately after execution of the DIVU instruction has started. (Of allthe instructions, the DIVU instruction has the longest instruction cycles (21 instruction cycles).)However, if the program does not use the DIVU and MULU instructions, the maximum numberof instruction cycles for the interrupt processing time is 6 + 9 = 15.

The length of instruction cycles depends on the clock mode and the main clock speed setting(gear function). See Section 3.6 "Clock" for more information.

Normal instruction execution Interrupt handling

CPU operation

Interrupt request sampling delay time

Interrupt handling time(Nine instruction cycles)

Interrupt request generated

Interrupt wait time

: Last cycle of instruction. Interrupt requests are sampled at this timing.

Interrupt processing routine

44

3.4 Interrupts

3.4.5 Stack operation during interrupt processing

This section describes the saving and restoring of registers during interrupt processing.

Stack operation at start of interrupt processing

When an interrupt is accepted, the CPU automatically saves the current values of the programcounter (PC) and program status (PS) on the stack.

Figure 3.4-5 "Stack operation at start of interrupt processing" shows the stack operation at thestart of interrupt processing.

Figure 3.4-5 Stack operation at start of interrupt processing

Stack operation when interrupt returns

Executing the interrupt return instruction (RETI) at the completion of interrupt processingrestores the program status (PS) and program counter (PC) (in that order) from the stack (theopposite of the interrupt start processing). This restores the PS and PC to their values prior tothe start of the interrupt.

Caution:

The accumulator (A) and temporary accumulator (T) are not automatically saved on thestack. If required, use the PUSHW and POPW instructions to save and restore the values ofA and T.

Before interrupt

SP 0280H

Memory

xxH

xxH

xxH

xxH

027CH

027DH

027EH

027FH

xxH

xxH

0280H

0281H

Address

PC E000H

PS 0870H

After interrupt

PC E000H

Memory

0 8 H7 0 H

E 0 H

0 0 H

027CH

027DH

027EH

027FH

x xH

x xH

0280H

0281H

Address

PS 0870H

SP 027CH

PC

PS

45

CHAPTER 3 CPU

3.4.6 Stack area for interrupt processing

Execution of interrupt processing uses a stack area in RAM. The stack pointer (SP) contains the top address of the stack area.

Stack area for interrupt processing

The stack area is used to save and restore the program counter (PC) when the subroutine callinstruction (CALL) or vector call instruction (CALLV) is executed or to temporarily save andrestore registers using the PUSHW and POPW instructions.

• The stack area is located in RAM together with other data areas.

• Fujitsu recommends initializing the stack pointer (SP) with the maximum RAM address andallocating data areas from the bottom of RAM.

Figure 3.4-6 "Example of setting the stack area for interrupt processing" shows an example ofstack area setting.

Figure 3.4-6 Example of setting the stack area for interrupt processing

Note:

Interrupts, subroutine calls, PUSHW instructions, and similar save data on the stack in thelower address direction. Similarly, instructions such as return instructions (RETI, RET) andthe POPW instruction release the stack area in the lower to higher address direction. Takecare to allocate data areas for other data and general-purpose register areas such that thestack does not overlap these areas when multiple interrupts or subroutine calls result in alow address for the stack area being used.

0000 H

0080 H

0100 H

0200 H

FFFF H

I/O

RAM

General-purpose register

ROM

0280 H

Stack areaRecommended SP setting(When the maximum RAM address is 0280H)

Data area

Access prohibited

46

3.5 Reset

3.5 Reset

The following four reset causes are provided.• External reset• Software reset• Watchdog reset• Power-on reset (available as an option)Depending on the operating mode and option settings when a reset occurs, an oscillation stabilization delay time for the main clock may or may not occur.

Reset causes

External reset

Inputting an "L" level to the external reset pin (RST) generates an external reset. The externalreset is released when the reset pin returns to the "H" level.

As an option, the external reset pin can also function as a reset output pin.

Software reset

Writing "0" to the software reset bit of the standby control register (STBC:RST) generates asoftware reset of four instruction cycles.

Watchdog reset

If data is not written to the watchdog control register (WDTC) within the specified time after thewatchdog timer starts, a watchdog reset is generated for four instruction cycles.

Power-on reset

Whether the power-on reset is available can be selected as an option.

If the power-on reset is available, turning on the power supply generates a reset.

If the power-on reset is not available, an external reset circuit is required to generate a resetwhen the power is turned on.

Table 3.5-1 Reset causes

Reset cause Reset condition

External reset "L" level applied to the external reset pin

Software reset "0" written to the software reset bit of the standby control register (STBC:RST)

Watchdog reset Watchdog timer overflow

Power-on reset Power supply turned on

47

CHAPTER 3 CPU

Reset cause and oscillation stabilization delay time for the main clock

The operation of the oscillation stabilization delay time depends on the operating mode whenthe reset occurred and whether the power-on reset option is selected.

After a reset ends, normal operation restarts in main clock mode regardless of the reset causeor operating mode before the reset (clock mode and standby mode). Therefore, if a resetoccurs when the main clock oscillation is halted or during the oscillation stabilization delay timefor the main clock, the device enters the reset state during oscillation stabilization delay for themain clock. However, if the power-on reset option is not selected, no oscillation stabilizationdelay time is required for the main clock after power-on or after an external reset.

For software resets and watchdog resets, no oscillation stabilization delay time is required if themain clock is already operating. However, as the main clock oscillation is halted during sub-clock mode, an oscillation stabilization delay time is required in this case.

Table 3.5-2 "Reset cause and oscillation stabilization delay time" lists the relationship betweenthe reset cause, oscillation stabilization delay time for the main clock, and the reset operation(mode fetch).

Table 3.5-2 Reset cause and oscillation stabilization delay time

Reset cause Operation state

Reset operation and oscillation stabilization delay time for main clock

Power-on reset selected Power-on reset not selected

External reset(*1)

Power-on, during stop mode or sub-clock mode

If the external reset has been released after the oscillation stabilization delay time for the main clock has elapsed, the reset operation is performed(*2).

Remains in reset state until the external reset is released. The reset operation is performed after the external reset is released.

Software reset or watchdog reset

Main clock mode The reset operation is performed after generation of a reset for four instruction cycles (*3).

Sub-clock mode The reset operation is performed after the oscillation stabilization delay time for the main clock has elapsed (*2)

Power-on reset After power-on, the reset operation is performed after the oscillation stabilization delay time for the main clock has elapsed (*2).

An external reset circuit is required to generate a reset continually until the main clock oscillation stabilizes after the power is turned on.

*1 The device does not wait for the oscillation stabilization delay time if an external reset occurs in main clock mode. The reset operation is performed after the external reset is released.*2 If the reset output option is selected, the RST pin outputs an "L" level during the oscillation stabilization delay time for the main clock.*3 If the reset output option is selected, the RSTpin outputs an "L" level for four instruction cycles.

48

3.5 Reset

3.5.1 External reset pin

Inputting an "L" level to the external reset pin generates a reset. If the reset output option is selected, internal resets output an "L" level from the pin.

Block diagram of external reset pin

The external reset pin (RST) on models with the reset output option is a hysteresis input and anN-channel open-drain output with pull-up.

On models without the reset output option, the external reset pin becomes a dedicated resetinput pin.

Figure 3.5-1 "Block diagram of external reset pin" shows the block diagram of the external resetpin.

Figure 3.5-1 Block diagram of external reset pin

Functions of the external reset pin

Inputting an "L" level to the external reset pin RST generates the internal reset signal.

Owing to the occurrence of internal resets and oscillation stabilization delay time, the pinoutputs an "L" level. Internal resets consist of the software reset, watchdog reset, and power-onreset.

Caution:

The external reset input is accepted asynchronously, irrespective of the internal clock. Theclock is required for initialization of internal circuits. In particular, when an external clock isused, the clock must still be input while a reset input is present.

Pull-up resistorApprox. 50 k (at 5 V)

Pin

RSTInternal reset

Pch

Nch

Input buffer

Internal reset signal

Reset output

No reset output

Option

49

CHAPTER 3 CPU

3.5.2 Reset operation

When a reset is released, the CPU reads the mode data and reset vector from the internal ROM based on the mode pin settings (mode fetch). On recovering from a reset in sub-clock mode, stop mode, or after power-on in models with the power-on reset option, mode fetch is performed after the oscillation stabilization delay time has elapsed. If a reset occurs during a write to RAM, the value at the address being written to is not guaranteed.

Overview of reset operation

Figure 3.5-2 Flow of reset operation

External reset input

Fetch mode data

Fetch reset vector

Fetch instruction code from address indicated by the reset vector and execute instruction

Power-on reset option selected?

Yes

No

External reset released?

YES

Reset state

Mode fetch(Reset operation)

Normal operation(RUN state)

Power-on reset(Option)

Software resetWatchdog reset

At power-on, or during sub-clock mode or stop mode?

YES

NO

NO

NO

YES

Operation in sub-clock mode?

Reset state during oscillation

stabilization delay for the main clock





50

3.5 Reset

Mode pins

The MB89170/170A/170L series uses only single-chip mode. Always set the mode pins(MODA) to "Vss." This selects reading of the mode data and reset vector from the internalROM.

Do not change the mode pin settings after the reset operation is completed.

Mode fetch

When the reset is released, the CPU reads the mode data and reset vector from the internalROM.

Mode data (address: FFFD H)

Always set the mode data to single-chip mode (00H).

Reset vector (address: FFFE H(upper) and FFFF H (lower))

Set the address from which to start execution after the reset operation is completed. Instructionexecution starts from the address stored in the reset vector.

Reset state during oscillation stabilization delay

The reset operation for power-on resets or for external resets during sub-clock mode or stopmode (in main clock or sub-clock mode) starts after the elapse of the oscillation stabilizationdelay time for the main clock selected as an option setting. If the external reset input has notyet been released at this time, the reset operation does not start until the reset is released.

As an oscillation stabilization delay time is required even when an external clock is used, inputof an external clock is still required during a reset.

The oscillation stabilization delay time for the main clock is timed by the timebase timer.

As the "reset state during oscillation stabilization delay" does not occur when the power-on resetoption is not selected, the external reset pin (RST) must be held at the "L" level to inhibit CPUoperation until the source oscillation has stabilized.

Effect of a reset on RAM contents

The contents written in the RAM do not change before and after resets other than power-onresets. However, if an external reset is input while a write operation is in progress, the value atthe address being written to is not guaranteed. Accordingly, all RAM being used must beinitialized after a reset.

51

CHAPTER 3 CPU

3.5.3 Pin states during a reset

Pin states are initialized by a reset.

Pin states during a reset

When a reset occurs, all but a subset of I/O pins (resource pins) enter the high impedance stateand the area from which to read the mode data is set to the internal ROM. (Pins for which apull-up resistor is selected as an option setting enter the "H" level.)

Pin states after the mode data is read

All but a subset of I/O pins remain at high impedance immediately after the mode data is read.(Pins for which a pull-up resistor is selected as an option setting enter the "H" level.)

Caution:

Take care that misoperation does not occur on the devices connected to pins that enter thehigh impedance state when a reset occurs.

See Appendix E "PIN STATES FOR THE MB89170/170A/170L SERIES" for the pin statesduring a reset.

52

3.6 Clock

3.6 Clock

The clock generator contains two separate oscillation circuits. The high-speed main clock and low-speed sub-clock are generated independently by connecting resonators to external oscillators (source oscillation). Alternatively, externally generated clocks can be input.The clock controller controls the speed and supply of the two clock systems in accordance with the clock mode and standby mode.Also, an option setting is available that uses only a single-clock circuit.MB89170L series is fixed to a single-clock circuit.

Clock supply map

The clock controller controls the clock oscillation and the clock supplied to the CPU andperipheral circuits (peripheral functions). Therefore, the operating clock used for the CPU andperipheral circuits depends on the main clock and sub-clock selection (clock mode), the mainclock speed selection (gear function), and the standby mode (sleep, stop, or watch mode).

The clock for the peripheral functions is supplied from the divided output of the free-run counterwhich operates on the peripheral circuit clock.

However, some peripheral functions are supplied from the divided output of the timebase timerwhich operates using the main clock source oscillation divided by two, and the divided output ofthe watch prescaler which operates using the sub-clock. These peripherals are not affected bythe gear function.

Figure 3.6-1 "Clock supply map (MB89170/170A series" shows the clock supply map for theMB89170/170A series and Figure 3.6-2 "Clock supply map (MB89170L series" shows the clocksupply map for the MB89170L series.

53

CHAPTER 3 CPU

Figure 3.6-1 Clock supply map (MB89170/170A series)

Caution:

The MB89170L series does not contain the sub-clock oscillator circuit, watch prescaler, andDTMF generator.

Divide by 4Divide by 8


Timebase timer

Supply to CPU

Supply to

peripheral circuit

1tinst

1tinst

Free-run counter

Watch prescaler


8-bit serial I/O

Buzzer output

DTMF generator

Oscillation stabilization

delay controller

Watchdog timer

Main clock oscillator circuit

Osc

illat

ion

cont

rol

Pin

Pin

X0

X1

Sub-clock oscillator circuit

Pin

Pin

X0A

X1A

Clock modeStop mode

FCH

FCL

3

4

4

3

3

PinEC

PinSCK

Clock controller

Peripheral functions*1

*2

*2

*1

*1

*1

*2

*1, 3

*1, 3

FCH: Main clock source oscillationFCL: Sub-clock source oscillationtinst: Instruction cycle*1 Not affected by clock mode or gear function.*2 Operating speed, etc., affected by clock mode and gear function*3 Operation halts when the clock supplying the source oscillation (in main clock or sub-clock mode) halts.

Divide by 2

Divide by 2

Gear function

Clock mode

Sleep modeStop modeWatch modeOscillation stabilization delay

Stop modeWatch mode

54

3.6 Clock

Figure 3.6-2 Clock supply map (MB89170L series)



Timebase timer

Supply to CPU

Supply to

peripheral circuit

1tinst

1tinst

Free-run counter


8-bit serial I/O

Buzzer output

Oscillation stabilization

delay controller

Watchdog time

Main clockoscillator circuit

Pin

Pin

X0

X1FCH

4

4

3

3

PinEC

PinSCK

Clock controller

Peripheral functions*1

*2

*2

*1

*1

*2

*1, 3

FCH: Main clock source oscillationtinst: Instruction cycle*1 Not affected by clock mode or gear function.*2 Operating speed, etc., affected by clock mode and gear function*3 Operation halts when the clock supplying the source oscillation (in main clock mode) halts.

Divide by 2

Gear function

Sleep modeStop modeOscillation stabilization delay

Stop mode

55

CHAPTER 3 CPU

3.6.1 Clock generator

Enabling and halting the oscillation of the main clock and sub-clock is controlled based on the clock mode and stop mode.

Clock generator

When using a crystal or ceramic resonator

Connect as shown in Figure 3.6-3 "Example connection for a crystal or ceramic resonator".

Figure 3.6-3 Example connection for a crystal or ceramic resonator

Note:

A piezoelectric resonator with a built-in external capacitor (FAR series) can also be used.Refer to the data sheet for more information.

X0 X1

C1 C2

Dual-clock option



X0 X1 X0A X1A

Single-clock option

GND

C1 C2 C1 C2



X0A X1A

MB89170/170A series MB89170/170A series

R

X0 X1

C1 C2


MB8917L series

56

3.6 Clock

When using an external clock

Connect an external clock to the X0 pin and leave the X1 pin open as shown in Figure 3.6-4"Example connection for an external clock". When supplying the sub-clock externally, connectthe external clock to the X0A pin and leave the X1A pin open.

Figure 3.6-4 Example connection for an external clock

Caution:

The clock generator of the MB89170/170A series can be set as a single-clock circuit with anoption setting. If the single-clock option is not selected, the device cannot wake-up fromsub-clock mode if you switch to sub-clock mode when operating only on the main clock.Therefore, always select the single-clock option when using only one clock.

The MB89170L series clock generator is fixed to the single-clock circuit.

X0 X1 X0A X1A X0 X1 X0A X1A

GNDOpenOpenOpen

Dual-clock option



Single-clock option



MB89170/170A series MB89170/170A series

X0 X1

Open


MB89170L series

57

CHAPTER 3 CPU

3.6.2 Clock controller

The clock controller consists of the following seven blocks.• Main clock oscillator circuit• Sub-clock oscillator circuit• System clock selector• Clock control circuit• Oscillation stabilization delay time selector• System clock control register (SYCC)• Standby control register (STBC)

Block diagram of clock controller

Figure 3.6-5 "Block diagram of clock controller" shows a block diagram of the clock controller.

Figure 3.6-5 Block diagram of clock controller

- -


Standby control register (STBC)

System clock control register (SYCC)

Oscillation stabilization delay time selector


Halt clock supply to CPU

Pin state

Stop

Sleep

Watch

Watch prescaler clock

Timebase timer clock

Supply to CPU

Supply to peripheral circuits

Clock specification

Prescaler

23 /FCH

212/FCH

216/FCH

218/FCH

215/FCL



Sel

ecto

r Selector

TMD -STP SLP SPL RST

CS1 CS0WT0 SCSSCM - - WT1

System clock selectorMain clock control

Sub-clock control

2

From timebase timer

Fromwatch prescaler

FCH: Main clock source oscillationFCL: Sub-clock source oscillationtinst: Instruction cycle

Clock control circuit

Operation enable

Operation enable

1tinst

1tinst


58

3.6 Clock

Main clock oscillation circuit

The main clock oscillation circuit. Oscillation halts in main-stop mode and sub-clock mode.

Sub-clock oscillation circuit

The sub-clock oscillation circuit. Oscillates continuously except in sub-stop mode.

System clock selector

Selects the sub-clock or one of the four divided clocks derived from the source oscillation of themain clock and supplies the selected clock to the clock control circuit.

Clock control circuit

Controls supply of the operating clock to the CPU and peripheral circuits based on whether thedevice is in normal operation (RUN) mode or a standby mode (sleep, stop, or watch).

Also, halts supply of the clock to the CPU until the "halt clock supply" signal from the oscillationstabilization delay time selector is cleared.

Oscillation stabilization delay time selector

Based on the clock mode, standby mode, and reset, selects one of the four oscillationstabilization delay times for the main clock (which are generated by the timebase timer) or thesingle oscillation stabilization delay time for the sub-clock (which is generated by the watchprescaler) and outputs as the "halt clock supply to CPU" signal.

System clock control register (SYCC)

Used to select the clock mode, main clock speed, oscillation stabilization delay time for the mainclock, and to check statuses.


Used to switch from normal operation (RUN) mode to a standby mode, to set the pin statesduring stop mode or watch mode, and to perform software resets.

59

CHAPTER 3 CPU

3.6.3 System clock control register (SYCC)

The functions of the system clock control register (SYCC) include switching between the main clock and sub-clock, selecting the main clock speed, and selecting the oscillation stabilization delay time.

Structure of the system clock control register (SYCC)

Figure 3.6-6 Structure of the system clock control register (SYCC)

SCM


0 0 0 7H

Address

X--MM100B

Initial value

R R/W

SCSWT1 WT0 CS0CS1

R/W

SCM System clock monitor bit

Sub-clock (main clock halted or oscillation stabilization delay time in progress)Main clock

0

1

SCS System clock select bit

Selects sub-clock mode (32 kHz).

Selects main clock mode.

0

1

WT1

Oscillation stabilization delay time select bit

0

0

1

1

WT0

0

1

0

1

23/FCH approx. (0 ms approx.)

212/FCH approx. (1.0 ms approx.)



CS1Main clock speed select bit

Instruction cycle (at FCH = 3.58 MHz)

CS0

64/FCH (17.9 s)

16/FCH (4.47 s)

8/FCH (2.23 s)

4/FCH (1.11 s)

Fch Main clock source oscillation

R/W: Readable and writableR: Read-only-: UnusedX: UndefinedM: Depends on option setting : Initial value

R/W

0

0

1

1

0

1

0

1

R/W R/W

Oscillation stabilization delay time for the main clock from the

timebase timer output (at FCH = 3.58 MHz)

60

3.6 Clock

Instruction cycle (t inst )

The instruction cycle (minimum execution time) can be selected from the main clock divided by4, 8, 16, or 64, or the sub-clock (32.768 kHz) divided by 2. The selection is performed by thesystem clock select bit (SCS) and main clock speed select bits (CS1, CS0) in the SYCCregister.

The instruction cycle when the device operates at maximum speed in main clock mode(SYCC:SCS = 1, CS1, CS0 = 11B) with a main clock source oscillation (FCH) of 3.58 MHz is 4/FCH = 1.11 µs (approx.).

The instruction cycle in sub-clock mode (SCS = 0) with a sub-clock source oscillation (FCL) of32.768 kHz is 2/FCL = 61.0 µs (approx.).

Table 3.6-1 Function of each system clock control register (SYCC) bit

Bit name Function

bit7 SCM: System clock monitor bit

• Used to check the current clock mode (operating mode).• If the bit is "0", the device is operating in sub-clock mode (the main clock

is halted or the oscillation stabilization delay time is in progress prior to switching to main clock mode).

• If the bit is "1", the device is operating in main clock mode.Note:The bit is read-only. Writing has no meaning and does not affect operation.

bit6bit5

Unused bits • The read values are undefined.• Writing has no effect on operation.

bit4bit3

WT1, WT0: Oscillation stabilization delay time select bits

• These bits select the oscillation stabilization delay time for the main clock.• The device waits for elapse of the oscillation stabilization delay time

specified by these bits when switching from sub-clock mode to main clock mode or when an external interrupt restores normal operation from main-stop mode.

• The initial value of these bits are specified as an option setting. Consequently, if the device waits for the oscillation to stabilize after a reset, the duration of the delay is the time selected by the option.

Caution:Do not change the values of these bits at the same time that you switch from sub-clock to main clock mode (SCS = 1 --> 0). Also, before changing the values of the bits, use the SCM bit to verify that an oscillation stabilization delay time for the main clock is not currently in progress.

bit2 SCS:System clock select bit

• This bit specifies the clock mode.• Writing "0" to this bit switches from main clock mode to sub-clock mode.• Writing "1" to this bit switches from sub-clock mode to main clock mode

after the device waits for the oscillation stabilization delay time set by the WT1 and WT0 bits to elapse.

Caution:This bit has no meaning when the single-clock option is selected. It also has no meaning for MB89170L series. Always set to "1."

bit1bit0

CS1, CS0:Main clock speed select bits

• These bits select the clock speed in main clock mode.• Four different speeds are available for the operating clock for the CPU

and peripheral functions (gear function). However, the operating clock for the timebase timer and watch prescaler is not affected by these bits.

61

CHAPTER 3 CPU

3.6.4 Clock modes

The clock modes consist of main clock mode and sub-clock mode.In main clock mode, the main clock is the principle operating clock. The speed of the main clock can be selected from four speeds obtained by dividing the main clock source oscillation (gear function).In sub-clock mode, the main clock source oscillation halts and the sub-clock becomes the only operating clock.

Clock mode operation states

The device can switch from either clock mode to their respective standby modes. See Section3.7 "Standby Modes (Low Power Consumption)" for more information on standby mode.

Table 3.6-2 Clock mode operation states

Clock mode

Main clock speed SYCC

register (CS1,CS0)

Standby mode

Clock generation Operating clocks Standby mode wake-up

triggers (other than a reset)

Main clock

Sub-clock CPUTimebase

timerPeripherals

Watch prescaler

Main clock mode

(1.1)

Fast RUNOscillation Oscillation

FCH/4FCH/2 FCH/4

FCL

Any interrupt request

SleepHalted

Stop HaltedOscillation

Halted Halted External

(1.0)

RUNOscillation

FCH/8FCH/2 FCH/8

FCL


SleepOscillation Halted

Stop Halted Halted Halted External

(0.1)

RUNHalted Oscillation

FCH/16FCH/2 FCH/16

FCL


SleepHalted

Stop OscillationOscillation

Halted Halted External

(0.0)

RUNHalted

FCH/64FCH/2 FCH/64

FCL


SleepOscillation Halted


Sub-clock mode

-

RUN

HaltedOscillation

FCL

Halted (*1)FCL FCL


SleepHalted


Watch mode Halted Oscillation Halted Halted (*1) Halted FCL

External or watch interrupt

FCH: Main clock source oscillationFCL: Sub-clock source oscillation*1 As the timebase timer operates using the main clock, operation halts in sub-clock mode.

62

3.6 Clock

Gear function (main clock speed select function)

The four main clock speeds can be selected by writing a value between "00B" and "11B" to themain clock speed select bits in the system clock control register (SYCC:CS1, CS0).

The CPU and peripheral circuits operate using the specified main clock. However, the timebasetimer and watch prescaler are not affected by the gear function.

Setting the main clock to a slower speed reduces the power consumption.

Main clock mode operation

In normal main clock mode operation (main-RUN mode), both the main clock and sub-clock areoscillating. The watch prescaler operates using the sub-clock. The CPU, timebase timer, andother peripheral circuits use the main clock.

While the device operates in main clock mode, the speed of the main clock used by blocks otherthan the timebase timer can be switched (gear function). Also, the device can switch to main-sleep or main-stop mode by setting a standby mode.

Operation always restarts in main-RUN mode after any sort of reset (after release of a reset inany operating mode).

Switching from main clock mode to sub-clock mode

Writing "0" to the system clock selection bit in the system clock control register (SYCC:SCS)switches from main clock mode to sub-clock mode.

The current operating clock can be checked by reading the system clock monitor bit in thesystem clock control register (SYCC:SCM).

Caution:

If switching to sub-clock mode immediately after turning on the power supply or the like, usesoftware to have the system wait for a period of time exceeding the oscillation stabilizationdelay time for the sub-clock. The sub-clock oscillation stabilization delay time is generatedby the watch prescaler.

Operation in sub-clock mode

In normal sub-clock mode operation (sub-RUN mode), the main clock oscillation halts and thedevice operates using only the sub-clock. Operating on the low speed clock reduces the powerconsumption.

All functions other than the timebase timer operate in the same manner as in main clock mode.Specifying a standby mode when the device operates in sub-clock mode sets the device to sub-sleep, sub-stop, or watch mode.

Returning main clock mode from sub-clock mode

Writing "1" to the system clock selection bit in the system clock control register (SYCC:SCS)returns main clock mode from sub-clock mode.

However, operation in main clock mode does not start until the oscillation stabilization delaytime for the main clock has elapsed. The oscillation stabilization delay time can be selectedfrom four different times with the oscillation stabilization delay time select bits in the systemclock control register (SYCC:WT1, WT0).

Caution:

Do not change the oscillation stabilization delay time select bits (SYCC:WT1, WT0) at thesame time that switching from the sub-clock to the main clock (SYCC:SCS = 1) takes place.Similarly, do not change the bits while an oscillation stabilization delay for the main clock isin progress. In this case, use the system clock monitor bit to verify that the operating clockhas switched to the main clock (SYCC:SCM = 1) before writing to the bits.

63

CHAPTER 3 CPU

When the main clock mode is restored from sub-clock mode by a reset, models with the power-on reset option wait for the oscillation stabilization delay time for the main clock to elapse. Formodels without the power-on reset option, no oscillation stabilization delay occurs for resetsother than software resets and watchdog resets.

64

3.6 Clock

3.6.5 Oscillation stabilization delay time

When the device is set to main-RUN mode from a state when the main clock is halted such as at power-on or in main-stop mode or sub-clock mode, a delay is required for the main clock oscillation to stabilize. Similarly, the sub-clock oscillation halts in sub-stop mode and therefore an oscillation stabilization delay time is also required for the sub-clock.

Oscillation stabilization delay time

Resonators such as ceramic and crystal resonators require a time of several milliseconds toseveral tens of milliseconds after oscillation starts for oscillation to stabilize at the characteristicfrequency (oscillation frequency).

Therefore, CPU operation is disabled immediately after the oscillation starts and the clock is notsupplied to the CPU until the oscillation stabilization delay time has elapsed and the oscillationhas sufficiently stabilized.

The time required for oscillation to stabilize depends on the type (crystal, ceramic, etc.) ofresonator connected to the clock oscillator (clock generator). Therefore, select an appropriateoscillation stabilization delay time for the resonator to be used.

Figure 3.6-7 "Clock oscillator operation immediately after oscillation starts" shows the operationof the clock oscillator immediately after oscillation starts.

Figure 3.6-7 Clock oscillator operation immediately after oscillation starts


Normal operation(Recovery from stop mode or reset operation)

Oscillation starts

X1

Oscillation stabilized

Resonator oscillation time

65

CHAPTER 3 CPU

Oscillation stabilization delay time for the main clock

When operation starts in main clock mode from a state in which the main clock oscillation ishalted, a delay is required for the main clock oscillation to stabilize.

The oscillation stabilization delay time for the main clock is obtained by counting up on thecounter of the timebase timer until an overflow occurs on the specified bit. The counter iscleared before starting the count.

Oscillation stabilization delay time during operation

The oscillation stabilization delay time used when an external interrupt causes the device torecover from main-stop mode to main-RUN mode or when sub-clock mode switches to mainclock mode can be selected from four available times using the oscillation stabilization delaytime select bits in the system clock control register (SYCC:WT1, WT0).

Oscillation stabilization delay time during a reset

The oscillation stabilization delay time used during a reset (the initial value of WT1, WT0) canbe selected as an option setting.

On models with the power-on reset option, an oscillation stabilization delay occurs at any ofresets during sub-clock mode, at a power-on reset, or on waking up from stop mode by anexternal reset.

Table 3.6-3 "Oscillation stabilization delay time and main clock mode operation start conditions"lists the relationship between the oscillation stabilization delay time and the conditions forstarting main clock mode.

Oscillation stabilization delay time for the sub-clock

The device waits for the elapse of a fixed oscillation stabilization delay time (215/FCL, FCL:sub-clock source oscillation) for the sub-clock with the period when an external interrupt wakesup the device from sub-stop mode (in which the sub-clock oscillation is halted) to sub-RUNmode (when the sub-clock starts oscillation).

The oscillation stabilization delay time for the sub-clock is the time period that begins when thewatch prescaler is cleared and ends when an overflow occurs.

An oscillation stabilization delay time for the sub-clock is also required at power-on.

Therefore, if switching to sub-clock mode after power-on, use software to have the system wait

Table 3.6-3 Oscillation stabilization delay time and main clock mode operation start conditions

Main clock mode operation start

conditionsPower-on

During sub-clock modeWake-up from main-

stop mode Switch from sub-clock

mode to main clock mode

External reset

Software or watchdog

reset

External reset

External interrupt

Oscillation stabilization delay time selection

Option setting SYCC:WT1, WT0 *2

Power-on reset option O O O O O O

No power-on reset option

X X O X O O

O: Oscillation stabilization delay time occurs.X: Oscillation stabilization delay time does not occur.*1 System clock select bit of the system clock control register*2 Oscillation stabilization delay time select bits of the system clock control register

66

3.6 Clock

for a period of time exceeding the oscillation stabilization delay time for the sub-clock.

67

CHAPTER 3 CPU

3.7 Standby Modes (Low Power Consumption)

The standby modes consist of sleep mode, stop mode, and watch mode. The device can switch to standby mode from either main clock or sub-clock mode by writing to the standby control register (STBC).In main clock mode, the device can switch to either sleep or stop mode (two modes). In sub-clock mode, the device can switch to sleep, stop, or watch mode (three modes). The standby modes reduce the power consumption by halting operation of the CPU and peripheral functions. This section describes the relationship between the standby modes and clock modes, and the operation of each part of the device in each standby mode.

Standby modes

The clock modes reduce power consumption by reducing the speed of the operating clocksupplied to the CPU and peripheral circuits, for example by switching between the main clockand sub-clock or by changing the speed of the main clock (gear function). In contrast, thestandby modes reduce power consumption by using the clock controller to halt the clock supplyto the CPU (sleep mode), halt the clock supply to the CPU and peripheral circuits (watch mode),or halt the source oscillation itself (stop mode).

Main-sleep mode

Main-sleep mode halts the operation of the CPU and watchdog timer. Peripheral functionsother than the watch prescaler continue to operate using the main clock (some functions canoperate using the sub-clock).

Sub-sleep mode

Sub-sleep mode halts the main clock oscillation and the operation of the CPU, watchdog timer,and timebase timer. Peripheral functions continue to operate using the sub-clock.

Main-stop mode

Main stop mode halts the operation of the CPU and peripherals. The main clock oscillationhalts but the sub-clock oscillation continues. This mode halts all functions other than theexternal interrupts, watch prescaler count, and those functions that operate on the sub-clock.

Sub-stop mode

Sub-stop mode halts all functions other than the external interrupts. Oscillation halts for boththe main clock and sub-clock.

Watch mode

The device can switch to watch mode only when in sub-clock mode. In watch mode, allfunctions halt other than the watch prescaler (watch interrupt), external interrupts, and thosefunctions that operate on the sub-clock.

Note:

In modes in which the main clock is halted (such as main-stop mode and watch mode), theLCD controller driver can continue to operate using the sub-clock if the sub-clock is still

68


oscillating. See Chapter 9, "Buzzer Output" and Figure 3.6-1 "Clock supply map (MB89170/170A series", "Clock supply map (MB89170/170A series)" and Figure 3.6-2 "Clock supplymap (MB89170L series)", "Clock supply map (MB89170L series)" in Section 3.6, "Clock."

69

CHAPTER 3 CPU

3.7.1 Operating states in standby modes

This section describes the operating states of the CPU and peripheral functions in standby modes.

Operating states in standby modes

Table 3.7-1 CPU and peripheral function operating states in standby modes

Operating mode

Function

Main clock mode Sub-clock mode

RUN SleepStop

(SPL=0)Stop

(SPL=1)RUN Sleep

Stop(SPL=0)

Stop(SPL=1)

Watch

Main clock

Opertes

OperatesStopped Stopped Stopped Stopped

Stopped Stopped

Stopped

Sub-clock Operates Operates Operates Operates Operates

CPU

Instruc-tions Stopped Stopped Stopped Operates Stopped Stopped

ROM

Held Held Held Held Held Held Held HeldROM

Per

iphe

ral f

unct

ions

I/O port

Timebase timer

Operates

Stopped Stopped

Stopped

Stopped

Stopped Stopped

StoppedWatchdog timer

StoppedOperates

(*2)

8-bit/16-bit timer/counter

Operates

Operates Operates8-bit serial I/O Operates

(*2)

Buzzer output Operates (*2)

Operates (*2)

Operates (*2)

Operates (*2)

Operates (*2)

External interrupts 1, 2

Operates Operates

Operates Operates

Operates Operates

OperatesWatch prescaler

Operates (*1)

Operates (*1)

Stopped StoppedDTMF generator

Stopped StoppedProhibited

(*3)Prohibited

(*3)Stopped

Pins Held Held Hi-z Operates Held Held Hi-z Held

Wakeup method Reset or any interrupt

*1 The watch prescaler continues counting but the watch interrupt is not generated.*2 Can operate if the output of the watch prescaler is selected as the operating clock.*3 Use prohibited. Disable operation by using the program before switching to sub-clock mode.Note:The following should be noted for the MB89170L series:• No sub-clock mode is supported as the operating mode.• The peripheral functions do not include the watch prescaler and DTMF generator.

70


Pin states in standby mode

Depending on the pin state setting bit in the standby control register (STBC:SPL), most I/O pinseither maintain their states prior to entering stop or watch mode or enter the high impedancestate, regardless of the clock mode.

See Appendix E, "Pin States for the MB89170/170A/170L Series" for more information on pinstates in standby mode.

71

CHAPTER 3 CPU

3.7.2 Sleep mode

This section describes the operation of the sleep mode.

Sleep mode operation

Switching to sleep mode

Sleep mode halts the CPU operating clock. The CPU halts, and registers and RAM maintaintheir values prior to entering sleep mode, and peripheral functions other than the watchdogtimer continue to operate.

However, as the main clock oscillation halts in sub-clock mode, the timebase timer does notoperate in this case as the timebase timer uses the main clock source oscillation divided by twoas its count clock.

Writing "1" to the sleep bit in the standby control register (STBC:SLP) switches the device tosleep mode. If an interrupt request is present when "1" is written to the SLP bit, the write isignored and instruction execution continues without switching to sleep mode (the device doesnot switch to sleep mode when the interrupt processing is completed).

Waking up from sleep mode

The device can wake up from sleep mode either by a reset or an interrupt from a peripheralfunction.

If a reset occurs in sub-sleep mode, the reset operation starts after the oscillation stabilizationdelay time for the main clock has elapsed.

The pin states are initialized with the reset operation.

The device wakes up from sleep mode if a peripheral function or external interrupt circuitgenerates an interrupt request with a priority level that is higher than interrupt level "11" duringsleep mode. This occurs regardless of the state of the CPU interrupt enable flag (CCR:I) andinterrupt level bits (CCR:IL1, IL0).

After waking up, the device handles the interrupt in the same manner as other interrupts.Interrupt processing is executed if the interrupt can be accepted. If the interrupt is not accepted,execution continues from the instruction following the one executed immediately before enteringsleep mode.

72


3.7.3 Stop mode

This section describes the operation of stop mode.

Stop mode operation

Switching to stop mode

Stop mode halts the source oscillation. Almost all functions halt, and registers and RAMmaintain their values prior to entering stop mode.

In main clock mode, the main clock oscillation halts but the sub-clock oscillation continues.Therefore, the watch prescaler count and those functions that use the sub-clock continue tooperate but the CPU and other peripheral functions, except for the external interrupt circuit, halt.

In sub-clock mode, both the main clock and sub-clock oscillations halt. All peripheral functionshalt except for the external interrupt circuit. Accordingly, this mode maintains data withminimum power consumption.

Writing "1" to the stop bit in the standby control register (STBC:STP) switches the device to stopmode. If the value of the pin state setting bit (STBC:SPL) at this time is "0", external pinsmaintain their existing states. If SPL is "1", the external pins enter the high impedance state (orto the "H" level for pins with a pull-up resistor selected as an option setting).

If an interrupt request is present when "1" is written to the STP bit, the write is ignored andinstruction execution continues without switching to stop mode (the device does not switch tostop mode even when the interrupt processing is completed).

When switching to stop mode in main clock mode, disable the output of the timebase timerinterrupt request (TBTC:TBIE = 0) if required. Similarly, when switching to stop mode in sub-clock mode, disable the output of the watch prescaler interrupt request (WPCR:WIE = 0).

Waking up from stop mode

The device can wake up from stop mode either by a reset or an external interrupt.

On models with the power-on reset option, if a reset occurs in stop mode, the reset operationstarts after the oscillation stabilization delay time for the main clock has elapsed.

No oscillation stabilization delay time occurs when a reset occurs in stop mode on modelswithout the power-on reset option. The pin states are initialized with the reset operation.

The device wakes up from stop mode if an external interrupt circuit generates an interruptrequest with a priority level that is higher than interrupt level "11" during stop mode. This occursregardless of the state of the CPU interrupt enable flag (CCR:I) and interrupt level bits(CCR:IL1, IL0). As the peripheral functions are halted during stop mode, only external interruptrequests can occur. Also, in main-stop mode, the watch prescaler continues to operate but thewatch interrupt is not generated.

After waking up, the device handles the interrupt in the same manner as other interrupts afterthe oscillation stabilization delay time has elapsed. Interrupt processing is executed if theinterrupt can be accepted. If the interrupt is not accepted, execution continues from the nextinstruction after the instruction that was executed prior to entering stop mode.

If the device wakes up from stop mode with an external interrupt, some peripheral functionsrestart midway through their operation. For example, the length of the first interval of theinterval timer is undefined. Therefore, always initialize peripheral functions after waking up from

73

CHAPTER 3 CPU

stop mode.

Caution:

Using an interrupt to wake up from stop mode can be done only when using an interruptrequest from an external interrupt circuit.

74


3.7.4 Watch mode

This section describes the operation of watch mode.

Watch mode operation

Switching to watch mode

Watch mode halts the operating clock to the CPU and main peripheral circuits. The device canswitch to watch mode only when in sub-clock mode (when the main clock oscillation is halted).

Registers and RAM maintain their values prior to entering watch mode. This mode halts allfunctions other than the watch prescaler (watch interrupt), external interrupt circuit, and thosefunctions that use the sub-clock. This enables data to be maintained with very low powerconsumption.

Writing "1" to the watch bit in the standby control register (STBC:TMD) when sub-clock mode isset in the system clock select bit of the system clock control register (SYCC:SCS = 0) switchesto watch mode.

If the pin state set bit in the standby control register (STBC:SPL) is "0" when watch mode is set,external pins maintain their existing states. If SPL is "1", the external pins enter the highimpedance state (or to the "H" level for pins with a pull-up resistor selected as an option setting).

If an interrupt request is present when "1" is written to the TMD bit, the write is ignored andinstruction execution continues without switching to watch mode (the device does not switch towatch mode after the interrupt processing is completed).

Waking up from watch mode

The device can wake-up from watch mode with a reset, watch interrupt, or external interrupt.

On models with the power-on reset option, if a reset occurs in watch mode, the reset operationstarts after the oscillation stabilization delay time for the main clock has elapsed.

No oscillation stabilization delay time occurs when a reset occurs in watch mode on modelswithout the power-on reset option. The pin states are initialized with the reset operation.

The device wakes up from watch mode if the watch prescaler or external interrupt circuitgenerates an interrupt request with a priority level that is higher than interrupt level "11" duringwatch mode. This occurs regardless of the state of the CPU interrupt enable flag (CCR:I) andinterrupt level bits (CCR:IL1, IL0). As most peripheral functions other than the watch prescalerhalt during watch mode, interrupt requests other than the watch interrupt and external interruptsare not generated.

After wake-up, the device handles the interrupt in the same manner as other interrupts.

Interrupt processing is executed if the interrupt can be accepted. If the interrupt is not accepted,execution continues from the instruction following the one executed immediately before enteringwatch mode.

When the device wakes up from watch mode, some peripheral functions restart midway throughtheir operation. For example, the length of the first interval of the interval timer is undefined.Therefore, always initialize peripheral functions after wake-up from watch mode.

75

CHAPTER 3 CPU

3.7.5 Standby control register (STBC)

The standby control register (STBC) is used to set the device to sleep, stop, or watch mode, to set the pin states during stop and watch mode, and to perform software resets.


Figure 3.7-1 Standby control register (STBC)

STP


0 0 0 8H

Address

00010XXXB

Initial value

SPL

W R/W

SLP RST

STPStop bit

Always read as "0". No effect on operation

Switches to stop mode.

0

1

Read Write

TMD

W W

SLPSleep bit


Switches to sleep mode.

0

1

0

1

Read Write

SPL Pin state setting bitExternal pins maintain their previous states during stop mode.

0

RSTSoftware reset bit

Always read as "1".

Generates a reset signal for four instruction cycles.

1

Read Write

0

TMD

Watch bit


Switches to watch mode.

Read Write

Only meaningful in sub-clock mode (SYCC:SCS = 0)

R/W: Readable and writableW: Write-only-: UnusedX: Undefined

: Initial value

W

No effect on operation

External pins enter the high impedance state during stop mode.

1

76


Table 3.7-2 Functions of the standby control register (STBC) bits

Bit name Function

bit7 STP:Stop bit

• This bit switches the device to stop mode.• Writing "1" to the bit switches the device to stop mode.• Writing "0" has no effect on operation.• Reading the bit always returns "0".

bit6 SLP:Sleep bit

• This bit switches the device to sleep mode.• Writing "1" to the bit switches the device to sleep mode.• Writing "0" has no effect on operation.• Reading the bit always returns "0".

bit5 SPL:Pin state set bit

• This bit specifies the state of external pins when the device is in stop or watch mode.

• Writing "0" to the bit causes external pins to hold their existing states (levels) when the device enters stop or watch mode.

• Writing "1" to the bit causes external pins to enter the high impedance state when the device enters stop or watch mode. (Pins with a pull-up resistor selected as an option setting to the "H" level.)

• A reset initializes the bit to "0".

bit4 RST:Software reset bit

• This bit triggers a software reset.• Writing "0" to the bit generates an internal reset for four instruction cycles.• Writing "1" has no effect on operation.• Reading the bit always returns "1".Note:

Initializing a software reset in sub-clock mode causes operation to start in main clock mode after waiting for the oscillation stabilization delay time to elapse.Therefore, the reset signal is output during the oscillation stabilization delay time.

bit3 TMD:Watch bit

• This bit switches the device to watch mode.• Writing to the bit is meaningful only when in sub-clock mode (SYCC:SCS

= 0).• Writing "1" to the bit switches the device to watch mode.• Writing "0" has no effect on operation.• Reading the bit always returns "0".Caution:

Always write "1" to this bit for the MB89170L series.

bit2bit1bit0


77

CHAPTER 3 CPU

3.7.6 State transition diagram 1 (power-on reset, dual-clock)

This section shows the state transition for models with the power-on reset option and which use two clocks.

State transition diagram 1 (power-on reset, dual-clock)

Figure 3.7-2 State transition diagram 1 (power-on reset, dual-clock)

[1]

(7) [3] (3)[2]

(1)

(2)

(6)

[4]

(4)

(5)

(8)

[6]

[7]

[5]

<8>

<7>

<6><5>

<1>

<2>

<10><9>

<11>

<4>

<3>

[8]

Main clock mode

Sub-clock mode

Main-sleep stateMain-RUN

stateMain-stop state

Main clock oscillation stabilization delay

Sub-clock oscillation stabilization delay

Sub-RUN, main clock oscillation

stabilization delay

Sub-sleep stateSub-stop state

Watch state

Reset state

Sub-RUN state

Reset state during oscillation stabilization

delay

Power turned on

Power-on reset

78


Transitions to and from clock modes (non-standby modes)

Transitions to and from standby modes

Caution:

As the CPU and watchdog timer halt during standby modes, watchdog and software resetsdo not occur.

Table 3.7-3 Transitions to and from clock modes (power-on reset, dual-clock)

State transition Transition conditions

Switch to normal main clock mode (main-RUN) state after power-on reset

[1] Oscillation stabilization delay time for main clock (Timebase timer output)[2] Reset input released

Reset in main-RUN state [3] External reset, software reset, watchdog reset

Switch from main-RUN state to sub-RUN state

[4] SYCC:SCS = 0(*1)

Return from main-RUN state to sub-RUN state

[5] SYCC:SCS = 1[6] Oscillation stabilization delay time completed for main clock(Check using SYCC:SCM)[7] External reset, software reset, watchdog reset

Reset in sub-RUN state [8] External reset, software reset, watchdog reset

SYCC: System clock control register*1 After turning on the power, do not switch the device to sub-RUN mode until after the oscillation stabilization delay time for the sub-clock has elapsed.

Table 3.7-4 Transitions to and from standby modes (power-on reset, dual-clock)



Switch to sleep mode

[1] STBC:SLP=1 <1> STBC:SLP=1

Wake-up from sleep mode

[2] Interrupt (any type)[3] External interrupt

<2> Interrupt (any type)<3> External reset

Switch to stop mode

[4] STBC:STP=1 <4> STBC:STP=1

Wake-up from stop mode

[5] External interrupt[6] Oscillation stabilization delay time completed for the main clock(Output from timebase timer)[7] External reset[8] External reset(During oscillation stabilization delay)

<5> External interrupt<6> Oscillation stabilization delay time completed for sub-clock(Output from watch prescaler)<7> External reset<8> External reset (During oscillation stabilization delay)

Switch to watch mode

-<9> STBC:TMD=1 (*1)


-<10> External interrupt or watch interrupt<11> External reset

STBC: Standby control register*1 The device can switch to watch mode only from the sub-RUN state (SYCC:SCS = 0).

79

CHAPTER 3 CPU

3.7.7 State transition diagram 2 (no power-on, dual-clock)

This section shows the state transition diagram for models without the power-on reset option and which use two clocks.

State transition diagram 2 (no power-on reset, dual-clock)

Figure 3.7-3 State transition diagram 2 (no power-on reset, dual-clock)

(3)[3][2]

(1)

(2)

(6)

(4)

(7)

(5)

(8)

[6]

[7]

[9]

[4]

<8>

<7>

<5> <6> [5]

<1>

<2>

<10><9>

<11>

<4>

Main clock mode

Sub-clock mode

Main-sleep stateMain-RUN

stateMain-stop state

Main clock oscillation

stabilization delay

Sub-clock oscillation stabilization delay

Sub-RUN, main clock oscillation

stabilization delay

Sub-sleep stateSub-stop state

Watch state

Reset state

Power turned on

Sub-RUN state


[1] External reset

[8]

[10]

<3>

80


Transitions to and from clock modes (non-standby modes)

Table 3.7-5 Transitions to and from clock modes (no power-on reset, dual-clock)


Switch to normal main clock mode (main-RUN) state after external reset

[1] The external reset input must be maintained until the main clock oscillation stabilizes.[2] Reset input released

Reset in main-RUN state [3] External reset, software reset, watchdog reset

Switch from main-RUN state to sub-RUN state

[4] SYCC:SCS = 0(*1)

Return from sub-RUN state to main-RUN state

[5] SYCC:SCS = 1[6] Oscillation stabilization delay time completed for main clock (Check using SYCC:SCM)[7] Software reset, watchdog reset[8] The external reset input must be maintained until the main clock oscillation stabilizes.

Reset in sub-RUN state [9] Software reset, watchdog reset[10] The external reset input must be maintained until the main clock oscillation stabilizes.

SYCC: System clock control register*1 After turning on the power, do not switch the device to sub-RUN mode until the oscillation stabilization delay time for the sub-clock has elapsed.

81

CHAPTER 3 CPU

Transitions to and from standby modes

Caution:

For external resets which occur other than in the normal operating state (RUN) in main clockmode or in sleep mode, the external reset input must be maintained until the main clockoscillation stabilizes.

Table 3.7-6 Transitions to and from standby modes (power-on reset, dual-clock)



Switch to sleep mode

[1] STBC:SLP=1 <1> STBC:SLP=1

Wake-up from sleep mode

[2] Interrupt (any type)[3] External interrupt

<2> Interrupt (any type)<3> External reset

Switch to stop mode

[4] STBC:STP=1 <4> STBC:STP=1

Wake-up from stop mode

[5] External interrupt[6] Oscillation stabilization delay time completed for the main clock(Output from timebase timer)[7] External reset[8] External reset(During oscillation stabilization delay)

<5> External interrupt<6> Oscillation stabilization delay time completed for sub-clock(Output from watch prescaler)<7> External reset<8> External reset (During oscillation stabilization delay)

Switch to watch mode

-<9> STBC:TMD=1 (*1)


-<10> External interrupt or watch interrupt<11> External reset

STBC: Standby control register*1 The device can switch to watch mode only from the sub-RUN state (SYCC:SCS = 0).

82


3.7.8 State transition diagram 3 (single-clock)

This section shows the state transition diagrams when a single-clock is used. Transition diagrams are shown for models with the power-on reset portion and for models without the power-on reset option. When a single-clock is used, the sub-clock mode and watch mode states do not exist.The MB89170L series is fixed to a single-clock and does not support both the sub-clock mode and watch mode states.

State transition diagram 3 (single-clock)

Figure 3.7-4 State transition diagram 3 (with power-on reset)

[1]

(7) [3][2]

(1)

(2)

(6)

(4)

(5)

(8)

Main clock mode

Main-sleep stateMain-RUN stateMain-stop state



Power turned on

Reset state

(3)

Power-on reset

83

CHAPTER 3 CPU

Figure 3.7-5 State transition diagram 3 (without power-on reset)

(3)

(1)

(2)

(6)

(4)

(7)

(8)

Main clock mode

Main-sleep stateMain-RUN stateMain-stop state


Reset state

Power turned on

[2] [3]

(5)

[1] External reset

84


3.7.9 Pin states in standby mode

Table 3.7-7 "Pin states in standby modes (MB89170/170A series)" lists the MB89170/170A series pin states during standby modes. Table 3.7-8 "Pin states in standby modes (MB89170L series)" lists the MB89170L series pin states during standby modes.

Pin states in standby modes

See Appendix E, "Pin States for the MB89170/170A/170L Series" for more information on pinstates in modes other than standby modes.

Table 3.7-7 Pin states in standby modes (MB89170/170A series)

Pin nameSleep mode Stop mode(SPL=0) Stop mode(SPL=0) Watch

mode (SPL=0)

Watch mode

(SPL=1)Main-sleep

Sub-sleep

Main-stop

Sub-stop Main-stop

Sub-stop

X0 Oscillation input

Hi-z Hi-z Hi-z Hi-z Hi-z

X1 Oscillation output

"H" output "H" output "H" output "H" output "H" output

X0A *2 Oscillation input Oscillation input

Hi-z Oscillation input

Hi-z Oscillation input

Oscillation input

X1A *2 Oscillation output Oscillation output

"H" output Oscillation output

"H" output Oscillation output

Oscillation output

M0D0M0D1

Mode input Mode input Mode input Mode input

Mode input

RST Reset input Reset input Reset input Reset input

Reset input

P00/INT20 to P07/INT27

Port I/OResource I/O


Hi-z Port I/OResource I/O

Hi-z

P10 tp P17

P20 to P27 Port output Port output Hi-z Port output

Hi-z

P30/SCK to P37/BZ



Hi-z (*1) Port I/OResource I/O

Hi-z (*1)

P40 to P44 Port output Port output Hi-z Port output

Hi-z

*1 The input level is fixed so as to prevent linkage due to open inputs.*2 Connect pins to ground when the single-clock option is selected.Hi-z: High impedanceSPL: Pin state set bit in the standby control register (STBC)Note:

- The input level of the external interrupt enable pin is not fixed so that interrupt input is possible.- When "Hi-z" is indicated for a pin for which the pull-up resistor mask option was selected, the pin enters the pull-up state.

85

CHAPTER 3 CPU

See Appendix E, "Pin States for the MB89170/170A/170L Series" for more information on pinstates in mode other than standby modes.

Table 3.7-8 Pin states in standby modes (MB89170L series)

Pin nameSleep mode Stop mode (SPL=0) Stop mode (SPL=0)

Main-sleep Main-stop Main-stop

X0 Oscillation input Hi-z Hi-z

X1 Oscillation output "H" output "H" output

M0D0M0D1

Mode input Mode input Mode input

RST Reset input Reset input Reset input

P00/INT20 to P07/INT27 Port I/O

Resource I/OPort I/OResource I/O


P10 tp P17

P20 to P27 Port output Port output Hi-z

P30/SCK to P37/BZ Port I/OResource I/O


Hi-z (*1)

P40 to P44 Port output Port output Hi-z

*1 The input level is fixed so as to prevent linkage due to open inputs.*2 Connect pins to ground when the single-clock option is selected.Hi-z: High impedanceSPL: Pin state set bit in the standby control register (STBC)Note:

- The input level of the external interrupt enable pin is not fixed so that interrupt input is possible.- When "Hi-z" is indicated for a pin for which the pull-up resistor mask option was selected, the pin enters the pull-up state.

86


3.7.10 Notes on using standby modes

If an interrupt request from a peripheral function is present when a standby mode is set in the standby control register (STBC), the device does not switch to standby mode. When an interrupt is used to wake-up the device from a standby mode to the normal operating state, the operation after wake-up depends on whether the interrupt request is accepted.

Interrupts and switching to standby mode

Writing "1" to the stop bit (STBC:STP), sleep bit (SLP), or watch bit (TMD) of the standby controlregister (STBC) is ignored if an interrupt request to the CPU with an interrupt priority level higherthan "11" has been generated from a peripheral function. Consequently, the device does notswitch to standby mode. (The device does not switch to standby mode even after the interruptprocessing is completed.)

This occurs regardless of whether the CPU accepts the interrupt.

Even if the CPU is performing interrupt processing, the device can switch to standby modeprovided that the interrupt request flag bit has been cleared and no other interrupt request ispresent.

Using an interrupt to wake up from a standby mode

If an interrupt request with an interrupt priority level higher than "11" is generated by aperipheral function or other source during sleep or stop mode, the device wakes up from thestandby mode. This occurs regardless of whether the CPU accepts the interrupt.

After waking up, the device performs normal interrupt processing. If the priority set in theinterrupt level setting register (ILR1 to ILR3) for the interrupt request has a higher priority levelthan the level set in the interrupt level bits of the condition code register (CCR:IL1, IL0) and ifthe interrupt enable flag is enabled (CCR:I = 1), execution branches to the interrupt processingroutine. If the interrupt is not accepted, operation restarts from the next instruction after theinstruction that activated standby mode.

To stop execution from branching to an interrupt immediately after waking up, disable interruptsor perform a similar measure before setting standby mode.

Notes on setting standby mode

To set a standby mode using the standby control register (STBC), set the values listed in Table3.7-9. The priority, if bits are simultaneously set to "1", is: stop mode, watch mode, sleepmode. However, always set one bit to "1" only.

Also, do not switch the device to stop mode, sleep mode, or watch mode immediately afterswitching from sub-clock mode to main clock mode (SYCC:SCS = 0 -> 1). Wait until the clockmonitor bit in the system clock control register (SYCC:SCM) goes to "1" before switching to anyof these modes.

Note that writing to watch bit (TMD) during main clock mode is ignored.

87

CHAPTER 3 CPU


As the oscillators that produce the source oscillations are halted during stop mode (whether inmain clock mode or sub-clock mode), an oscillation stabilization delay time is required after theoscillators restart.

In main clock mode, the oscillation stabilization delay time for the main clock is generated by thetimebase timer (the time can be selected from four options). In sub-clock mode, the oscillationstabilization delay time for the sub-clock is generated by the watch prescaler.

In main clock mode, if the selected interval time for the timebase timer is less than theoscillation stabilization delay time, an interval timer interrupt request will be generated during theoscillation stabilization delay. If necessary, disable output of interrupt requests from thetimebase timer (TBTC:TBIE = 0) before switching to stop mode in main clock mode.

Similarly, a watch interrupt request may be generated, depending on the selected interruptinterval time for the watch prescaler. If necessary, disable output of watch interrupt requestsfrom the watch prescaler (WPCR:WIE = 0) before switching to stop mode in sub-clock mode.

Table 3.7-9 Setting low-power consumption modes using the standby control register (STBC)

STBC registerMode

STP (bit7) SLP (bit6) TMD (bit3)

0 0 0 Normal

0 0 1 Watch

0 1 0 Sleep

1 0 0 Stop

88

3.8 Memory Access Mode


The only operating mode for memory access in the MB89170/170A/170L series is single-chip mode.

Single-chip mode

In single-chip mode, only internal RAM and ROM are used. Therefore, the CPU cannot accessareas other than the internal I/O area, RAM area, and ROM area (internal access).

Mode pins (MOD1, MOD0)

Always connect the mode pins (MOD1, MOD0) to "Vss, Vss."

The device reads the mode data and reset vector from internal ROM when a reset occurs.

Do not change the mode pin settings after the reset operation has completed (during operation).

Table 3.8-1 "Mode pin settings" lists the mode pin settings.

Table 3.8-1 Mode pin settings

Pin statesMeaning

MOD1 MOD0

Vss Vss Read the mode data and reset vector from internal ROM.

Vss Vcc Setting prohibited

Vcc Vss

Vcc Vcc

89

CHAPTER 3 CPU

Mode data

Always set the mode data in internal ROM to "00H" to select single-chip mode.

Figure 3.8-1 Structure of the mode data

Operation for selecting the memory access mode

Selecting mode other than single-chip mode is not possible.

Table 3.8-2 "Mode pins and mode data" shows the mode pins and mode data.

Figure 3.8-2 "Operation for selecting the memory access mode" shows the operation forselecting the memory access mode.

Data

00H

Other than 00H

Operation

Selects single-chip mode.

Reserved. Do not set.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0AddressF F F DH

Table 3.8-2 Mode pins and mode data

Memory access mode Mode pins (MODA) Mode data

Single-chip mode Vss, Vss 00H

Other modes Setting prohibited Setting prohibited

90


Figure 3.8-2 Operation for selecting the memory access mode.

Reset generated

Mode pins(MOD1,MOD0)

Other

Check mode pins.

Wait for reset to be released (external reset or oscillation stabilization delay time).

Set I/O pin functions for program execution(RUN) state.

Mode fetch

Check mode data.

Setting prohibited

Setting prohibited

Vss, Vss

The mode data is read from internal ROM

Single-chip mode

I/O pins at high impedance

Fetch mode data and reset vector from internal ROM

Single-chip mode (00H)

Mode data

Set I/O state of each pin in the port data direction registers (DDR), etc.

I/O pins can be used as ports.

Other

Reset in progress?

91

CHAPTER 3 CPU

92

CHAPTER 4 I/O PORTS

his chapter describes the functions and operations of the I/O ports.

4.1 "Overview of the I/O Ports"

4.2 "Port 0"

4.3 "Port 1"

4.4 "Port 2"

4.5 "Port 3"

4.6 "Port 4"

4.7 "I/O port program example"

93

CHAPTER 4 I/O PORTS

4.1 Overview of the I/O Ports

The device has five I/O ports (37 pins) consisting of output-only and general-purpose I/O ports (parallel I/O ports). The ports share pins with peripheral (peripheral function I/O pins).

I/O Port Functions

The I/O ports have functions for operating via the port data register (PDR) to output data fromthe CPU to the I/O pins or to read signals input to the I/O pins into the CPU. Also for someports, the I/O direction of I/O pins can be set via a port data direction register (DDR) in bits.

The following lists the functions of each port and the peripheral with which it shares pins.

• Port 0: General-purpose I/O ports/Shares pins with peripherals (external interrupt 2 pins)

• Port 1: General-purpose I/O ports

• Port 2: General-purpose I/O ports

• Port 3: Output-only ports/Shares pins with peripherals (serial I/O, timer, external interrupt 1,and buzzer pins)

• Port 4: Output-only ports

Table 4.1-1 "Port functions" lists the functions of each port and Table 4.1-2 "Port registers" liststhe port registers.

Table 4.1-1 Port functions

Port Pin Input typeOutput

typeFunction bit7 bi6 bit5 bit4 bit3 bit2 bit1 bit0

Port 0P00/INT20 to P07/INT27

CMOS (hysteresis)

CMOSpush-pull

General-purpose I/O port

P07 P06 P05 P04 P03 P02 P01 P00

External interrupt 2

INT27 INT26 INT25 INT24 INT23 INT22 INT21 INT20

Port 1 P10 to P17 CMOS


P17 P16 P15 P14 P13 P12 P11 P10

- - - - - - - - -

Port 2 P20 to P27 -


P27 P26 P25 P24 P23 P22 P21 P20

- - - - - - - - -

Port 3P30/SCK to P33/BZ

CMOS (hysteresis)


P37 P36 P35 P34 P33 P32 P31 P30

PeripheralBZ INT2 INT1

TO/INT0

EC SI SO SCK

Port 4 P40 to P44 -Nchopen-drain

Output-only port - - - P44 P43 P42 P41 P40

- - - - - - - - -

-:Not used.

94

4.1 Overview of the I/O Ports

Table 4.1-2 Port registers

Register Read/write Address Initial value

Port 0 data register (PDR0) R/W 0000H XXXXXXXXB

Port 0 data direction register (DDR0) W (*1) 0001H 00000000B

Port 1 data register (PDR1) R/W 0002H XXXXXXXXB

Port 1 data direction register (DDR1) W (*1) 0003H 00000000B

Port 2 data register (PDR2) R/W 0004H 00000000B

Port 3 data register (PDR3) R/W 000CH XXXXXXXXB

Port 3 data direction register (DDR3) R/W 000DH 00000000B

Port 4 data register (PDR4) R/W 000EH XXX11111B

*1 Bit manipulation instructions cannot be used on DDR0 and DDR1.R/W: Readable and writableR: Read-onlyW: Write-onlyX: Undefined

95

CHAPTER 4 I/O PORTS

4.2 Port 0

Port 0 is a general-purpose I/O port that shares pins with the external interrupt input pins. This section mainly describes the general-purpose I/O port functions.The section shows the structure, pins, pin block diagram, and associated registers for port 0.

Port 0 structure

Port 0 consists of the following three elements:

• General-purpose I/O pins/external interrupt 2 input pins (P00/INT20 to P07/INT27)

• Port 0 data register (PDR0)

• Port 0 data direction register (DDR0)

Port 0 pins

Port 0 has eight CMOS input and CMOS output I/O pins.

hen these pins are set as input pins, they can also function as external interrupt input pins.

Table 4.2-1 "Port 0 pins" lists the port 0 pins.

Table 4.2-1 Port 0 pins

Port Pin Function2 Shared peripheralI/O type Circuit

typeInput Output

Port 0

P00/INT20 P00 General-purpose I/O

INT20 External interrupt input 2

CMOS (*1) CMOS E















*1 The external interrupt inputs are hysteresis inputs.

96

4.2 Port 0

See Section 1.7 "Pin Descriptions" for more information on circuit types.

Port 0 block diagram

Figure 4.2-1 Block diagram of port 0 pin

Caution:

Pin values are continuously input to the external interrupt circuit. Therefore, when using thepin as a standard I/O port, you must disable the operation of the external interrupt circuitcorresponding to the pin. See Chapter 11 "EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)"for more information.

Port 0 registers

The registers associated with port 0 are PDR0 and DDR0.

Each bit of these registers corresponds to a pin of port 0.

Table 4.2-2 "Correspondence between port 0 registers and pins" lists the correspondencebetween the register bits and port 0 pins.

PDR read

PDR write

Output latch

Stop or watch mode (SPL=1)

PDR (Port data register)

Inte

rnal

dat

a bu

s

Pin

Pch

NchDDR

PDR read

Pull-up resistor(option)50 k approx. (at 5 V)

To external interrupt circuit External interrupt input enable


DDR write

Pch

(Port data direction register)

SPL: Pin state set bit in standby control register (STBC).

(In case of bit manipulation instructions)

Table 4.2-2 Correspondence between port 0 registers and pins

Port Pin corresponding to each register bit

Port 0PDR0, DDR0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Corresponding pin P07 P06 P05 P04 P03 P02 P01 P00

97

CHAPTER 4 I/O PORTS

4.2.1 Port 0 registers (PDR0, DDR0)

This section describes the port 0 registers.

Functions of the port 0 registers

Port 0 data register (PDR0)

The PDR0 register represents the pin states. Therefore, the output latch value ("0" or "1") canbe read for pins set as outputs but not for pins set as inputs.

Note:

As bit manipulation instructions (SETB and CLRB) read the output latch values rather thanthe pin level, bit manipulation instructions do not change the output latch value of bits otherthan the target bit.

Port 0 data direction register (DDR0)

The DDR0 register sets the pin input/output direction for individual bits.

Setting the bit corresponding to a port to "1" sets the port as an output port. Setting the bit to "0"sets the port as an input port.

Caution:

As the DDR0 register is write-only, bit manipulation instructions (SETB and CLRB) cannot beused.

Setting when used as external interrupt inputs

When using a pin as an external interrupt input, enable the operation of the external interruptcircuit and set the corresponding pin as an input port. In this case, the value of thecorresponding output latch has no meaning.

Table 4.2-3 "Port 0 register functions" lists the port 0 register functions.

Table 4.2-3 Port 0 register functions

Register Data Reading WritingRead/write

Address Initial value

Port 0 data register

0The pin level is "L".

Sets "0" to the output latch. Outputs the "L" level to the pin for the output port.

R/W0000H XXXXXXXXB

1The pin level is "H".

Sets "1" to the output latch. Outputs the "H" level to the pin for the output port.

Port 0 data direction register

0 Cannot be read (write-only).

Disables operation of the output transistor and sets as an input pin.

W0001H XXXXXXXXB

1Enables operation of the output transistor and sets as an output pin.

R/W: Readable and writableW: Write-onlyX: Undefined

98

4.2 Port 0

4.2.2 Port 0 operation

This section describes the operation of port 0.

Port 0 operation

Operation as an output port

• Setting the corresponding DDR0 register bit to "1" sets a port as an output port.

• When a port is set as an output port, operation of the output transistor is enabled and theoutput latch data is output to the pin.

• Writing data to the PDR0 register saves the data in the output latch and outputs the data tothe pin.

• Reading the PDR0 register reads the pin value.

Operation as an input port

• Setting the corresponding DDR0 register bit to "0" sets a port as an input port.

• When a port is set as an input port, the output transistor is turned off and the pin enters thehigh impedance state.

• Writing data to the PDR0 register saves the data in the output latch but does not output thedata to the pin.


Operation as an external interrupt input

• Set the DDR0 register bit corresponding to the external interrupt input pin to "0" to set the pinas an input port.

• Reading the PDR0 register reads the pin value regardless of whether external interrupt inputor interrupt request output is enabled or disabled.

Operation during a reset

• The DDR0 register values are initialized to "0" when the CPU is reset. This turns the outputtransistors off (input port) and sets the pins to high impedance state.

• The PDR0 register is not initialized by a reset. Therefore, if using pins as output ports,always set the output data in the PDR0 register before setting the ports as outputs in thecorresponding DDR0 register bits.

Operation during stop mode and watch mode

The pins enter the high impedance state if the pin state set bit in the standby control register(STBC:SPL) is "1" when the device switches to stop or watch mode. This is done by forciblyturning off the output transistors, regardless of the DDR0 register values. To prevent a leakcurrent due to open-circuit inputs, inputs are fixed.

99

CHAPTER 4 I/O PORTS

Table 4.2-4 "Port 0 pin states" lists the port 0 pin states.

Note:

For pins with a pull-up resistor selected as an option setting, the pin enters the "H" level(pulled-up state) rather than the high impedance state when the output transistor is turnedoff.

Table 4.2-4 Port 0 pin states

Pin

Normal operationMain-sleep

Main-stop (SPL = 0)Sub-sleep

Sub-stop (SPL = 0)Watch mode (SPL = 0)

Main stop (SPL = 1)Sub-stop (SPL = 1)

Watch mode (SPL = 1)During reset

P00/INT20 to P07/INT27 General-purpose I/O ports/external interrupt inputs

Hi-z(External interrupt inputs)

Hi-z

SPL: Pin state set bit in the standby control register (STBC:SPL)Hi-z: High impedance

100

4.3 Port 1

4.3 Port 1

Port 1 is a general-purpose I/O port.This section describes the structure, pins, pin block diagram, and associated registers for port 1.

Port 1 structure


• General-purpose I/O pins (P10 to P17)



Port 1 pins

Port 1 has eight I/O pins for CMOS input/CMOS output.




Port Pin Function Shared peripheralI/O type Circuit

typeInput Output

Port 1

P10 P10 General-purpose I/O

- CMOS CMOS F








101

CHAPTER 4 I/O PORTS



Port 1 register



Table 4.3-2 "Correspondence between port 1 registers and pins" lists the correspondencebetween the register bits and port 1 pins.

PDR read

PDR write

Output latch

Stop of watch mode (SPL=1)


Inte

rnal

dat

a bu

s

Pin

Pch

NchDDR

PDR read

Pull-up resistor (option)

50 k approx. (at 5 V)Stop of watch mode (SPL=1)

DDR write

Pch



(in case of bit manipulation instructions)





102

4.3 Port 1



Functions of the port 1 register


The PDR1 register represents the pin states. Therefore, the output latch value ("0" or "1") canbe read for pins set as outputs but not for pins set as inputs.

Note:

As bit manipulation instructions (SETB and CLRB) read the output latch values rather thanthe pin level, bit manipulation instructions do not change the output latch value of bits otherthan the target bit.



Setting the bit corresponding to a port to "1" sets the port as an output port.

Setting the bit to "0" sets the port as an input port.

Caution:

As the DDR1 register is write-only, the bit manipulation instructions (SETB and CLRB)cannot be used.





Port 1 data register


Sets "0" to the output latch. Outputs the "L" level to the pin for the output port.

R/W0002H XXXXXXXXB


Sets "1" to the output latch. Outputs the "H" level to the pin for the output port.

Port 1 data direction register

0 Cannot be read (write-only).


W0003H 0000000B

1Enables operation of the output transistor and sets as an output pin.


103

CHAPTER 4 I/O PORTS



Port 1 operation



• When a port is set as an output port, operation of the output transistor is enabled and theoutput latch data is output to the pin.

• Writing data to the PDR1 register saves the data in the output latch and outputs the data tothe pin.











The pins enter the high impedance state if the pin state set bit in the standby control register(STBC:SPL) is "1" when the device switches to stop or watch mode. This is done by forciblyturning off the output transistors, regardless of the DDR1 register values. To prevent a leakcurrent due to open-circuit inputs, inputs are fixed.

104

4.3 Port 1


Note:

For pins with a pull-up resistor selected as an option set, the pin enters the "H" level (pulled-up state) rather than the high impedance state when the output transistor is turned off.


Pin






P10 to P17 General-purpose I/O ports Hi-z Hi-z


105

CHAPTER 4 I/O PORTS

4.4 Port 2

Port 2 is an output-only pin.This section describes the structure, pin, pin block diagram, and associated registers for port 2.

Port 2 structure

Port 2 consists of the following two elements:

• Output-only pins (P20 to P27)


Port 2 pins

Port 2 has eight output-only pins with COMS outputs.





typeInput Output

Port 2

P20 P20 Output-only

- - CMOS H

P21 P21 Output-only

P22 P22 Output-only

P23 P23 Output-only

P24 P24 Output-only

P25 P25 Output-only

P26 P26 Output-only

P27 P27 Output-only

106

4.4 Port 2



Port 2 register

The register associated with port 2 is PDR2.

Each bit of PDR2 register corresponds to a pin of port 2.

Table 4.4-2 "Correspondence between port 2 register and pins" lists the correspondencebetween port 2 register and pins.

PDR read

PDR write

Output latch

Pin

Stop or watch mode(SPL=1)


Inte

rnal

dat

a bu

s

SPL: Pin state set bit in standby control register (STBC)

Pch

Nch

Table 4.4-2 Correspondence between port 2 register and pins


Port 2PDR2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0


107

CHAPTER 4 I/O PORTS

4.4.1 Port 2 register (PDR2)

This section describes the port 2 register.



The PDR2 register represents the output latch states. Therefore, the pin states cannot be read.




AddressInitial value


0The output latch value is "0".

Outputs an "L" level to the pin (Sets "0" to the output latch).

R/W 0004H 00000000B


Outputs an "H" level to the pin (Sets "1" to the output latch).


108

4.4 Port 2



Port 2 operation


Writing data to the PDR2 register saves the data in the output latch and outputs the data to thepin via the output buffer.


The PDR2 register values are initialized to "0" when the CPU is reset. The pins enter the highimpedance state during the reset, then enter the "L" level when the reset is released.


If the pin state set bit in the standby control register (STBC:SPL) is "1" when the deviceswitches to stop or watch mode, the output buffers are forcibly turned off and the pins enter thehigh impedance state.



Pin






P20 to P27 Output-only ports Hi-z Hi-z


109

CHAPTER 4 I/O PORTS

4.5 Port 3

Port 3 is a general-purpose I/O port that shares pins with the external interrupt inputs and peripheral I/O.This section principally describes the general-purpose I/O port functions.The section describes the structure, pins, pin block diagram, and associated registers for port 3.

Port 3 structure


• General-purpose I/O pin/external interrupt 1 input pins and peripheral I/O pins (P30/SCK toP37/BZ)



Port 3 pins

Port 3 has eight I/O pins for CMOS input and CMOS output.

When set as inputs, these pins also function as external interrupt input pins.

When the pins that are shared with peripherals are used by the peripheral, the pins cannot beused as general-purpose I/O ports.





typeInput Output

Port 3

P30/SCK P20 General-purpose I/O SCK 8-bit serial I/O clock I/O

Hysteresis CMOS G

P31/SO P21 General-purpose I/O S01 8-bit serial I/O data output

P32/SI P22 General-purpose I/O SI 8-bit serial I/O data input

P33/EC P23 General-purpose I/O EC 8/16-bit timer pulse input

P34/TO/INTO

P24 General-purpose I/O TO 8/16-bit timer output/INT0/external interrupt input 0

P35/INT1 P25 General-purpose I/O INT1 External interrupt input 1

P36/INT2 P26 General-purpose I/O INT2 External interrupt input 2

P37/BZ P27 General-purpose I/O BZ Buzzer output

110

4.5 Port 3



Caution:

Pin values are continuously input to the external interrupt circuit. Therefore, when using thepin as a standard I/O port, you must disable the operation of the external interrupt circuitcorresponding to the pin. See Chapter 10 "EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)"for more information.

Port 3 registers



Table 4.5-2 "Correspondence between port 3 registers and pins" lists the correspondencebetween port 3 registers and pins.

Pin

Pch

Nch


Pch

PDR read

PDR read

PDR write

DDR write

DDR read

Output latch


From peripheral outputFrom peripheral output enable


DDR

Inte

rnal

dat

a bu

s


Stop or watch mode(SPL=1)


To peripheral input

To external interrupt circuitExternal interrupt input enable

P34 to P36 only

(in case of bit manipulation instructions)





111

CHAPTER 4 I/O PORTS



Functions of the port 3 registers


The PDR3 register represents the pin states. Therefore, the output latch value ("0" or "1") canbe read for pins set as outputs but it cannot be read for pins set as inputs.

Note:

As bit manipulation instructions (SETB, CLRB) read the output latch values rather than thepin level, bit manipulation instructions do not change the output latch value of bits other thanthe target bit.



Setting the bit corresponding to a port to "1" sets the port as an output port. Setting the bit to "0"sets the port as an input port.

Settings when used as external interrupt inputs

When using a pin as an external interrupt input, enable the operation of the external interruptcircuit and set the pin as an input port. In this case, the value of the corresponding output latchhas no meaning.

Setting when used as peripheral outputs

When using a peripheral with an output pin, set the output enable bit for the peripheral toenable.

As the peripheral output has priority, the PDR3 register or the set value of DDR3 correspondingto the peripheral output pin has no meaning, regardless of the output value or output enablestatus of the peripheral.

Settings when used as peripheral inputs

When using a peripheral with an input pin, set the pin corresponding to the peripheral input asan input port. In this case, the value of the corresponding output latch has no meaning.


112

4.5 Port 3






Sets "0" to the output latch. If the pin is an output, outputs an "L" level to the pin.

R/W

000CH XXXXXXXXB


Sets "1" to the output latch. If the pin is an output, outputs an "H" level to the pin.


0Pin is an input.


000DH 00000000B

1Pin is an output.

Enables operation of the output transistor and sets as an output pin.

R/W: Readable and writableX: Undefined

113

CHAPTER 4 I/O PORTS



Port 3 operation



• When a port is set as an output port, operation of the output transistor is enabled and theoutput latch data is output from the pin.

• Writing data to the PDR3 register saves the data in the output latch and output the data tothe pin.







Operation as an external interrupt input

• Set the DDR3 register bit corresponding to the external interrupt input pin to "0" to set the pinas an input port.

• Reading the PDR3 register reads the pin value regardless of whether external interrupt inputor interrupt request output is enabled or disabled.

Operation as a peripheral output

• Setting the output enable bit of the peripheral to enabled sets the corresponding pin as aperipheral output.

• The pin value can be read from the PDR3 register even when the peripheral output isenabled. This enables the output value of the peripheral to be read.

Operation as a peripheral input

• Set the DDR3 register bit corresponding to the peripheral input pin to "0" to set the pin as aninput port.

• The peripheral input continuously inputs the pin value (other than in stop mode or watchmode).

• Reading the PDR3 register reads the pin value regardless of whether the peripheral is usingthe input pin.

114

4.5 Port 3





The pins enter the high impedance state if the pin state set bit in the standby control register(STBC:SPL) is set to "1" when the device switches to stop or watch mode. This is done byforcibly turning off the output transistors, regardless of the DDR3 register values. To prevent aleak current due to open-circuit inputs, inputs are fixed.


Note:

For pins with a pull-up resistor selected as an option setting, the pin enters the "H" level(pulled-up state) rather than the high impedance state when the output transistor is turnedoff.


Pin






P34/T0/INT0P35/INT1P36/INT2

General-purpose I/O ports/External interrupt inputs/Peripheral I/O

Hi-z(External interrupt inputs)

Hi-z

P30/SCK to P33/ECP37/BZ

General-purpose I/O ports/Peripheral I/O

Hi-z


115

CHAPTER 4 I/O PORTS

4.6 Port 4

Port 4 is an output-only port.This section describes the structure, pins, pin block diagram, and associated registers for port 4.

Port 4 structure

Port 4 consists of the following two elements.

• Output-only pins (P40 to P44)


Port 4 pins

Port 4 pins are made up of five output-only pins with N-channel open-drain outputs.





typeInput Output

Port 4

P40 P40 Output-only

- -N-ch

open-drainI

P41 P41 Output-only

P42 P42 Output-only

P43 P43 Output-only

P44 P44 Output-only

116

4.6 Port 4



Port 4 register

The register associated with port 4 is PDR4.

Each bit of the PDR4 register corresponds to a pin of port 4.

Table 4.6-2 "Correspondence between port 4 register and pins" lists the correspondencebetween the port 4 register and pins.

PDR read

PDR write

Output latchPin


PDR (Port data register)In

tern

al d

ata

bus



Nch

Table 4.6-2 Correspondence between port 4 register and pins


Port 4PDR4 - - - bit4 bit3 bit2 bit1 bit0

Corresponding pin - - - P44 P43 P42 P41 P40

117

CHAPTER 4 I/O PORTS

4.6.1 Port 4 register (PDR4)

This section describes the port 4 register.



The PDR4 register represents the output latch states. Therefore, the pin states cannot be read.







Outputs an "L" level to the pin.(Sets "0" to the output latch and turns on the output transistor.)

R/W 000EH XXX11111B


The pins enter the high impedance state.(*1)(Sets "1" to the output latch and turns off the output transistor.)

R/W: Readable and writable*1 Pins with a pull-up resistor selected as an option enter the pulled-up state.

118

4.6 Port 4



Port 4 operation


• Writing data to the PDR4 register saves the data in the output latch. When the output latchis "0", the output transistor goes on and the pin outputs an "L" level. When the output latch is"1", the output transistor goes off and the pin enters the high impedance state.

• Reading the PDR4 register always reads the output latch values.


The PDR4 register values are initialized to "1" when the CPU is reset. This turns off all theoutput transistors and sets the pins to high impedance state.


If the pin state set bit in the standby control register (STBC:SPL) is "1" when the deviceswitches to stop or watch mode, the output transistors are forcibly turned off and the pins enterthe high impedance state.


Note:

When the output transistor is turned off for pins with a pull-up resistor selected as an optionsetting, the pins enter the "H" level (pulled-up state) rather than the high impedance state.


Pin






P10 to P17 General-purpose I/O ports Hi-z Hi-z


119

CHAPTER 4 I/O PORTS

4.7 I/O port program example

This section shows an example program using the I/O ports.

I/O port program example

Program specifications

• Ports 0 and 1 are used to turn on all seven-segment LED lights (eight segments includingthe decimal point).

• P00 is used as the anode common pin of the LED and pins P10 to P17 correspond to eachsegment pin.

Figure 4.7-1 "Eight-segment LED connection example" shows the eight-segment LEDconnection example.

Figure 4.7-1 Eight-segment LED connection example

Coding example

Figure 4.7-2 TIMEBASE TIMER

PDR0 EQU 0000H ;Address of the port 0 data PDR0 EQU 0001H ;Address of the port 0 data direction registerPDR1 EQU 0002H ;Address of the port 1 data registerDDR1 EQU 0003H :Addressof the port 1 data direction register;---------Main program---------------------------------------------- CSEG ; [CODE SEGMENT] : CLRB PDR0:0 ;Set P00 to the "L" level MOV PDR1, #11111111B ;Set all port 1 pins to the "H" level. CLRB PDR0, #11111111B ;Set P00 as an output, #xxxxxxx1B. CLRB DDR1, #11111111B ;Set all port 1 bits as outputs. : ENDS;-------------------------------------------------------------------

P00

P17

P16

P10

MB89170

120

4.7 I/O port program example

END

121

CHAPTER 4 I/O PORTS

122

CHAPTER 5 TIMEBASE TIMER

This chapter describes the functions and operation of the timebase timer.

5.1 "Overview of the Timebase Timer"

5.2 "Structure of the Timebase Timer"

5.3 "Timebase Timer Control Register (TBTC)"

5.4 "Timebase Timer Interrupt"

5.5 "Operation of the Timebase Timer"

5.6 "Notes on Using the Timebase Timer"

5.7 "Timebase Timer Program Example"

123


5.1 Overview of the Timebase Timer

The timebase timer is a 21-bit free-run counter which counts up synchronized with the internal count clock (main clock source oscillation divided by two). The timebase timer has an interval timer function which can be set to one of four different interval times. The timebase timer is also used as the timer output for the oscillation stabilization delay time and as the operation clock for the watchdog timer. Operation of the timebase timer halts in modes in which the main clock source oscillation halts.

Interval timer function

The interval timer function generates interrupts at fixed time intervals.

• An interrupt is generated when the interval timer bit overflows on the counter of the timebasetimer.

• The interval timer bit (interval time) can be selected from four options.

Table 5.1-1 "Timebase timer interval times" lists the interval times for the timebase timer.

Clock supply function

The clock supply function supplies the timer output used to generate the oscillation stabilizationdelay time for the main clock (four available times) and the operation clock for some peripheralfunctions.

Table 5.1-2 "Clocks supplied by the timebase timer" lists the periods of the clocks supplied fromthe timebase timer to the various peripherals.

Table 5.1-1 Timebase timer interval times

MB89170 series MB89170A/170L series

Internal count clock period

Interval timeInternal

count clock period

Interval time

2/FCH (0.56µs) 213/FCH (approx. 2.29 ms) 2/FCH (0.28µs) 213/FCH (approx. 1.14 ms)

213/FCH (approx. 9.15 ms) 213/FCH (approx. 4.58 ms)



FCH: Main clock source oscillationThe figures in parentheses () are the values when the main clock source oscillation is 3.58 MHz (for the MB89170 series) or 7.16 MHz (for the MB89170A/170L series).

124

5.1 Overview of the Timebase Timer

Note:

As the period of the oscillation is unstable immediately after oscillation starts, the listedoscillation stabilization delay times are guides only.

Table 5.1-2 Clocks supplied by the timebase timer

Clock supply destination

Clock period Remarks

MB89170 series MB89170A series

Main clock oscillation stabilization delay time

23/FCH (approx. 0.0 ms) 23/FCH (approx. 0.0 ms) Selected using the oscillation stabilization delay time select bits in the system clock control register (SYCC:WT1, WT0) in the clock controller.




Watchdog timer 222/FCH (approx. 1171.6 ms) 222/FCH (approx. 585.8 ms) Count-up clock for the watchdog timer.

Buzzer output 210/FCH to 213/FCH (0.29 to 2.29 ms approx.)

210/FCH to 213/FCH (0.14 to 1.14 ms approx.)

See Chapter 9 "BUZZER OUTPUT".

FCH: Main clock source oscillationThe figures in parentheses () are the values when the main clock source oscillation is 3.58 MHz (for the MB89170 series) or 7.16 MHz (for the MB89170A series).

125


5.2 Structure of the Timebase Timer

The timebase timer consists of the following four blocks:• Timebase timer counter• Counter clear circuit• Interval time selector• Timebase timer control register (TBTC)

Block diagram of timebase timer

Figure 5.2-1 Block diagram of timebase timer

Timebase timer counter

This 21-bit up-counter uses the main clock source oscillation divided by two as its count clock.Operation halts if the main clock source oscillation halts.

Counter clear circuit

The counter can be cleared by a TBTC register setting (TBR = 0). The circuit also clears thecounter when the device enters main stop mode (STBC:STP = 1) or sub-clock mode(SYCC:SCS = 0), or when a power-on reset (option) occurs.

Interval time selector

This circuit selects which of the four available timebase timer counter bits is to be used as the


Power-on reset

Stop mode start(in main clock mode)

IRQ6Timebase timer interrupt

TBC0 TBRTBC1TBOF TBIE

Watchdog timer clear

OF: OverflowFCH: Main clock source oscillation

Sub-clock mode start

Counter clear

Timebase timer control register (TBTC)

x21 x23 x214 x215 x216 x217 x221 x213 x212 x211x22

Timebase timer counterTo watchdog timer

Interval timer selector

To oscillation stabilization delay time selector in clock counter

To buzzer output

OFOF OF

OF

x210 x29 x28 x27 x26FCH

divided by two

126

5.2 Structure of the Timebase Timer

interval timer bit. An overflow on the selected bit causes an interrupt.


Used to select the interval time, clear the counter, control interrupts, and check the status.

127


5.3 Timebase Timer Control Register (TBTC)

The timebase timer control register (TBTC) is used to select the interval time, clear the counter, control interrupts, and check the status.


Figure 5.3-1 Timebase timer control register (TBTC)

TBIE

0

1

TBC1

0

0

1

1

213 / FCH

215 / FCH

218 / FCH

222 / FCH

TBC0

0

1

0

1


0 0 0 AH

Address

00XXX000B

Initial value

TBC0 TBRTBC1

R/W R/W WR/WR/W

TBIE

Interrupt request enable bit

Disable output of interrupt requests.

Enable output of interrupt requests.

TBOFOverflow interrupt request flag bit

No overflow on specified bit.

Clear this bit.0

1

Interval time select bits

Read Write

FCH:Main clock source oscillation

TBOF

R/W : Readable and writable W : Write-only - : Unused X : Undefined : Initial value

Overflow occurred on specified bit.

TBRTimebase timer initialize bit

Clear the timebase timer counter.

0

1

Read Write

Reading always returns "1".

No change. No other effect.


128

5.3 Timebase Timer Control Register (TBTC)

Table 5.3-1 Function of each timebase timer control register (TBTC) bit

Bit name Function

bit7 TBOF:Overflow interrupt request flag bit

• Set to "1" when an overflow occurs on the specified bit of the timebase timer counter.

• An interrupt request is output if both this bit and the interrupt request enable bit (TBIE) are "1".

• Writing "0" clears the bit. Writing "1" does not change the bit value and has no other effect.

bit6 TBIE:Interrupt request enable bit

This bit enables or disables output of an interrupt request to the CPU. An interrupt request is output if both this bit and the overflow interrupt request flag bit (TBOF) are "1".

bit5bit4bit3


bit2bit1

TBC1, TBC0:Interval time select bits

These bits select the period of the interval timer. The bits specify the interval timer bit in the timebase timer counter.Four different interval times are available.

bit0 TBR:Timebase timer initialize bit

This bit clears the timebase timer counter.Writing "0" to this bit clears the counter to "000000H". Writing "1" does not change the bit value and has no other effect. Note:

Reading always returns "1".

129


5.4 Timebase Timer Interrupt

An overflow on the specified bit of the timebase timer counter triggers a timebase timer interrupt (interval timer function).

Interrupt when operating the interval timer function

The counter counts up on the interval count clock until an overflow occurs on the selectedinterval timer bit. This sets the overflow interrupt request flag bit (TBTC:TBOF) to "1". If theinterrupt request enable bit is enabled (TBTC:TBIE = 1) at this time, an interrupt request (IRQ6)is output to the CPU. Write "0" to the TBOF bit with the interrupt processing routine. The TBOFbit is set when an overflow occurs on the specified bit, regardless of the TBIE bit value.

Caution:

When enabling output of interrupt requests (TBIE = 1) after release of a reset, always clearthe TBOF bit (TBOF = 0) at the same time.

Note:

- An interrupt request is generated immediately if the TBOF bit is "1" when the TBIE bit isswitched from disabled to enabled (0 -> 1).

- If the counter is cleared (TBTC:TBR = 0) at the same time that the selected bit overflows,the TBOF bit is not set.

Oscillation stabilization delay time and timebase timer interrupt

If the interval time is set shorter than the oscillation stabilization delay time for the main clock,an interval interrupt request from the timebase timer (TBTC:TBOF = 1) will occur when startingoperation in main clock mode. In this case, disable the timebase timer interrupt (TBTC:TBIE =0) before the operation is switched to a mode in which the main clock halts (main-stop mode orsub-clock mode).

Register and vector table for the timebase timer interrupt

See Section 3.4.2 "Processing during an interrupt" for more information on interrupt operation.

Table 5.4-1 Register and vector table for the timebase timer interrupt

InterruptInterrupt level setting register Vector table address

Register Setting bits Upper Lower

IRQ6 ILR2 (007DH) L61 (bit5) L60 (bit4) FFEEH FFEFH

130

5.5 Operation of the Timebase Timer

5.5 Operation of the Timebase Timer

The timebase timer operates as an interval timer function and as a clock source for some peripherals.

Operation of the interval timer function (timebase timer)

Figure 5.5-1 "Interval timer function settings" shows the settings required to operate thetimebase timer as an interval timer function.

Figure 5.5-1 Interval timer function settings

When the main clock oscillation is operating, the counter of the timebase timer counts upcontinuously synchronized with the internal count clock (main clock source oscillation divided bytwo).

When the counter is cleared (TBR = 0), the count restarts from zero. When an overflow occurson the interval timer bit, the overflow interrupt request flag bit (TBOF) is set to "1". In otherwords, the timebase timer generates interrupt requests at fixed intervals relative to the time atwhich the counter was cleared.

Operation of the clock supply function

The timebase timer is also used as a timer to generate the oscillation stabilization delay time forthe main clock. The counter of the timebase timer counts up from zero until an overflow occurson the oscillation stabilization delay time bit. This time becomes the oscillation stabilizationdelay time. The oscillation stabilization delay time can be selected from four available timesusing the oscillation stabilization delay time selection bits in the system clock control register(SYCC:WT1, WT0).

The timebase timer also provides the clock for the watchdog timer and buzzer output. Clearingthe counter of the timebase timer has an effect on the buzzer output operation. Also, when thetimebase timer output is selected (WDTC:CS = 0), clearing the timebase timer counter alsoclears the watchdog timer counter.


TBTC TBC0 TBRTBC1

1 00

TBIETBOF : Used bit 1 : Set "1". 0 : Set "2".

131


Operation of the timebase timer

Figure 5.5-2 "Operation of the timebase timer" shows the operation in the following states:

• When a power-on reset occurs.

• When the device enters sleep mode while the interval timer function is operating in mainclock mode.

• When the device enters main-stop mode.

• When a counter clear request occurs.

The timebase timer is cleared and operation halts during sub-clock mode and main-stop mode.The timebase timer count is used to generate the oscillation stabilization delay time when thedevice returns from sub-clock mode or main-stop mode.

Figure 5.5-2 Operation of the timebase timer

TBOF bit

1FFFFFH

00000H

Counter value

Oscillation stabilization delay overflow

CPU operation starts.

Power-on reset (option)

Interval period (TBTC:TBC1, TBC0=11H))

Cleared in the interrupt processing routine.

Sleep

StopSLP bit(STBC register)

STP bit(STBC register)

Counter clear(TBTC:TBR=0)

Cleared due to switch to main stop mode.

:Indicates the oscillation stabilization delay time.

Wakeup from sleep mode by IRQ6.

TBIE bit

Wakeup from stop mode via external interrupt.

For the case where the interval timer set bits of the timebase timer control register (TBTC:TBC1, TBC0) are "11B" (222/FCH).

132

5.6 Notes on Using the Timebase Timer

5.6 Notes on Using the Timebase Timer

This section describes points to note when using the timebase timer.

Notes on using the timebase timer

Notes on setting by using the program

System cannot return from interrupt processing if the interrupt request flag bit (TBTC:TBOF) is"1" and the interrupt request enable bit is enabled (TBTC:TBIE = 1). Always clear the TBOF bit.

Clearing the timebase timer

In addition to clearing the timebase timer using the timebase timer initialize bit (TBTC:TBR = 0),the timer is also cleared when the elapse of the oscillation stabilization delay time is required forthe main clock. When the timebase timer is selected as the count clock for the watchdog timer(WDTC:CS = 0), clearing the timebase timer also clears the watchdog timer.

When used as the timer for the oscillation stabilization delay time

The main clock oscillation is halted at power-on, during main-stop mode, and during sub-clockmode. Consequently, the timebase timer is used to provide an oscillation stabilization delaytime for the main clock when the oscillator starts operating.

A suitable oscillation stabilization delay time must be selected based on the type of resonatorconnected to the main clock oscillator (clock generator).

See Section 3.6.1 "Clock generator" for more information.

Notes on peripheral functions which receive a clock from the timebase timer

In modes in which the source oscillation of the main clock halts, the counter is cleared and theoperation of the timebase timer halts. As the output starts from the initial state when the counterof the timebase timer is cleared, the length of the "H" level on the clocks supplied from thetimebase timer may be shortened and that of the "L" level lengthened by up to one half theperiod. Output of the clock to the watchdog timer also starts from the initial state. However, asthe counter of the watchdog timer is cleared at the same time, the watchdog timer operatesunder a normal period.

Figure 5.6-1 "Effect on the buzzer output of clearing the timebase timer" shows the effect on thebuzzer output of clearing the timebase timer.

133


Figure 5.6-1 Effect on the buzzer output of clearing the timebase timer

Counter value

XXX3FFH

XXX200H

XXX000H

Counter clear by the program (TBTC:TBR=0)

Clock supplied to the buzzer output

X: Any value. Cleared value is "0". For the case when "001B" is set in the buzzer selection bits of the buzzer register (BZCR:BZ2, BZ1, BZ0). (Main clock source oscillation divided by 2048. Outputs approximately 1.75/3.50 kHz when operating at 3.58/7.16 MHz.)

134

5.7 Timebase Timer Program Example

5.7 Timebase Timer Program Example

This section describes an example program using the timebase timer.

Timebase timer program example


Repeatedly generates interval timer interrupts at 218/FCH (FCH: main clock source oscillation)intervals. The interval time in this case is approximately 73.2 or 36.6 ms (at 3.58 or 7.16 MHz).

Coding example

TBTC EQU 0000AH ;Address of the timebase timer control register

TBOF EQU TBTC:7 ;Address of Interrupt request flag bit definition

ILR2 EQU 007DH ;Address of the interrupt level setting

INT_V DSENG ABS ;[DATA SEGMENT] ORG 0FFEEHIRQ6 DW WARI ;Interrupt vector settingINT_V ENDS;---------Main program---------------------------------------------- CSEG ;[CODE SEGMENT] ;Assume stack pointer (SP), etc., ;already initialized. : CLRI ;Disable interrupts. MOV ILR2,#11011111B ;Set interrupt level (level 1). MOV TBTC,#01000100B ;Clear interrupt request flag bit, ;enable output of interrupt requests, ;select 218/FCH, clear timebase timer. SETI ;Enable interrupts. :;----------Interrupt program----------------------------------------WARI CLRB TBOF ;CLEAR INTERRUPT REQUEST FLAG. PUSHW A XCHW A, T PUSHW A : User processing. : POPW A XCHW A ,T POPW A RETI ENDS

135


;----------------------------------------------- END

136

CHAPTER 6 WATCHDOG TIMER

This chapter describes the functions and operation of the watchdog timer.

6.1 "Overview of the Watchdog Timer"

6.2 "Structure of the Watchdog Timer"

6.3 "Watchdog Control Register (WDTC)"

6.4 "Operation of the Watchdog Timer"

6.5 "Notes on Using the Watchdog Timer"

6.6 "Watchdog Timer Program Example"

137


6.1 Overview of the Watchdog Timer

The watchdog timer is a 1-bit counter that uses the output of either the timebase timer (which operates on the main clock) or the watch prescaler (which operates on the subclock) as its count clock. once started, the watchdog timer resets the cpu if not cleared within fixed time.

Function of the watchdog timer

The watchdog timer is a counter used to prevent program runaway. once started, the timermust be periodically cleared within a fixed time. If a program fails to clear the timer within thistime because the program has entered an infinite loop for example, the timer generates awatchdog reset to the cpu for four instruction cycles.

The output of either the timebase timer or watch prescaler can be selected as the count clockfor the watchdog timer.

Table 6.1-1 "Watchdog timer interval time" lists the interval time for the watchdog timer. If Thewatchdog timer is not cleared, the watchdog reset occurs between the minimum and maximumtime. Always clear the counter within the listed minimum time.

See Section 6.4 "Operation Of The Watchdog Timer" for the minimum and maximum watchdogtimer interval times.

Caution:

When the output of the timebase timer is selected as the count clock, clearing the timebasetimer (tbtc:tbr = 0) also clears the counter of the watchdog timer. Similarly, When the outputof the watch prescaler is selected as the count clock, clearing the watch prescaler (wpcr:wclr= 0) also clears the counter of the watchdog timer. Therefore, If The counter being used asthe count clock (timebase timer or watch prescaler) is repeatedly cleared within the intervaltime of the watchdog timer, the watchdog timer function does not operate.

Table 6.1-1 Watchdog timer interval time

Count clock

Timebase timer output(MB89170 series: For 3.58 MHz main clock

source oscillation)(MB89170A/170L series: For 7.16 MHz

main clock source oscillation)

Watch prescaler output(for 32.768 kHz subclock source

oscillation)

Minimum time Approx. 585.8 ms(*1) (MB89170 series)Approx. 292.9 ms(*1)(MB89170A/170L series)

500 ms (*2)

Maximum time Approx. 1171.6 ms (MB89170 series)Approx. 585.8 ms (MB89170A/170L series)

1000 ms

*1 Main clock source oscillation (FCH) divided by 2 x number of timebase timer counts (221)*2 Sub-clock source oscillation (FCL) period x number of watch prescaler counts (214)Note:

For the MB89170L series, the watch prescaler output cannot be used.

138

6.1 Overview of the Watchdog Timer

Note:

Switching to sleep mode, stop mode, or watch mode clears the watchdog timer counter andhalts operation until normal operation (run state) resumes.

139


6.2 Structure of the Watchdog Timer

The watchdog timer consists of the following six blocks:• Count clock selector• Watchdog timer counter• Reset control circuit• Watchdog timer clear selector• Counter clear control circuit• Watchdog control register (WDTC)

Block diagram of watchdog timer

Figure 6.2-1 Block diagram of watchdog timer

Count Clock Selector

Selects the count clock for the watchdog timer counter. the output of either the timebase timeror watch prescaler can be selected.

Watchdog Timer Counter (1-bit Counter)

A 1-bit counter that uses the output of either the timebase timer or watch prescaler as its countclock.

Reset Control Circuit

Generates a reset signal to the cpu when the watchdog timer counter overflows.

Reset control circuit

1-bit counter OverflowRST

Watchdog control register (WDTC)

Watchdog timer

Count clock selector

222/FCH

(Timebase timer output)

214/FCL

(Watch prescaler output)

Counter clear control circuit

Sleep mode startStop mode startWatch mode start

Watchdog timer clear selector

Clear signal from timebase timer

Clear signal from watch prescaler

WTE0CS WTE3 WTE2 WTE1

Clear Start

FCH: Main clock source oscillationFCL: Subclock source oscillation

- - -

140

6.2 Structure of the Watchdog Timer

Watchdog timer clear selector

Selects the watchdog timer clear signal from either the timebase timer or watch prescaler at thesame time as the count clock selector.

Counter clear control circuit

Controls clearing of the watchdog timer counter and halting operation.

Watchdog control register (Wdtc)

Selects the count clock and starts or clears the watchdog timer counter. as the register is write-only, bit manipulation instructions cannot be used.

141


6.3 Watchdog Control Register (WDTC)

The watchdog control register (WDTC) is used to start and clear the watchdog timer.

Watchdog control register (WDTC)

Figure 6.3-1 Watchdog control register (WDTC)

WTE3

0


0 0 0 9H

Address

WTE0

Watchdog control bit

CS WTE3 WTE2 WTE1

W W W W

WTE2

1

WTE1

0

WTE0

1

0XXXXXXXB

Initial value

R/W :Readable and writable W :Write-only - :Unused X :Undefined

:Initial valueNote: As the register is write-only, bit manipulation instructions cannot be used.*1: FCH=Main clock source oscillation*2: FCL=Sub-clock source oscillation

CS

0

1

Count clock selection bit

R/W

Other than the above No operation

- Clears the watchdog timer (for the second and subsequent write after a reset).

- Starts the watchdog timer (for the first write after a reset).

- - -

Watch prescaler output period (214/FCL*2)

Timebase timer output period (222/FCH*1)

Table 6.3-1 Function of each watchdog control register (WDTC) bit

Bit name Function

bit7 CS:Count clock selection bit

Selects the count clock for the watchdog timer when the timer starts. The output of either the timebase timer or watch prescaler can be selected.Caution:

If using sub-clock mode, always select the output of the watch prescaler.Select the count clock when the watchdog timer starts. Do not change the selection after the watchdog timer starts.Bit manipulation instructions cannot be used.

bit6bit5bit4


142

6.3 Watchdog Control Register (WDTC)

bit3bit2bit1bit0

WTE3, WTE2, WTE1, WTE0:Watchdog control bits

• Writing "0101B" starts (for the first write after a reset) or clears (for the second and subsequent write after a reset) the watchdog timer.

• Writing other than "0101B" has no effect on operation.Caution:

The read value is "1111B". Bit manipulation instructions cannot be used.

Table 6.3-1 Function of each watchdog control register (WDTC) bit (Continued)

Bit name Function

143


6.4 Operation of the Watchdog Timer

The watchdog timer generates a watchdog reset when an overflow occurs on the watchdog timer counter.

Operation of the watchdog timer

Starting the watchdog timer

• Writing "0101B" to the watchdog control bits of the watchdog control register (WDTC:WTE3to WTE0) for the first time after a reset starts the watchdog timer. specify the count clockselection bit (WDTC:CS) at the same time.

• Once started, the watchdog timer cannot be halted other than by a reset.

Clearing the watchdog timer

• Writing "0101B" to the watchdog control bits of the watchdog control register (WDTC:WTE3to WTE0) for the second and subsequent times clears the counter of the watchdog timer.

• If the counter is not cleared within the watchdog timer interval time, the counter overflowsand an internal reset signal for four instruction cycles is generated.

Watchdog timer interval time

The interval time depends on the watchdog timer clear timing. Figure 6.4-1 "watchdog timerclear timing and interval time" shows the relationship between the watchdog timer clear timingand the interval time, set when the output of the timebase timer is selected as the count clock(main clock source oscillation: MB89170 Series = 3.58 mhz, MB89170A/170l Series = 7.16MHz).

Figure 6.4-1 Watchdog Timer Clear Timing And Interval Time

Maximum time

Count clock output of the timebase timer

Minimum time

Watchdog reset

Watchdog 1-bit counter

Count clock output of the timebase timer

Watchdog reset

Watchdog 1-bit counter

585.8ms (MB89170 series)292.9ms (MB89170A/170L series)

1171.6ms (MB89170 series)585.8ms (MB89170A/170L series)

Overflow

Overflow

Watchdog clear

Watchdog clear

144

6.5 Notes on Using The Watchdog Timer

6.5 Notes on Using The Watchdog Timer

This Section describes points to be noted for using the watchdog timer.

Notes on using the watchdog timer

Halting the watchdog timer

Once started, the watchdog timer cannot be halted other than by a reset.

Selecting the count clock

The count clock selection bit (WDTC:CS) can be set only when "0101B" is written to thewatchdog control bits (WDTC:WTE3 TO WTE0) to start the watchdog timer. accordingly, the bitcannot be changed with bit manipulation instructions. do not change the setting after startingthe watchdog timer.

As the main clock oscillation halts in sub-clock mode, the timebase timer does not operate inthis mode.

To use the watchdog timer in sub-clock mode, you must first select the watch prescaler for thecount clock (WDTC:CS = 1).

Clearing the watchdog timer

• Clearing the counter (timebase timer or watch prescaler) being used for the count clock forthe watchdog timer also clears the watchdog timer counter.

• Switching to sleep mode, stop mode, or watch mode clears the watchdog timer counter.

Notes on writing programs

When writing a program that repeatedly clears the watchdog timer in the main loop of theprogram, the processing time for the main loop (including interrupt processing) must be lessthan the minimum value of the watchdog timer interval time.

Operation in sub-clock mode

If a watchdog reset occurs in sub-clock mode, operation restarts in main clock mode after theoscillation stabilization delay time has elapsed. therefore, if the reset output has been selectedas an option setting, the reset signal is output during the oscillation stabilization delay time.

145


6.6 Watchdog Timer Program Example

This section describes an example of a program using the watchdog timer.

Watchdog timer program example


• Immediately after the start of the program, select the watch prescaler for the count clock andstart the watchdog timer.

• Clear the watchdog timer in each iteration of the main program loop.

• The main loop (including interrupt processing) must be executed within a time period that isless than the minimum watchdog timer interval time (approximately 585.8 ms at 3.58 MHz(MB89170 Series) or 292.9 ms at 7.16 MHz (MB89170A Series)).

Coding example

WDTC EQU 00009H ;Address of the watchdog control ;registerWDT_CLR EQU 10000101B

VECT EQU ABS ;[DATA SEGMENT] ORD 0FFFEHRST_V DW PROG ;Set reset vectorVECT ENDS;---Main Program--------------------------------------------------- CSEG ;[CODE SEGMENT]PROG ;Initialization routine for reset MOVW SP,#0280H ;Set an initial value for the stack ;pointer (for interrupt processing). : Initialize Peripheral Functions (Interrupts), Etc. :INIT MOV WDTC,#WDT_CLR ;Start the watchdog timer. ;Select the watch prescaler for the ;for the count clock. :MAIN MOV WDTC,#WDT_CLR ;Clear the watchdog timer. : User Processing (Interrupt Processing May Occur During This Period) : JMP MAIN ;Execution must loop within the minimum ;watchdog timer interval time. ENDS;------------------------------------------------------------------- END

146

CHAPTER 7 8/16-BIT TIMER/COUNTER

This chapter describes the functions and operation of the 8/16-bit timer/counter.

7.1 "Overview of the 8/16-Bit Timer/Counter"

7.2 "Structure of the 8/16-Bit Timer/Counter"

7.3 "8/16-Bit Timer/Counter Pins"

7.4 "8/16-Bit Timer/Counter Registers"

7.5 " 8/16-Bit Timer/Counter Interrupts"

7.6 "Operation of the Interval Timer Function"

7.7 "Operation of the Counter Function"

7.8 "Operation of the Square Wave Output Initialization Function"

7.9 "Halting and Restarting the 8/16-Bit Timer/Counter"

7.10 "State in Each Mode of 8/16-Bit Timer/Counter Operation"

7.11 "Notes on Using the 8/16-Bit Timer/Counter"

7.12 "8/16-Bit Timer/Counter Program Examples"

147


7.1 Overview of the 8/16-Bit Timer/Counter

The 8/16-bit timer/counter consists of two 8-bit counters (timer 1 and timer 2). The counters can be used separately (8-bit mode) or together (16-bit mode).Timer 1 has an interval timer function which can count up, synchronizing with three different internal count clocks and a counter function which counts up on a clock input from an external pin. The output of timer 1 can be used to output a square wave with a specified frequency.Timer 2 only has an interval timer function using the three internal count clocks and can output square waves with a specified frequency. In 16-bit mode, timer 2 is linked serially to timer 1.

Interval timer function

The interval timer function generates periodic interrupt requests at any time interval.

The function can also invert the output level of a pin (TO pin) at each time interval to output asquare wave of any frequency (in 8-bit mode for timer or in 16-bit mode).

• In 8-bit mode, timer 1 and timer 2 operate as independent timers. Each timer can operate asan interval timer with a period equal to the count clock to 28 times longer than the countclock period.

• In 16-bit mode, the timers are linked to operate as a 16-bit timer, with timer 1 used for thelower byte and timer 2, for the upper byte. The 16-bit timer can operate as an interval timerwith a period equal to the count clock to 216 times longer than the count clock period.

• The count clock can be selected from three different internal count clocks (timer 1 operatesas a count function when the external clock is selected).

Table 7.1-1 "Timer 1 interval time and square wave output range in 8-bit mode" to Table 7.1-3"Interval time and square wave output range in 16-bit mode" list the interval time and squarewave output range for each operating mode.

Table 7.1-1 Timer 1 interval time and square wave output range in 8-bit mode

Count clock period Interval time Square wave output range (Hz)

Internal count clock 2tint 2tinst to 29tinst 1/(22tinst) to 1/(210tinst)

32tint 25tinst to 213tinst 1/(26tinst) to 1/(214tinst)


External clock 1text 1text to 28text 1/(2text) to 1/(29text)

148

7.1 Overview of the 8/16-Bit Timer/Counter

Note:

[Example calculation of interval time and square wave frequency]

The following formula calculates the timer 1 interval time and the frequency of the squarewave output from the TO pin when timer 1 is operated continuously without changing thetimer 1 data register (T1DR) value. The conditions for the example are a 3.58 MHz mainclock source oscillation (FCH), timer 1 data register (T1DR) value of "DDH (221)", 2 tinstselected as the count clock period, and 8-bit mode operation.

Note that the calculation is for main clock mode (SCS = 1) with the maximum clock speed(CS1, CS0 = 11B, one instruction cycle = 4/FCH) selected in the system clock control register(SYCC).

Table 7.1-2 Timer 2 interval time in 8-bit mode

Count clock period Interval time

Internal count clock 2tint 2tinst to 29tinst

32tint 25tinst to 213tinst

512tint 29tinst to 217tinst

Table 7.1-3 Interval time and square wave output range in 16-bit mode

Count clock period Interval time Square wave output range (Hz)

Internal count clock 2tint 2tinst to 217tinst 1/(22tinst) to 1/(218tinst)



External clock 1text 1text to 216text 1/(2text) to 1/(217text)

tinst: Instruction cycle (depending on clock mode, etc.)text: External clock period (1 text greater than or equal to 2 tinst)

(MB89170 series)

Interval time = (2x4/FCH)xT1DR register+1)= (8/3.58MHz)x(221+1) 496.1 s

Output frequency = FCH/(2x8x(T1DR register+1))= 3.58MHz/(16x(221+1)) 1.01kHz

Output frequency = FCH/(2x8x(T1DR register+1))= 7.16MHz/(16x(221+1)) 1.02kHz

(MB89170A/170L series)

Interval time = (2x4/FCH)xT1DR register+1)= (8/7.16MHz)x(221+1) 248.0 s

149


Counter function

The counter function counts the number of trailing edges on the external clock input from theexternal pin (EC pin). As the external clock can be selected only for timer 1, the counterfunction can operate only on timer 1 in 8-bit mode or in 16-bit mode.

• The counter counts up on the external clock. When the count becomes equal to the setlevel, the counter generates an interrupt request and also inverts the TO pin output level.

• The count can count up to 28 on timer 1 in 8-bit mode.

• The count can count up to 216 in 16-bit mode.

• The count function can be used in the same manner as the interval timer function byinputting an external clock with a fixed period.

150

7.2 Structure of the 8/16-Bit Timer/Counter

7.2 Structure of the 8/16-Bit Timer/Counter

The 8/16-bit timer/counter consists of the following five blocks:• Count clock selectors 1 and 2• Counter circuits 1 and 2• Square wave output control circuit• Timer data registers (T1DR and T2DR)• Timer control registers (T1CR1 and T2CR)

Block diagram of 8/16-bit timer/counter

Figure 7.2-1 Block diagram of 8/16-bit timer/counter

Inte

rnal

dat

a bu

s

T1STR T1CS0 T1CS1 T1OS0 T1OS1 T1IE T1IFTimer control register (T1CR)

T1STP

Pin control/output initialization

Square wave output control circuit 1

Pin

8-bit counter

Comparator

Timer data register (T1DR)

x 2x 32x 512

1tinst

Count clock selector 1

Interrupt request IRQ3

Output enable signal

P34/TO/INT0

Timer data register (T2DR)

Comparator

8-bit counterx 2x 32x 512

Count clock selector 2

T2STR T2CS0 T2CS1 T2OS0 T2OS1 T2IE T2IFTimer control register

(T2CR) T2STP

Counter circuit 1

Counter circuit 2

T1DR and T2DR write

T2DR read

1tinst

R, SQ

T.FF

2

2

T1DR read

tinst: Instruction cycle

Pin

P33/EC

2

LOAD Compare data latch

EQ

LOAD Compare data latch

EQ

CLR

CK

CK

CLRCO

CK

TO1

151


Count clock selectors 1 and 2

These circuits respectively select the input clock. Three internal clocks and one external clockcan be selected for 16-bit mode or for timer 1 in 8-bit mode. Only the three internal clocks canbe selected for timer 2 in 8-bit mode.

Counter circuits 1 and 2

Counter circuits 1 and 2 respectively consist of an 8-bit counter, comparator, compare datalatch, and data registers (T1DR and T2DR).

The 8-bit counter counts up on the selected count clock. The comparator compares the countervalue with the value in the compare data latch. When the values match, the counter is clearedand the value in the data register is loaded into the compare data latch.

In 8-bit mode, counter circuits 1 and 2 operate independently as timer 1 and timer 2. In 16-bitmode, counter circuit 1 that provides the lower eight bits and counter circuit 2 that provides theupper eight bits operate as the linked 16-bit counter.

Square wave output control circuit

An interrupt request is generated when the comparator detects a match in 16-bit mode or in 8-bit mode on timer 1. If square wave output is enabled at this time, the output control circuitinverts the output of the TO pin.

The square wave output can also be initialized to the "L" level or "H" level.

Timer data register (T1DR and T2DR)

Writing these registers sets the data to be compared with each 8-bit counter value. Reading theregisters reads the current counter values.

Timer control registers (T1CR and T2CR)

These registers are used to select the function, enable and disable operation, control interrupts,and check the state.

8/16-bit timer/counter interrupt

IRQ3:

For the interval timer function or counter function, an IRQ3 interrupt request is generatedwhen the counter value becomes equal to the value in the data register if output of interruptrequests is enabled (T1CR:T1IE = 1 (in 16-bit mode or 8-bit mode on timer 1) or T2CR:T2IE= 1 (in 8-bit mode on timer 2)).

152

7.3 8/16-Bit Timer/Counter Pins

7.3 8/16-Bit Timer/Counter Pins

The 8/16-bit timer/counter pins, their block diagram, registers, and interrupts are described.

8/16-bit timer/counter pins

The 8/16-bit timer/counter pins are P33/EC and P34/TO/INTO.

P33/EC pin

The P33/EC pin can function as either a general-purpose I/O port (P33) or as the externalclock input pin for the timer (EC).

EC:

If the external clock input (counter function) is selected (T1CR1:T1CS1, T1CS0 = 11B) fortimer 1 in 8-bit mode or for 16-bit mode, the timer counts the clock input from this pin. Whenusing the P33/EC pin as the EC pin, set the pin as an input port in the port data directionregister (DDR3:bit 3 = 0).

P34/TO/INTO pin

The P34/TO/INTO pin can function as either a general-purpose I/O port (P34) or as the squarewave output pin for the timer (TO).

TO:

The square wave is output from this pin for timer 1 in 8-bit mode or for 16-bit mode. Ifsquare wave output is enabled (T1CR:T1OS1, T1OS0 = other than 00B), the P34/TO/INTOpin automatically becomes an output pin and functions as the TO pin, regardless of the valueof the port data direction register (DDR3:bit 4).

153


Block diagram of 8/16-bit timer/counter pins

Figure 7.3-1 Block diagram of 8/16-bit timer/counter pins

Note

Pins with a pull-up resistor selected as an option setting enter the "H" level during a reset,stop mode, or watch mode (SPL = 1).

Pin

Pch

Nch

Pull-up resistor (option) of 50 k approx. (at 5 V)

Pch

PDR read

PDR read (bit manipulation instructions)

PDR write

DDR write

P33/ECP34/TO/INT0

DDR read

Output latch


From timer output

From output enable


DDR

Inte

rnal

dat

a bu

s



SPL: Pin state setting bit in the standby control register (STBC)

To external clock input [EC pin only]

To external interrupt circuit

External interrupt input enable

P34 to P36 only

154

7.4 8/16-Bit Timer/Counter Registers


This section describes the 8/16-bit timer/counter registers.

8/16-bit timer/counter registers

Figure 7.4-1 8/16-bit timer/counter registers


Timer 1 control register (T1CR)

T1OS0 T1CS1 T1STP T1STRT1CS0T1IET1IF T1OS1Address0019H

Initial valueX000XXX0B



T2OS0 T2CS1 T2STP T2STRT2CS0T2IET2IF T2OS1Address0018H

Initial valueX000XXX0B


Timer 1 data register (T1DR)

Address001BH

Initial valueXXXXXXXXB



Address001AH

Initial valueXXXXXXXXB

R/W: Readable and writable X : Undefined

R/W R/W R/W R/W R/W R/W R/W R/W




155


7.4.1 Timer 1 control register (T1CR)

The T1CR is used to select the function, enable and disable operation, control interrupts, and check the state in 16-bit mode or in 8-bit mode on timer 1. Initializing the timer 2 control register (T2CR) is still required even when only timer 1 is used in 8-bit mode.


Figure 7.4-2 Timer 1 control register (T1CR)

R/W


0 0 1 9H

Address

X000XXX0B

Initial value

T1IF T1IE

R/WR/W R/W

T1STP01

Timer stop bitContinues operation without clearing counterTemporarily halts counter operation

T1CS10011

T1CS00101

Count clock selection bits2tinst32tinst512tinstExternal clock

R/W

T1STR01

Timer start bitHalts counter operationClears counter and start operation

R/W: Readable and writable

TIIF

This bit is cleared

Write Interrupt request flag bit

Read

No counter match0

1 Counter match occurred

R/WR/WR/W

Interrupt request enable bitDisables output of interrupt requestsEnables output of interrupt requests

T1OS10011

T1OS00101

Square wave output control bitUsed as a general-purpose port (P34)Sets data to set square wave output to "L"Sets data to set square wave output to "H"Outputs the level corresponding to the set data to the square wave output pin (TO)(*1)

T1IE01

T1OS0 T1CS1 T1STP T1STRT1CS0T1OS1



* : *1 The square wave output pin enters the level corresponding to the data set when T1STR was "0".: Initial value

X : Undefined

156


Caution:

When using only timer 1 of the 8/16-bit timer/counter in 8-bit mode, set the timer count clockselection bits in the timer 2 control register (T2CR:T2CS1, T2CS0) to other than "11B" beforeusing timer 1. Using the timer without setting the register causes malfunction.

See Section 7.8 "Operation of the Square Wave Output Initialization Function" for information onhow to use the square wave output control bits.

Table 7.4-1 Function of each timer 1 control register (T1CR) bit

Bit Description

bit7 T1IF: Interrupt request flag bit

• In 8-bit mode : This bit is set to "1" when the timer 1 counter value matches the value (compare data latch) set in the timer 1 data register (T1DR).

• In 16-bit mode : This bit is set to "1" when the timer 1 and timer 2 counter values match the values set in the T1DR and T2DR respectively.

• An interrupt request is output when this bit and the interrupt request enable bit (T1IE) are "1".

• Writing "0" clears the bit. Writing "1" has no effect and does not change the bit.

bit6 T1IE: Interrupt request enable bit

• This bit enables or disables output of interrupt requests to the CPU.• An interrupt request is output when this bit and the interrupt request

flag bit (T1IF) are "1".

bit5bit4

T1OS1, T1OS0:Square wave output control bits

• The P34/TO/INTO pin becomes a general-purpose port (P34) when these bits are "00B". For other settings, the P34/TO/INTO pin becomes the square wave output pin (TO).

• Writing "01B" or "10B" sets the initial value in the square wave output control circuit and the TO pin enters the output status. The pin level is undefined.

• When these bits are "11B" and the timer is halted (T1STR = 0), the TO pin is set to the level corresponding to the initialization data.

bit3bit2

T1CS1, T1CS0:Clock source selection bits

• These bits select the count clock supplied to the counter.• The clock can be selected from three internal clocks and an external

clock.• he external clock is selected when these bits are "11B" and the timer

operates as the counter function.Caution:

The P33/EC pin must be set as an input port when the external clock is selected (T1CS1, T1CS0 = 11B).

bit1 T1STP:Timer stop bit

• This bit is used to temporarily halt the counter.• Writing "1" to this bit temporarily halts the counter. Writing "0" to this

bit while the timer is active (T1STR = 1) causes the counter to continue operation.

bit0 T1STR:Timer start bit

• This bit starts and stops the counter.• Changing the value of this bit from "0" to "1" clears the counter. At

this time, if the timer is in the operation continuation state (T1STP = 0), the counter starts operation and begins to count up on the selected count clock. Writing "0" halts the counter operation.

• Starting the timer (T1STP = 0 -->1) in 16-bit mode clears the counters of both timer 1 and timer 2.

157


7.4.2 Timer 2 control register (T2CR)

The timer 2 control register (T2CR) is used to select the function, enable and disable operation, control interrupts, and check the state of timer 2 in 8-bit mode. The T1CR controls the timers in 16-bit mode. However, setting the T2CR register is still required in 16-bit mode.


Figure 7.4-3 Timer 2 control register (T2CR)

R/W


0 0 1 8H

Address

X000XXX0B


Initial value

T2IF T2IE T2OS0 T2CS0 T2STP T2STR

R/W

T2OS1

R/W R/W

T2STP01

Timer stop bitContinues operation without clearing counterTemporarily halts counter operation

T2CS1

T2CS10011

T2CS00101

Count clock selection bits2tinst32tinst512tinst16-bit mode

R/W

T2STR01

Timer start bitHalts counter operationClears counter and starts operation

R/W : Readable and writable X : Undefined : Initial value

T2IF

Clears this bit


WriteInterrupt request flag bit

Read

No counter match0

1 Counter match occurred

R/WR/WR/W

Interrupt request enable bitDisables output of interrupt requestsEnables output of interrupt requests

T2OS10011

T2OS00101

Square wave output control bitAlways set to "00"Setting prohibitedSetting prohibitedSetting prohibited

T2IE01

158


Caution:

For use in 16-bit mode, set the T2CS1 and T2CS0 bits to "11B" before controlling operationusing the T1CR register.

Table 7.4-2 Function of each timer 2 control register (T2CR) bit

Bit Description

bit7 T1IF: Interrupt request flag bit

• This bit is set to "1" when the timer 2 counter value matches the value (compare data latch) set in the timer 2 data register (T2DR).

• An interrupt request is output when this bit and the interrupt request enable bit (T2IE) are "1".

• Writing "0" clears the bit. Writing "1" has no effect and does not change the bit.

Caution:The T1IF bit is used in 16-bit mode. In this case, the T2IF bit has no relation to the operation.

bit6 T1IE: Interrupt request enable bit

• This bit enables or disables output of interrupt requests to the CPU.• An interrupt request is output when this bit and the interrupt request

flag bit (T2IF) are "1".Caution:

The T1IE bit is used in 16-bit mode. In this case, the T2IE bit has no relation to the operation.

bit5bit4

T1OS1, T1OS0:Square wave output control bits

These bits are not used for timer 2. Always set to "00".

bit3bit2

T1CS1, T1CS0:Clock source selection bits

• These bits select the count clock supplied to the counter.• The clock can be selected from three internal clocks.• Writing "11B" to these bits selects 16-bit mode.Caution:

The P33/EC pin must be set as an input port when the external clock is selected (T1CS1, T1CS0 = 11B).

bit1 T2STP:Timer stop bit

• This bit is used to temporarily halt the counter.• Writing "1" to this bit temporarily halts the counter. Writing "0" to this

bit while the timer is active (T2STR = 1) causes the counter to continue operation.

CautionThe T1STP bit is used in 16-bit mode. In this case, the T2STP bit has no relation to the operation.

bit0 T2STR:Timer start bit

• This bit starts and stops the counter.• Changing the value of this bit from "0" to "1" clears the counter. At

this time, if the timer is in the operation continuation state (T2STP = 0), the counter starts operation and begins to count up on the selected count clock. Writing "0" halts the counter operation.

Caution:The T1STR bit is used in 16-bit mode. The T2STR bit has no relation to the operation.

159


7.4.3 Timer 1 data register(T1DR)

The timer 1 data register (T1DR) is used to read the counter value and to set the interval timer value (for the interval timer function) or counter value (for the counter function). The register sets the interval timer value for timer 1 in 8-bit mode and sets the lower eight bits of the interval timer value in 16-bit mode.


The value set in this register is compared with the counter value. Reading this register readsthe current counter value. The value set in the register cannot be read.

Figure 7.4-4 "Timer 1 data register (T1DR)" shows the bit structure of the timer 1 data register.

Figure 7.4-4 Timer 1 data register (T1DR)

8-bit mode (timer 1)

The value set in this register is compared with the timer 1 counter value. The register value setsthe interval time for the interval timer function and the number of counts to be detected for thecounter function. Enabling the count operation (T1CR:T1STR = 0 --> 1, T1STP = 0) loads thecontents of the T1DR to the compare data latch and causes the counter to start counting up.

The counter counts up until the counter value matches the value in the compare data latch.When a match occurs, the T1DR value is reloaded into the compare data latch, the counter iscleared, and counting continues.

As the compare data latch is re-set when a match is detected, a value written to the T1DRregister during the counter operation is used from the next cycle (after a match is detected).

Note:

Use the following formula to calculate the setting value of the T1DR during the interval timeroperation. Note that the clock mode and gear function affect the instruction cycle.

16-bit mode

The value set in this register is compared with the lower eight bits of the counter value of the 16-bit timer.

The register value sets the lower eight bits of the interval time for the interval timer function andthe lower eight bits of the number of counts to be detected for the counter function. The T1DRvalue is loaded into the lower eight bits of the compare data latch when count operation startsand when a match is detected for the 16-bit counter. If a value is written to the T1DR during the16-bit counter operation, the value is used after the next match is detected.

R/W: Readable and writableR/WR/W R/W R/WR/W R/W R/W R/W


0 0 1 BH

Address

XXXXXXXXB

Initial value

X: Undefined

T1DR value = interval time/(count clock period x instruction cycle) -1

160


See Section 7.4.4 "Timer 2 data register (T2DR)" for the values of the T1DR set when theinterval timer function is selected.

161


7.4.4 Timer 2 data register (T2DR)

The timer 2 data register (T2DR) is used to read the counter value and to set the interval timer value (for the interval timer function) or counter value (for the counter function). The register sets the interval timer value for timer 2 in 8-bit mode and sets the upper eight bits of the interval timer value in 16-bit mode.


The value set in this register is compared with the counter value. Reading this register readsthe current counter value. The value set in the register cannot be read.

Figure 7.4-5 "Timer 2 data register (T2DR)" shows the bit structure of the timer 2 data register.

Figure 7.4-5 Timer 2 data register (T2DR)

8-bit mode (timer 2)

The value set in this register is compared with the timer 2 counter value. The register value setsthe interval time for the interval timer function and the number of counts to be detected for thecounter function. The T2DR value is loaded into the compare data latch when count operationstarts and when a match with the counter value is detected.

If a value is written to the T2DR during counter operation, the value is used from the next cycle(after a match is detected).

Note:

Use the following formula to calculate the setting value of the T2DR during interval timeroperation. Note that the instruction cycle depends on the clock mode and gear function.

16-bit mode

The value set in this register is compared with the upper eight bits of the counter value of the16-bit timer.

The register value sets the upper eight bits of the interval time for the interval timer function andthe upper eight bits of the number of counts to be detected for the counter function. The T2DRvalue is loaded into the upper eight bits of the compare data latch when count operation startsand when a match is detected for the 16-bit counter. If a value is written to the T2DR during 16-bit counter operation, the value is used after the next match is detected. The timer 1 controlregister (T1CR) is used to control count operation in 16-bit mode.

R/WR/W R/W R/WR/W R/W R/W R/W


0 0 1 AH

Address

XXXXXXXXB

Initial value


T2DR value = interval time/(count clock period x instruction cycle) -1

162


Note:

Use the following formula to calculate the setting values for the T1DR and T2DR for theinterval timer function. Note that the instruction cycle depends on the clock mode and gearfunction.

The upper eight bits and lower eight bits of the 16-bit data value are set in the T2DR and theT1DR, respectively.

16-bit data value = interval time/(count clock period x instruction cycle) -1

163


7.5 8/16-Bit Timer/Counter Interrupts

Both the interval timer function and counter function of the 8/16-bit timer/counter can generate an interrupt request when a match occurs between the data register and count values.

8/16-bit timer/counter interrupts

Table 7.5-1 "Interrupt control bits and conditions for the 8/16-bit timer/counter" lists the interruptrequest flag bits, interrupt request output enable bits, and interrupt generation conditions for the8/16-bit timer/counter.

In 8-bit mode, timer 1 and timer 2 generate interrupt requests of the 8/16-bit timer/counterindependently. In 16-bit mode, timer 1 generates interrupt requests. However, the basicoperation is the same. The following describes the timer 1 interrupt operation in 8-bit mode.

Timer 1 interrupt operation in 8-bit mode

The counter counts up from "00H" on the selected count clock. When a match occurs with thevalue set in the compare data latch of the timer data register (T1DR), the interrupt request flagbit (T1CR:T1IF) is set to "1".

In this case if the interrupt request enable bit is enabled (T1CR:T1IE = 1), an interrupt request(IRQ3) is output to the CPU. Write "0" to the T1IF bit in the interrupt processing routine to clearthe interrupt request.

The T1IF bit is set to "1" when the counter value matches set value, regardless of the T1IE bitvalue.

In 8-bit mode, timer 1 and timer 2 operate independently but both generate the same interruptrequest (IRQ3). Therefore, you may need to check the interrupt request flag bits via software.

Note

• When a match occurs between the counter value and T1DR1 register value at the same timethat the counter is halted (T1CR:T1STR = 0), the T1IF bit is not set.

• An interrupt request is generated immediately if the T1IE bit is switched from disabled toenabled (0 --> 1) while the T1IF bit is "1".

Table 7.5-1 Interrupt control bits and conditions for the 8/16-bit timer/counter

8-bit mode 16-bit mode

Timer 1 Timer 2 Timer 1 + timer 2

Interrupt request flag bit T1CR:T1IF T2CR:T2FI T1CR:T1IF

Interrupt request enable bit T1CR:T1IF T2CR:T2IF T1CR:T1IF

Interrupt conditions The value set in T1DR matches the 8-bit counter value

The value set in T2DR matches the 8-bit counter value

The value set in T1DR and T2DR matches the 16-bit counter value

164

7.5 8/16-Bit Timer/Counter Interrupts

Register and vector table for 8/16-bit timer/counter interrupts

See Section 3.4.2 "Processing during an interrupt" for interrupt operation.

Table 7.5-2 Register and vector table for 8/16-bit timer/counter interrupts


Register Setting bit Upper Lower

IRQ3 ILR1 (007CH) L31 (bit7) L30 (bit6) FFF4H FFF5H

165


7.6 Operation of the Interval Timer Function

This section describes the operation of the interval timer function of the 8/16-bit timer/counter.

Operation of the interval timer function

8-bit mode

Figure 7.6-1 "Interval timer function (timer 1 and timer 3) settings" shows the settings requiredfor operating the interval timer function of timer 1 in 8-bit mode.

Figure 7.6-1 Interval timer function (timer 1 and timer 3) settings

Figure 7.6-2 "Interval timer function (timer 2) setting" shows the settings required for operatingthe interval timer function of timer 2 in 8-bit mode.

Figure 7.6-2 Interval timer function (timer 2) setting

Activating the counter in 8-bit mode starts counting up from "00H" on the leading edge of theselected clock. When the counter value becomes equal to the value set in the data register(compare data latch), the interrupt request flag bit in the timer control register (T1CR:T1IF orT2IF) is set to "1" and the counter starts again from "00H". When timer 1 is used, the output ofthe square wave output control circuit is inverted upon detection of a match. If square waveoutput is enabled (T1CR:T1OS1, T1OS0 = other than 00B), a square wave is output from theTO pin.

Figure 7.6-3 "Operation of the interval timer function in 8-bit mode (timer 1)" shows theoperation of the interval timer function in 8-bit mode.


T1CR

: Used bit : Unused bit 0 : Set 0

T1DR Set interval time (comparison value)

T1OS0 T1CS1 T1STP T1STRT1CS0T1IET1IF T1OS1

Other than 11

T2CR T2OS0 T2CS1 T2STP T2STRT2CS0T2IET2IF T2OS1

Other than 11


T2CR

: Used bit 0 : Set 0

T2DR Set interval time (comparison value)

T2OS0 T2CS1 T2STP T2STRT2CS0T2IET2IF T2OS1

Other than 1100

166

7.6 Operation of the Interval Timer Function

Figure 7.6-3 Operation of the interval timer function in 8-bit mode (timer 1)

16-bit mode

Figure 7.6-4 "Interval timer function (16-bit mode) settings" shows the settings required foroperating the interval timer function in 16-bit mode.

Figure 7.6-4 Interval timer function (16-bit mode) settings

Timer control is performed with the timer 1 control register (T1CR) in 16-bit mode. In this case,however, initial settings of the timer 2 control register (T2CR) are required. The value set in thedata registers is compared with the 16-bit counter value. The T2DR holds the upper eight bitsand the T1DR holds the lower eight bits. Clearing the counter clears all 16 bits at once. Otheroperations in 16-bit mode are the same as timer 1 operations in 8-bit mode.

80H

Time

Comparison value (E0H) Comparison value (FFH)Counter value

T1DR value (E0H)

T1IF bit

TO pin

Counter clear(*2)

T1STR bit(T1STP=0)

Cleared by the program

Match Match MatchStart

*1 If the data register value is changed during counter operation, the new value is used from the next cycle.*2 The counter is cleared and the value set in the data register is loaded to the compare data latch when the counter is started and when a match is detected.

E0H

FFH

00H

T1DR value changed (EOH FFH)(*1)

T2CR

: Used bit : Unused bit1 : Set 10 : Set 0

T1DR

T2DR

Set lower eight bits of interval time

Set upper eight bits of interval time


T1CR T1IET1IF

T2IET2IF

0 0 11

Other than 11



167


7.7 Operation of the Counter Function

This section describes the operation of the counter function of the 8/16-bit timer/counter.

Operation of the counter function

8-bit mode

Figure 7.7-1 "Counter function (8-bit mode) settings" shows the settings required for operatingthe counter function of timer 1 in 8-bit mode.

Figure 7.7-1 Counter function (8-bit mode) settings

The operation of the counter function in 8-bit mode is the same as the interval timer function (fortimer 1 in 8-bit mode) except that the external clock is used instead of an internal clock.

16-bit mode

Figure 7.7-2 "Counter function (16-bit mode) settings" shows the settings required for operatingthe counter function in 16-bit mode.


T1CR

T1DR

: Used bit : Unused bit 0 : Set 0

Set counter value to be compared

T1IET1IF

DDR3

0

T2CR T2IET2IF

Other than 11

1 1



168

7.7 Operation of the Counter Function

Figure 7.7-2 Counter function (16-bit mode) settings

The operation of the counter function in 16-bit mode is the same as the interval timer function (in16-bit mode) except that the external clock is used instead of an internal clock.

Figure 7.7-3 "Operation of the counter function in 16-bit mode" shows the operation of thecounter function in 16-bit mode.

T2CR

T1DR

T2DR

Set lower eight bits of counter value to be compared

Set upper eight bits of counter value to be compared

T1CR T1IET1IF

T2IET2IF

0 0 1

: Used bit: Unused bit: Set 1: Set 00

1

1


DDR3

0

1 1



169


Figure 7.7-3 Operation of the counter function in 16-bit mode

Caution:

When reading the counter value in 16-bit mode while the counter is operating, always readthe value twice to verify that a valid value has been read.


T1IF register

External clock

Counter clear

T1STR bit(T1STP=0)

Counter value 0000H 0001H 0002H 0003H 1388H 0000H 0001H

T1DR(*1) (lower eight bits of setting value)

34H88H

T2DR(*1) (upper eight bits of setting value)

12H13H

*1 A value can be set at any timing. The value set in the data register is loaded to the compare data latch when the counter starts or when a match occurs. When this occurs, the counter is cleared.

Data setting (1234H)

Compare data latch 1 (lower eight bits of compared value)

34H88H

Compare data latch 2 (upper eight bits of compared value)

12H13H

LoadLoad

170

7.8 Operation of the Square Wave Output Initialization Function

7.8 Operation of the Square Wave Output Initialization Function

A required initial value of the square wave output can be set with the timer 1 control register (T1CR).

Operation of the square wave output initialization function

When the timer is halted (T1CR:STR1 = 0), any value can be set for the initial value of thesquare wave output by using the program.

Figure 7.8-1 "Equivalent circuit for initializing square wave output" shows the equivalent circuitfor initializing the square wave output control circuit. Table 7.8-1 "Procedure for setting initialvalue of square wave output (T1CR register)" shows the procedure for setting the initial value.Figure 7.8-2 "Initial setting of square wave output" shows the operation for square wave outputfor this case.

Figure 7.8-1 Equivalent circuit for initializing square wave output

Figure 7.8-2 "Initial setting of square wave output" shows the operation for square wave outputinitial setting.

Table 7.8-1 Procedure for setting initial value of square wave output (T1CR register)

Step Setting and operation

(1) To set the square wave output pin (TO) to the "L" level, write "01B" to the square wave output control bits (T1CR:T1OS1, T1OS0). Similarly, write "10B" to set the pin to the "H" level.Caution:

Until "11B" is written, the value is only stored in the level latch, and the TO pin becomes the output state and an undefined signal is output.

(2) Writing "11B" to the square wave output control bits (T1OS1, T1OS0) outputs the level corresponding to the level latch value (initial value) to the TO pin. Do not perform initial setting of the pin (T1OS1, T1OS0 = 11) and counter starting (T1STR = 0 [***] 1) at the same time.Setting the timer start bit (T1STR = 1) starts counter operation.

(3) The square wave output is inverted each time a match occurs between the counter value and the value set in the data register.

D

S Q

R CKQ

D Q

Q

D Q

T1STR

T1OS1

T1OS0

Level latch

QQ

D Q

Q

Write strobe signal

Output enable signal

Set the output pin to the "H" level (the output F/F is set)

Set the output pin to the "L" level (the output F/F is cleared)

Counter overflow signal

P34/TO/INTO pin

Output F/F

Level latch

171


Figure 7.8-2 Initial setting of square wave output

Set value (initial value)

Pin stateP34/TO/INT0

Square wave output Undefined

(1) (2) (3)

Port(*1) Timer(*2)

*1 The P34/TO/INTO pin becomes a general-purpose port (P34) when the T1OS1 and T1OS0 bits of the T1CR are "00B".*2 The P34/TO/INTO pin becomes the square wave output pin (TO) when either the T1OS1 or T1OS0 bit is set to "1".

172

7.9 Halting and Restarting the 8/16-Bit Timer/Counter

7.9 Halting and Restarting the 8/16-Bit Timer/Counter

This section describes the operation of halting and restarting the 8/16-bit timer/counter.

Halting and restarting the timer

The following describes the operation of timer 1. For the operation of timer 2, follow the sameprocedure.

The timer stop bit (T1STP) and timer start bit (T1STR) of the timer 1 control register (T1CR) areused to halt and restart timer 1.

To start the count operation after clearing the counter

Set "01B" to the T1STP and T1STR bits when the T1STR bit is "0". The timer is cleared on theleading edge of the T1STR bit and count operation starts.

To temporarily halt the timer, then restart the count operation without clearing the counter

Set "11B" to the T1STP and T1STR bits to temporarily halt the count operation. Then, to restartthe count operation from the temporarily halted state without clearing the counter, set "01B" tothe T1STP and T1STR bits.

Table 7.9-1 "Halting and restarting the timer" lists the state of the timer for each T1STP andT1STR bit setting and the operation of the timer started (T1STP, T1STR = 01B) from that state.

Table 7.9-1 Halting and restarting the timer

T1STP(T2STP)

T1STR(T2STR)

Timer stateTimer operation for starting (T1STP, T1STR = 01B)

from the state indicated on the left

0 0 Count operation halted Starts count operation after clearing the counter.

0 1Count operation in progress

Continues count operation.

1 0 Count operation halted Starts count operation after clearing the counter.

1 1Count operation temporarily halted

Restarts count operation without clearing the counter.

173


7.10 State in Each Mode of 8/16-Bit Timer/Counter Operation

This section describes the operation performed when the device enters sleep or stop mode or a halt request occurs during operation of the 8/16-bit timer/counter.

Operation during sub-clock or standby mode, or for a halt during operation

Figure 7.10-1 "Counter operation during sub-clock mode or standby mode, or for a temporaryhalt" shows what happens to the counter value if the device enters sleep or stop mode or a haltrequest occurs during operation of the interval timer function or counter function (for timer 1operation).

Switching to stop mode halts the counter and maintains the counter value. If the device wakesup from stop mode via an external interrupt, the counter restarts operation from the existingcounter value. Consequently, the first interval time or the number counts of the external clockwill be incorrect. Always re-initialize the 8/16-bit timer/counter after waking up from stop mode.

The operation for changing to (STBC:TMD = 1), and waking up from watch mode is the same asthat for stop mode. The device can wake-up from watch mode via the watch interrupt or anexternal interrupt.

Temporary halting of the counter (T1STP = 1) halts the counter and maintains the countervalue. If operation is then continued (T1STP = 0), the count operation restarts.

Figure 7.10-1 Counter operation during sub-clock mode or standby mode, or for a temporary halt

Time

Counter value

0000H

Match Match Match

Counter clearMatch Match

T1STR bit

T1IF bit (T1IE bit)

TO pin

SLP bit (STBC register)

STP bit (STBC register)

(*1)

Sleep

Wakeup from sleep mode by IRQ3 Stop

External interrupt

T1STP bit

Temporary halt


Data register setting value

Start

*1 If the pin state setting bit of the standby control register (STBC:SPL) is "1" and the pull-up option is not selected for the TO pin, the TO pin enters high impedance during stop mode. If the SPL bit is "0", the pin maintains its value that was set immediately before the device entered stop mode.

174

7.11 Notes on Using the 8/16-Bit Timer/Counter

7.11 Notes on Using the 8/16-Bit Timer/Counter

This section describes notes on using the 8/16-bit timer/counter.

Notes on using the 8/16-bit timer/counter

Notes on halting the timer

The following describes the operation for timer 1. For the operation for timer 2, follow the sameprocedure.

When the timer is temporarily halted by the T1STP bit, the count advances by one if the inputclock is at the "L" level. Similarly, the count may advance by one if the input clock is at the "L"level when "00B" is written simultaneously to the T1STP and T1STR bits after a temporary halt.If temporarily halting the timer, using the T1STP bit, read the counter value before setting theT1STP bit to "0".

Figure 7.11-1 Operation when the timer stop bit is used

Error

As the timing at which counting up on the selected clock starts is asynchronous to the programactivation timing of the 8/16-bit timer/counter, the time until the counter value matches the setdata may be shorter by up to one cycle of the count clock period. Figure 7.11-2 "Error beforestart of count operation" shows the error before the start of the count operation.

01H

01

02H

11 00

Temporary halt Halt

Input clock to timer (EC or internal clock)

01H 02H

01 11

Temporary halt Halt

Counter value

T1STP, T1STR bits (T1CR register)

When the input clock is at the "H" level When the input clock is at the "L" level

03H 04H

00

175


Figure 7.11-2 Error before start of count operation

Using one 8-bit channel

When using only timer 1 of the 8/16-bit timer/counter in 8-bit mode, you must first set a valueother than "11B" in the timer count clock selection bits of the timer 2 control register(T2CR:T2CS1, T2CS0). Using timer 1 without setting the timer 2 control register may causemisoperation.

Notes on setting the timers using the program

• When using the 8/16-bit timer/counter in 16-bit mode, set the count clock selection bits of thetimer 2 control register (T2CR:T2CS1, T2CS0) to "11B" and set the unused bits 4 and 5(T2CR:T2OS1, T2OS0) to "00B".

• When reading the counter value while the counter is operating in 16-bit mode, always readthe value twice to verify that the read value is valid.

• The output value of the square wave output does not change if the output is initialized whilethe timer is operating (T1CR:T1STR = 1). Initialization occurs when the timer is halted.

• The system cannot return from interrupt processing if the interrupt request flag bit(T1CR:T1IF, T2CR:T2IF) is "1" and the interrupt request enable bit is enabled (T1CR:T1IE =1, T2CR:T2IE = 1). Always clear the interrupt request flag bit.

• If the counter operation is halted by the timer start bit (T1CR:T1STR = 0, T2CR:T2STR = 0)at the same time that an interrupt occurs, the interrupt request flag bit (T1CR:T1IF,T2CR:T2IF) is not set.

Counter value

Count clock

2 30 1 4

Counter activated

1 cycle

Error Period of count 0

176

7.12 8/16-Bit Timer/Counter Program Examples


This section describes example programs using the 8/16-bit timer/counter.

Program example of the interval timer function


• Use only timer 1 in 8-bit mode to generate interval timer interrupts at 23.45-ms (MB89170series) or 11.73-ms (MB89170A series) intervals.

• Invert the square wave at each interval time and output the wave from the TO pin.

• Set the T1DR register as follows to generate an interval time of approximately 23.45 ms(MB89170 series) or 11.73 ms (MB89170A series) if the source oscillation (FCH) is 3.58 MHzand the main clock speed (gear) is set to the maximum speed (1 instruction cycle = 4/FCH).The count clock is the 512 tinst internal count clock.

T1DR register value=23.45ms MB89170 series 11.73ms MB89170A series / (512x4/3.58MHz)-1=40.0(28H)

177


Coding example

T2CR EQU 0018H ;Address of the timer 2 control registerT1CR EQU 0019B ;Address of the timer 1 control registerT2DR EQU 001AH ;Address of the timer 2 data registerT1DR EQU 001BH ;Address of the timer 1 data register

T1IF EUQ T1CR:7 ;Timer 1 interrupt request flag bit definitionILR EUQ 007CH ;Address of the interrupt level setting registerINT_V DSEG ABS ;[DATA SEGMENT] ORG FFF4H IRQ3 DW WARI ;Interrupt vector setting ENDs;---Main program----------------------------------------------- CSEG ;[CODE SEGMENT] ;Assume the stack pointer (SP), ;etc., to have been initialized. : CLRI ;Disable interrupts. MOV ILR1,#10111111B ;Set interrupt level 2. MOV T2CR,#00000010B ;Clear the timer 2 interrupt request flag, disable interrupt request output, set to other than 16-bit mode, and halt operation. MOV T1CR,#00011000B ;Clear the timer 1 interrupt request flag, set the square wave initial value "L", select 512 tinst, and halt operation. MOV T1DR,#28H ;Set a value (interval time) to be compared with the counter value. MOV T1CR,#00111000B ;Output the "L" level from the square wave output pin (TO). MOV T1CR,#11111001B ;Enable output of timer 1 interruptrequests, clear the counter, and start the timer. SET1 ;Enable interrupts in CPU. : ;-------Interrupt program-------------------------------------------WARI CLRB T1IF ;Clear the interrupt request flag. PUSHW A XCHW A,T PUSHW A : User processing : POPW A XCHW A,T POPW A RETI ENDS ;------------------------------------------------------------------- END

178


Program example for the counter function


• Use timer 1 and timer 2 in 16-bit mode to generate an interrupt each time 5000 (1388H)pulses of the external clock input to the EC pin are counted.

• A sample program (READ16) is also shown for reading the 16-bit counter value while thecounter is operating.

Coding example

DDR3 EQU 000DH ;Address of the port data direction registerT2CR EQU 0018H ;Address of the timer 2 control registerT1CR EQU 0019H ;Address of the timer 1 control registerT2DR EQU 001AH ;Address of the timer 2 data register T1DR EQU 001BH ;Address of the timer 1 data register

T1IF EUQ T1CR:7 ;Timer 1 interrupt request flag bit definitionILR1 EUQ 007CH ;Address of the interrupt level setting registerINT_V DSEG ABS ;[DATA SEGMENT] ORG FFF4H INT_V DSEG ABS ;[DATA SEGMENT] ORG FFF4H IRQ3 DW WARI ;Interrupt vector setting ENDS;---Main program----------------------------------------------- CSEG ;[CODE SEGMENT] ;Assume the stack pointer (SP), ;etc., to have been initialized. : MOV DDR3,#00000000B ;Set the P33/EC pin as an input pin. CLR1 ;Disable interrupts. MOV ILR1,#10111111B ;Set interrupt level 2. MOV T1DR,#088H ;Set lower eight bits of the value to be compared with the counter value. MOV T2DR,#013H ;Set upper eight bits of the value to be compared with the counter value. MOV T2CR,#00001100B ;Set timer 2 to 16-bit mode. MOV T1CR,#11111001B ;Clear the timer 1 interrupt request flag, enable output of interrupt requests, set as a general-purpose port (P34), select an external clock, the counter, then start operation. SET1 ;Enable interrupts in CPU. ;------Data read subroutine--------------------------------------- :READ16 MOVW A,T2DR ;Read T1DR + T2DR in 16-bit mode. MOVW A,T2DR ;Read T1DR + T2DR in 16-bit mode, and save the old value in the T register. CMPW A ;Read twice to check, and

179


compare A and T. BEQ RET16 ;Return if they match. XCHW A,T INCW A ;Old value + 1 CMPW A BNE READ16 ;Read again if they are not equal. RET16 RET : ;------Interrupt program-----------------------------------------WARI CLRB T1IF ;Clear the interrupt request flag. PUSHW A XCHW A,T PUSHW A : User processing : POPW A XCHW A,T POPW A RETI ENDS ;------------------------------------------------------------------- END

180

CHAPTER 8 8-BIT SERIAL I/O

This chapter describes the functions and operation of the 8-bit serial I/O.

8.1 "Overview of the 8-Bit Serial I/O"

8.2 "Structure of the 8-Bit Serial I/O"

8.3 "8-Bit Serial I/O Pins"

8.4 "8-Bit Serial I/O Registers"

8.5 "8-Bit Serial I/O Interrupts"

8.6 "Serial Output Operation"

8.7 "Serial Input Operation"

8.8 "States in Each Mode of 8-Bit Serial I/O Operation"

8.9 "Notes on Using 8-Bit Serial I/O"

8.10 "8-Bit Serial I/O Connection Example"

8.11 "8-Bit Serial I/O Program Example"

181


8.1 Overview of the 8-Bit Serial I/O

The 8-bit serial I/O transfers 8-bit serial data synchronized by the shift clock. The shift clock can be selected from three internal clocks and an external clock. Either LSB-first or MSB-first can be selected as the data shift direction.

Serial I/O function

The 8-bit serial I/O transfers 8-bit serial data synchronized by the shift clock.

• Converts 8-bit parallel data to serial data and outputs. Converts serial data into parallel dataand stores it.

• The shift clock can be selected from three internal clocks and an external clock.

• Shift clock input and output can be controlled and the internal shift clock can be output.

• Either LSB-first or MSB-first can be selected as the data shift direction (transfer direction).

Table 8.1-1 Shift clock period and transfer speed

Shift clock Clock period Frequency (Hz)Transfer speed (FCH = 7.16

MHz, maximum clock speed(*1))

Internal shift clock (output)

2tinst 1/(2tinst) 896.7kbps



External shift clock (input) 2tinst or more 1/(2tinst) or less DC to 525 kbps

FCH: Main clock source oscillationtinst: Instruction cycle (depends on clock mode, etc.)*1 For the case of main clock mode (SCS = 1) with the maximum clock speed (CS1, CS0 = 11B, 1 instruction cycle = 4/FCH) selected in the system clock control register (SYCC).

182

8.2 Structure of the 8-Bit Serial I/O

8.2 Structure of the 8-Bit Serial I/O

Each channel of the 8-bit serial I/O consists of the following four blocks:• Shift clock control circuit• Shift clock counter• Serial data register (SDR)• Serial mode register (SMR)

Block diagram of 8-bit serial I/O

Figure 8.2-1 Block diagram of 8-bit serial I/O

Shift clock control circuit

The shift clock can be selected from three internal clocks and an external clock.

If an internal clock is selected, the shift clock can be output to the SCK pin. Selecting theexternal clock uses the clock input from the SCK pin as the shift clock. The SDR register shift

Internal data bus

(Shift direction)

Serial data register (SDR)

D0 to D7 MSB-first

D7 to D0LSB-first

D7 to D0

2

SST

BDS

CKS0

CKS1

SOE

SCKE

SIOE

SIOF

Serial mode register(SMR)

Shift clock control circuit

Shift clock counter

Transfer direction selection

P32/SI

P31/SO

P30/SCK

Output enable

Output enable

2tinst

Shift clock selection

Interrupt requestIRQ4


Ove

rflo

w

8tinst

32tinst

Clear

Pin

Pin

Pin

Output buffer

Output buffer

183


operation is driven by this shift clock and the shifted-out values are output from the SO pin.Similarly, the SI pin input is shifted into the SDR register.

Shift clock counter

This counter counts the number of SDR register shifts driven by the shift clock and overflowsafter the 8-bit shift is complete.

When the counter overflows, the serial I/O transfer start bit of the SMR register is cleared (SST= 0) and the interrupt request flag is set (SIOF = 1). Halting serial transfer (SST = 0) halts thecount on the shift clock counter and the counter is cleared by the next start (SST = 1).


This register stores the transfer data. The data written to this register is converted to serial dataand is output. At the same time, the serial data is converted to parallel data and stored.

Serial mode register (SMR)

This is the control register for the serial I/O. The register functions include enabling anddisabling serial I/O operation, selecting the shift clock, setting the transfer (shift) direction,controlling interrupts, and checking the status.

Serial I/O interrupt

IRQ4:

When the serial I/O function completes 8 bits of serial data I/O, an interrupt request (IRQ4) isgenerated if output of interrupt requests is enabled (SMR:SIOE = 1).

184

8.3 8-Bit Serial I/O Pins

8.3 8-Bit Serial I/O Pins

This section describes the 8-bit serial I/O pins and their block diagrams.

8-bit serial I/O pins

The 8-bit serial I/O pins are P32/SI, P31/SO, and P30/SCK.

P32/SI pin

The P32/SI pin can function either as a general-purpose I/O port (P32) or as the serial datainput pin (SI) (hysteresis input) for the serial I/O.

SI:

Set as an input port in the port data direction register (DDR3:bit 2 = 0).

P31/SO pin

The P31/SO pin can function either as a general-purpose I/O port (P31) or as the serial dataoutput pin (SO) (CMOS output) for the serial I/O.

Enabling serial data output (SMR:SOE = 1) automatically sets the P31/SO pin as an output pinregardless of the value of the port data direction register (DDR3:bit 1). This sets the pin tofunction as the SO pin.

P30/SCK pin

The P30/SCK pin can function either as a general-purpose I/O port (P30) or as the shift clock I/O pin (SCK) (hysteresis input, CMOS output) for the serial I/O.

• When used as the shift clock input pin:

• To use the SCK pin as an input, set as an input port in the port data direction register(DDR3:bit 0 = 0) and disable shift clock output (SMR:SCKE = 0). In this case, select theexternal shift clock (SMR:CKS1, CKS0 = 11B).

• When used as the shift clock output pin:

• Enabling shift clock output (SMR:SCKE = 1) automatically sets the P30/SCK pin as anoutput pin regardless of the value of the port data direction register (DDR3:bit 0) and setsthe pin to function as the SCK output pin. In this case, select an internal shift clock(SMR:CKS1, CKS0 = other than 11B).

185


Block diagram of 8-bit serial I/O pins

Figure 8.3-1 Block diagram of 8-bit serial I/O pins

Note:


Pin

Pch

Nch

Pch

PDR read


DDR read

PDR write

DDR write

Output latch

Stop or watch mode (SPL = 1)


DDR

Inte

rnal

dat

a bu

s



SPL: Pin state setting bit of the standby control register (STBC)

P32/SIP31/SOP30/SCK

From each output [SO and SCK pins only]

To each input (SI and SCK pins only)

From each output enable [SO and SCK pins only]

Pull-up resistor (option) 50 k approx. (at 5 V)

186

8.4 8-Bit Serial I/O Registers


This section describes the 8-bit serial I/O registers.

8-bit serial I/O registers

Figure 8.4-1 8-bit serial I/O registers

SIOF SCKE SOE


0 0 1 CH

Address

00000000B

Initial value

R/W

SIOE CKS1 BDS SSTCKS0

R/W R/W R/WR/W R/W R/WR/W


0 0 1 DH

Address

XXXXXXXXB

Initial value


SMR (Serial mode register)

SDR (Serial data register)

R/WR/W R/W R/WR/W R/W R/WR/W

187


8.4.1 Serial mode register (SMR)

The serial mode register (SMR) is used to enable and disable 8-bit serial I/O operation, select the shift clock, set the transfer direction, control interrupts, and check the status.

Serial mode register (SMR)

Figure 8.4-2 Serial mode register (SMR)

SIOE

0

1

SOE


0 0 1 CH

Address

00000000B

Initial value

CKS1 BDS SSTCKS0


Disable output of interrupt requests

Enable output of interrupt requests

SIOFInterrupt request flag bit

Transfer is incomplete Clear this bit

No change, no other effect

0

1

Read Write

SCKE Shift clock output enable bit

Use P30/SCK as a general-purpose

port or shift clock input pin

Use P30/SCK as the shift clock output pin

0

1

SIOF SIOE SCKE

Transfer is complete

SOE Serial data output enable bit

Use P31/SO as a general-purpose port

Use P31/SO as the serial data output pin

0

1

CKS1

0

0

1

1

CKS0

0

1

0

1

Shift clock select bits

Internal shift clock

External shift clock

SCK pin

Output

Output

Output

Input


Transfer direction select bit

LSB-first

(start transfer from least significant bit)

MSB-first

(start transfer from most significant bit)

BDS

0

1

SSTSerial I/O transfer start bit

0

1

Read Write

Serial transfer halted

Serial transfer in progress

Halt/disable serial transfer

Start/enable serial transfer


R/W : Readable and writable : Initial value

2tinst

8tinst

32tinst

188


Table 8.4-1 Function of each serial mode register (SMR) bit

Bit Description

bit7 SIOF: Interrupt request flag bit

• Set to "1" after the serial I/O operation has input and output 8 bits of serial data. An interrupt request is output if this bit and the interrupt request enable bit (SIOE) are "1".

• Writing "0" clears the bit. Writing "1" has no effect and does not change the bit value.

bit6 SIOE:Interrupt request enable bit

This bit enables or disables output of interrupt requests to the CPU.An interrupt request is output if this bit and the interrupt request flag bit (SIOF) are "1".

bit5bit4

SCKE:Shift clock output enable bit

• This bit controls shift clock input and output.• The P30/SCK pin becomes the shift clock input pin when this bit is

"0" and the shift clock output pin when the bit is "1".Caution:• When used as the shift clock input, the P30/SCK pin must be set as

an input port. Also, select the external shift clock in the shift clock select bits (CKS1, CKS0 = 11B).

• Select an internal shift clock (CKS1, CKS0 = other than 11B) when the pin is the shift clock output (SCKE = 1).

Note:• Enabling the shift clock output (SCKE = 1) causes the P30/SCK pin

to function as the SCK output pin regardless of the state of the general-purpose port (P30).

• When using the P30/SCK pin as a general-purpose port (P30), set as a shift clock input (SCKE = 0).

bit4 SOE: Serial data output enable bit

The P31/SO pin becomes a general-purpose port (P31) when this bit is "0" and the serial data output pin (SO) when the bit is "1".Note:

Enabling serial data output (SOE = 1) causes the P31/SO pin to function as the SO pin regardless of the state of the general-purpose port (P31).

bit3bit2

CKS1, CKS0:Shift clock select bits

• These bits select the external shift clock or one of the three internal shift clocks.

• When these bits are other than "11B", an external shift clock is selected and, if the shift clock output enable bit (SCKE) is "1", the shift clock is output from the SCK pin.

• When these bits are "11B", the external shift clock is selected and, if set as the shift clock input, the shift clock is input from the SCK pin.

bit1 BDS:Transfer direction select bit

This bit selects whether to transfer the serial data starting from the least significant bit (LSB-first, BDS = 0) or the most significant bit (MSB-first, BDS = 1).Caution:

As the bit order is set when the data is read or written to the serial data register (SDR), changing the value of this bit after data has been written to the SDR register invalidates the data.

189


bit0 SST:Serial I/O transfer start bit

• This bit controls starting and enabling of serial I/O transfer. The bit can also be used to test whether transfer is complete.

• When using an internal shift clock (CKS1, CKS0 = other than 11B), writing "1" to this bit clears the shift clock counter and starts transfer.

• When using an external shift clock (CKS1, CKS0 = 11B), writing "1" to this bit enables transfer, clears the shift clock counter, and waits for input of the external shift clock.

• When transfer is completed, the bit is cleared to "0" and the SIOF bit is set to "1".

• Writing "0" to this bit during transfer (SST = 1) halts the transfer. Once a transfer has been halted, the output SDR register must be written to again and the transfer restarted for data input (to clear the shift clock counter).

Table 8.4-1 Function of each serial mode register (SMR) bit (Continued)

Bit Description

190


8.4.2 Serial data register (SDR)

The serial data register (SDR) stores the 8-bit serial I/O transfer data.For serial output operation, the register functions as the transmission data register. For serial input operation, the register functions as the reception data register.


Figure 8.4-3 "Serial data register (SDR)" shows the bit structure of the serial data register.

Figure 8.4-3 Serial data register (SDR)

Serial output operation

The register functions as the transmission data register. Starting serial I/O transfer (SMR:SST =1) performs serial transfer of the data written to this register.

As the transmission data is shifted out by the transfer operation, the data does not remain in theSDR register.

Serial input operation

The register functions as the reception data register. Starting serial I/O transfer (SMR:SST = 1)stores the received serial transfer data in this register.

During serial I/O transfer

Do not write data to the SDR register while a serial I/O transfer operation is in progress.Similarly, values read from the register at this time have no meaning.

If serial output and serial input are enabled at the same time, both serial input and outputoperations are performed.


0 0 1 DH

Address

XXXXXXXXB

Initial value

R/WR/W R/W R/W R/W R/WR/WR/W

R/W : Readable and writable X : Undefined

191


8.5 8-Bit Serial I/O Interrupts

Completion of an 8-bit serial I/O operation generates an interrupt request from the 8-bit data serial I/O.

Interrupts during serial I/O operation

The 8-bit serial I/O performs serial input and serial output simultaneously. When serial transferstarts, the contents of the serial data register (SDR) are input and output one bit at a timesynchronized with the period of the specified shift clock. The interrupt request flag bit(SMR:SIOF) is set to "1" on the leading edge of the eighth shift clock pulse.

An interrupt request (IRQ4) is output to the CPU if the interrupt request output enable bit isenabled (SMR:SIOE = 1) at this time.

Write "0" to the SIOF bit in the interrupt processing routine to clear the interrupt request. TheSIOF bit is always set when the output of 8 bits of serial is completed, regardless of the SIOE bitvalue.

Note:

During serial I/O operation, setting the interrupt request flag bit (SMR:SIOF = 1) is notperformed if serial transfer is halted (SMR:SST = 0) at the same time that serial data transferis completed. An interrupt request is generated immediately if the SIOF bit is "1" when theSIOE bit is switched from disabled to enabled (0 to 1).

Register and vector table for the 8-bit serial I/O interrupt

For more information on interrupt operation, see Section 3.4.2 "Processing during an interrupt".

Table 8.5-1 Register and vector table for the 8-bit serial I/O interrupt



IRQ4 ILR4 (007DH) L40 (bit0) L41 (bit1) FFF2H FFF3H

192

8.6 Serial Output Operation

8.6 Serial Output Operation

The 8-bit serial I/O can output 8-bit serial data synchronized with a shift clock.

Serial output operation

Serial output can operate using either an internal or external shift clock. When serial I/Ooperation is enabled, the contents of the SDR register are output from the serial data output pin(SO) at the same time that serial input is performed.

When using an internal shift clock

Figure 8.6-1 "Serial output settings (for an internal shift clock)" shows the settings required foroperating serial output using an internal shift clock.

Figure 8.6-1 Serial output settings (for an internal shift clock)

Activating the serial output operation outputs the contents of the SDR register from the serialdata output pin (SO). Output is synchronized with the trailing edge of the selected internal shiftclock. At this time, the device being communicated with (serial input device) must be waiting forthe input of an external shift clock.

When using an external shift clock

Figure 8.6-2 "Serial output settings (for an external shift clock)" shows the settings required foroperating serial output using an external shift clock.

Figure 8.6-2 Serial output settings (for an external shift clock)

Enabling the serial output operation outputs the contents of the SDR register from the serialdata output pin (SO). Output is synchronized with the trailing edge of the external shift clock.When serial output is completed, the SDR register must immediately be set again and operationenabled (SMR:SST = 1) so as to be ready to output the next data.

When the serial input operation is completed (leading edge) at the receiving device, set theexternal shift clock to the "H" level while waiting for output of the next data (idle state).


: Used bit: Set "1"

SMR

SDR Sets transmit data

1

SIOF SIOE SSTBDSCKS0CKS1SOESCKE

1

1

1 Other than "11"


SMR

SDR Sets transmit data

DDR3

0

0


1 : Used bit: Unused bit: Set "1": Set "0"0

1

1 1 1

193


Figure 8.6-3 "Operation of 8-bit serial output" shows the operation of 8-bit serial output.

Figure 8.6-3 Operation of 8-bit serial output

Operation when serial output is completed

The interrupt request flag bit is set (SMR:SIOF = 1) and the serial I/O start bit cleared(SMR:SST = 0) on the leading edge of the shift clock after inputting and outputting the eighth bitof serial data.

#7 #5 #4SDR

For LSB-first transfer

#6 #3 #1 #0#2

#0 #1 #2 #3 #4 #5 #6 #7

Shift clock

SIOF bit

SST bit

SO pin

Serial output data


0 1 2 3 4 5 6 7 Cleared by the program

Automatically cleared when transfer is completed

Transfer start Interrupt request

194

8.7 Serial Input Operation

8.7 Serial Input Operation

The 8-bit serial I/O can input 8-bit serial data synchronized with a shift clock.

Serial input operation

Serial input can operate using either an internal or external shift clock. When serial I/Ooperation is enabled, the contents of the SDR register are output from the serial data output pin(SO) at the same time that serial input is performed.


Figure 8.7-1 "Serial input settings (for an internal shift clock)" shows the settings required foroperating serial input using an internal shift clock.

Figure 8.7-1 Serial input settings (for an internal shift clock)

Activating the serial input operation inputs the value of the serial data input pin (SI) to the SDRregister. Input is synchronized with the leading edge of the selected internal shift clock. At thistime, the device being communicated with (serial output device) must have set a value in theSDR register and be waiting for input of an external shift clock.


Figure 8.7-2 "Serial input settings (for an external shift clock)" shows the settings required foroperating serial input using an external shift clock.

Figure 8.7-2 Serial input settings (for an external shift clock)

Enabling the serial input operation inputs the value of the serial data input pin (SI) to the SDRregister. Input is synchronized with the leading edge of the external shift clock. When serialinput is completed, the SDR register must immediately be read and operation enabled(SMR:SST = 1) so as to be ready to input the next data.

DDR3


SMR

SDR

Stores the received data

00

0



1

1 1

DDR3


SMR

SDR

Stores the received data

00

0



1

1 1

195


While waiting for output of the next data (idle state), set the external shift clock to the "H" level.

Figure 8.7-3 "Operation of 8-bit serial input" shows the operation of 8-bit serial input.

Figure 8.7-3 Operation of 8-bit serial input

Operation when serial input is completed

The interrupt request flag bit is set (SMR:SIOF = 1) and the serial I/O start bit is cleared(SMR:SST = 0) on the leading edge of the shift clock after inputting and outputting the eighth bitof serial data.

#7 #5 #4SDR

For MSB-first transfer

#6 #3 #1 #0#2

#7 #6 #5 #4 #3 #2 #1 #0

Shift clock

SIOF bit

SST bit

SI pin

Serial input data


0 1 2 3 4 5 6

Automatically cleared when transfer is completed

7Cleared by the program

Interrupt request

196

8.8 States in Each Mode of 8-Bit Serial I/O Operation


This section describes the operation when the device enters sleep mode, the device enters stop or watch mode, or a halt request occurs during operation of the 8-bit serial I/O.


Operation in sleep mode

Figure 8.8-1 "Operation in sleep mode (internal shift clock)" shows how serial I/O operationdoes not halt and transfer continues when the device enters sleep mode.

Figure 8.8-1 Operation in sleep mode (internal shift clock)

Operation in stop or watch mode

Figure 8.8-2 "Operation in stop or watch mode (internal shift clock)" shows how serial I/Ooperation halts and transfer is interrupted when the device enters stop or watch mode. Whenthe device wakes up from stop or watch mode, operation restarts from the point where it halted.Therefore, initialize the serial I/O in accordance with the state of the device with which you arecommunicating.

Figure 8.8-2 Operation in stop or watch mode (internal shift clock)

Operation during a halt

Figure 8.8-3 "Operation during a halt (internal shift clock)" shows how transfer halts and the shiftclock counter is cleared when operation is halted midway through a transfer (SMR:SST = 0).

#0 #1 #2 #3 #4 #5 #6 #7

SCK output

SST bit

SIOF bit

SO pin output


Sleep

Wakeup from sleep mode via IRQ4


Interrupt request

#0 #1 #2 #3 #4 #5 #6 #7

SCK output

SST bit

SIOF bit

SO pin output

STP bit (STBC register) Wakeup from stop or watch mode via an external interrupt

Interrupt request

Cleared by the programOscillation stabilization delay time

Stop or watch mode request

Stop or watch mode

197


Accordingly, the device with which you are communicating must also be initialized. Whenperforming serial output, update the SDR register before restarting operation.

Figure 8.8-3 Operation during a halt (internal shift clock)


Operation in sleep mode

Figure 8.8-4 "Operation in sleep mode (external shift clock)" shows how serial I/O operationdoes not halt and transfer continues when the device enters sleep mode.

Figure 8.8-4 Operation in sleep mode (external shift clock)

Operation in stop or watch mode

Figure 8.8-5 "Operation in stop or watch mode (external shift clock)" shows how serial I/Ooperation halts and transfer is interrupted when the device enters stop or watch mode. Whenthe device wakes up from stop or watch mode, operation restarts from the point where it halted.Therefore, a transfer error occurs. You must reinitialize the serial I/O.

#0 #1 #2 #3 #4 #0 #1

SCK output

SST bit

SIOF bit

SO pin output #5

RestartOperation halted

Update SDR register

#0 #1 #2 #3 #4 #5 #6 #7

SCK input

SST bit

SIOF bit

SO pin output


Sleep

Wakeup from sleep mode via IRQ4

Clock for next data

Transfer disabled


198


Figure 8.8-5 Operation in stop or watch mode (external shift clock)

Operation during a halt

Figure 8.8-6 "Operation during a halt (external shift clock)" shows how transfer halts and theshift clock counter is cleared when operation is halted midway through a transfer (SMR:SST =0). Accordingly, the device with which you are communicating must also be initialized. Whenperforming serial output, update the SDR register before restarting operation. At this time, theSO pin output changes when an external clock is input.

Figure 8.8-6 Operation during a halt (external shift clock)

#0 #1 #2 #3 #4 #5 #6 #7

SCK input

SST bit

SIOF bit

SO pin output

STP bit (STBC register) Wakeup from stop or watch mode via an external interrupt

Interrupt request


Transfer error occurs

Oscillationstabilization delay time

#6 #7

Clock for next data

Stop or watch mode request

Stop or watch mode

#0 #1 #2 #3 #4 #0 #1

SCK input

SST bit

SIOF bit

SO pin output #5

RestartUpdate SDR register

Operation halted#6 #7

Clock for next data

199


8.9 Notes on Using 8-Bit Serial I/O

This section describes points to note when using the 8-bit serial I/O.

Notes on using 8-bit serial I/O

Error in serial transfer start timing

As the timing at which serial transfer is activated by the program (SMR:SST = 1) isasynchronous to the trailing (output) or leading (input) edge of the shift clock, the timing of thefirst serial data input or output may be delayed by up to the period of the specified shift clock.

Malfunction due to noise

Malfunction may occur on the serial I/O if an unwanted pulse (a pulse which exceeds thehysteresis width) is present on the shift clock due to external noise during serial data transfer.

Notes on setting the serial I/O by using the program

• Write to the serial mode register (SMR) and serial data register (SDR) when the serial I/O ishalted (SMR:SST = 0).

• Do not change the values of other SMR register bits when starting (enabling) serial I/Otransfer (SMR:SST = 1).

• When inputting an external shift clock and when serial data output is enabled (SMR:SOE =1), the output level of the SO pin enters the level of the most significant bit (for MSB-firsttransfer) or least significant bit (for LSB-first transfer) when the external shift clock is input,even if serial I/O transfer is halted (SMR:SST = 0).

• If serial I/O transfer is halted (SMR:SST = 0) at the same time that a serial data transfer iscompleted, the interrupt request flag bit (SMR:SIOF) is not set.

• Interrupt processing cannot return if the SIOF bit is "1" and interrupt request output isenabled (SIOE = 1). Always clear the SIOF bit.

Shift clock idle state

During the delay between 8-bit data transfers (idle state), set the external shift clock to the "H"level. When using an internal shift clock (SMR:CKS1, CKS0 = other than 11B) to provide theshift clock output (SMR:SCKE = 1), the output enters the "H" level when idling.

Figure 8.9-1 "Shift clock idle state" shows the idle state of the shift clock.

Figure 8.9-1 Shift clock idle state

8-bit data transfer8-bit data transferIdle state Idle state Idle stateExternal shift clock

200

8.10 8-Bit Serial I/O Connection Example

8.10 8-Bit Serial I/O Connection Example

This section shows an example of connecting together the 8-bit serial I/O of two MB89170/170A/170L series devices to perform bi-directional serial I/O.

Bi-directional serial I/O

Figure 8.10-1 8-bit serial I/O connection example (interfacing two MB89170/170A/170L devices)

SCK

SI

SO

SCK

SO

SI

SIO-A SIO-B

Internal shift clock External shift clock

Output Input

201


Figure 8.10-2 Operation of bi-directional serial I/O

START

Is serial transfer enabled for

SIO-B? (*1)

YES

Set output data

Transfer enable state

Set the SI pin as a serial data input (input port)

Set the SI pin as a serial data input (input port)

- Set the SCK pin as the shift clock output- Set the SO pin as the serial data output- Select an internal shift clock- Set the data transfer (shift) direction

NO

Start serial transfer (*2) (SST = 1)

8-bit transfer completed? (*3)

8-bit transfer completed? (*3)

YES (SST=0)

Serial data transfer in progress

Read input data Read input data

Is there more data for transfer?

NO

NO

END

Halt operation of SIO-A (SST = 0)

SIO-A

START

Set output data

- Set the SCK pin as the shift clock input- Set the SO pin as the serial data output- Select the external shift clock- Select the same data transfer (shift) direction as SIO-A

Enable serial transfer (SST = 1)

YES (SST=0)

NO

Serial data transfer in progress

Halt operation of SIO-B (SST = 0)

SIO-B

SIO-A outputs serial data

Simultaneously, SIO-A feeds the SIO-B data

SST: The SST bit is the serial I/O transfer start bit of the serial mode register (SMR).*1 When only the SO, SI, and SCK pins are connected, there is no direct means of determining if serial transfer is enabled on SIO-B. Therefore, use a software timer or other method to have the system wait a sufficient amount of time for SIO-B to enable transfer.*2 Data transfer is not performed correctly if SIO-A starts transfer when serial transfer is not enabled on SIO-B.*3 An interrupt request is generated when an 8-bit data transfer is completed.

SIO-A SIO-B

YES

202

8.11 8-Bit Serial I/O Program Example


This section describes example programs using the 8-bit serial I/O.

Program example for serial output


• Output 8 bits of serial data (55H) from the SO pin of the serial I/O and generate an interruptwhen transfer is completed.

• In the interrupt processing routine, set the next data to be transferred and restart output.

• Operate using an internal shift clock and output the shift clock from the SCK pin.

• The transfer speed and time between interrupts is as follows for a main clock sourceoscillation (FCH) of 7.16 MHz, the main clock speed (gear) set to maximum speed (1instruction cycle = 4/FCH), and 32tinst shift clock.

• Transfer speed = 7.16 MHz/4/32 = 55.9 kbps

• Interrupt period = 4 x 32 x 8/7.16 MHz = 143 µs

Coding example

SMR EQU 001CH ;Address of serial mode register SDR EQU 001DH ;Address of the timer 1 controlT1CR EQU 0019B ;Address of serial data register

SIOF EQU SMR:7 ;Interrupt request flag bit definitionSST EQU SMR:0 ;Serial I/O transfer start bit definition

ILR2 EUQ 007DH ;Address of the interrupt level set register

INT_V DSEG ;[DATA SEGMENT] ORG 0FFF2H IRQ4 DW WARI ;Interrupt vector settingINT_V ENDS WARI ;------Main program----------------------------------------------- CSEG ;[CODE SEGMENT] ;Assume stack pointer (SP), etc., ;have been already initialized. : CLRI ;Disable interrupts. CLRB SST ;Halt serial I/O transfer. MOV ILR1,#11111101B ;Set interrupt level (level 1). MOV SDR,#55H ;Set transfer data (55H). MOV SMR,#01111000B ;Clear interrupt request flag bit, ;enable output of interrupt requests, ;enable shift clock output (SCK), ;enable serial data output (SO), ;and select 32tinst, LSB-first.

203


SET1 SST ;Start serial I/O transfer. SETI ;Enable interrupts. : ;------Interrupt processing routine------------------------WARI CLRB STOF ;Clear interrupt request flag. PUSHW A XCHW A,T ;Save A and T. PUSHW A MOV SDR,#55H ;Update transfer data (55H). SETB SST ;Start serial I/O transfer. : User processing : POPW A XCHW A,T ;Restore A and T. POPW A RETI ENDS ;------------------------------------------------------------------- END

204


Program example for serial input


• Input 8 bits of serial data from the SI pin of the serial I/O and generate an interrupt whentransfer is completed.

• In the interrupt processing routine, read the transfer data and re-enable input.

• Operate using the external shift clock and input the shift clock from the SCK pin.

Coding example

DDR3 EQU 000DH SMR EQU 001CH ;Address of serial mode registerSDR EQU 001DH ;Address of serial data register

SIOF EQU SMR:7 ;Interrupt request flag bit definitionSST EQU SMR:0 ;Serial I/O transfer start bit ;definition

ILR2 EQU 007DH ;Address of the interrupt level set register

INT_V DSEG ABS ;[DATA SEGMENT] ORG 0FFF2H IRQ4 DW WARI ;Interrupt vector settingINT_V ENDS ;------Main program----------------------------------------------- CSEG ;[CODE SEGMENT] ;Assume stack pointer (SP), etc., ;have been already initialized. : MOV DDR3,#00000000B ;Set P30/SCK and P32/SI as inputs. CLRI ;Disable interrupts. CLRB SST ;Halt serial I/O transfer. MOV ILR2,#11111101B ;Set interrupt level (level 1). MOV SMR,#01111000B ;Clear interrupt request flag bit, ;enable output of interrupt requests, ;set shift clock input (SCK), ;disable serial data output (SO), ;and select the external clock, ;LSB-first. SETB SST ;Enable serial I/O transfer. SETI ;Enable interrupts. : ;------Interrupt processing routine------------------------WARI CLRB STOF ;Clear interrupt request flag. PUSHW A XCHW A,T PUSHW A MOV A,SDR ;Read transfer data. SETB SST ;Enable serial I/O transfer. : User processing : POPW A

205


XCHW A,T POPW A RETI ENDS ;------------------------------------------------------------------- END

206

CHAPTER 9 BUZZER OUTPUT

This chapter describes the functions and operation of the buzzer output.

9.1 "Overview of the Buzzer Output"

9.2 "Structure of the Buzzer Output"

9.3 "Buzzer Output Pin"

9.4 "Buzzer Output Register"

9.5 "Buzzer Output Program Example"

207


9.1 Overview of the Buzzer Output

The buzzer output can select seven different output frequencies (square wave). the buzzer output can be used to produce a key touch tone, etc.

Buzzer output function

The function of the buzzer output is to output a signal (square wave) for use as a confirmationtone and the like.

• Seven different buzzer output frequencies can be selected, or output can be disabled.

• The divided output of the timebase timer (four frequencies) or watch prescaler (threefrequencies) can be selected as the clock source for the buzzer output.

Note:

The buzzer output uses the divided output of the timebase timer or watch prescaler as is.therefore, clearing the clock source (timebase timer or watch prescaler) selected for thebuzzer output also has an effect on the buzzer output.

Caution:

The timebase timer does not operate when the main clock oscillation is halted (during sub-clock mode). therefore, in this case, do not select the timebase timer as the clock source ofthe buzzer output. similarly, do not select divided output of the watch prescaler when singleclock system has been selected as an option setting or for the MB89170l series.

Table 9.1-1 "Output frequencies" lists the seven available output frequencies (square wave)which can be set by the buzzer output function.

Note:

[Output Frequency Calculation Example]

The output frequency from the BZ pin is as follows when the buzzer register (BZCR) selects

Table 9.1-1 Output frequencies

Clock source Buzzer output period Square wave output (kHz)

Timebase timer

213/FCH FCH/213 (0.437 kHz)

212/FCH FCH/212 (0.874 kHz)

211/FCH FCH/211 (1.748 kHz)

210/FCH FCH/210 (3.496 kHz)

Watch prescaler

25/FCL FCL/25 (1.024 kHz)

24/FCL FCL/24 (2.048 kHz)

23/FCL FCL/23 (4.096 kHz)

FCH: Frequency of the main clock source oscillationFCL: Frequency of the sub-clock source oscillationThe figures in parentheses ( ) are the frequencies when FCH = 3.58 MHz and FCL = 32.768kHz.

208

9.1 Overview of the Buzzer Output

the FCH/211 divided output of the timebase timer (BZ2, BZ1, BZ0 = 011B) and the main clocksource oscillation (FCH) is 3.58 mhz.

Output Frequency =FCH211

=3.58 MHz/2048

1.748 kHz

209


9.2 Structure of the Buzzer Output

The buzzer output consists of the following two blocks:• Buzzer output selector• Buzzer register (BZCR)

Block diagram of buzzer output

Figure 9.2-1 Block Diagram Of Buzzer Output

Buzzer output selector

This circuit selects one frequency from the four frequencies (square wave) output by thetimebase timer and three frequencies output by the watch prescaler.

Buzzer register (BZCR)

This register sets the buzzer output frequency and enables the output.

Setting a buzzer output frequency in the bzcr register (setting other than 000B) enables buzzeroutput.

Internal data bus


Buzzer output

Buzzer output enable signal

P37/BZ

213/FCH

212/FCH

211/FCH

210/FCH

25/FCL

24/FCL

23/FCL

Buzzer output selector

FCH: Frequency of main clock source oscillationFCL: Frequency of sub-clock source oscillation

From timebase timer

BZ1 BZ0BZ2

Pin

From watch prescaler

Selection

210

9.3 Buzzer Output Pin

9.3 Buzzer Output Pin

This section describes the buzzer output pin and the pin block diagram.

Buzzer output pin

The buzzer output pin is P37/BZ.

P37/bz pin

The P37/BZ pin can function as either a general-purpose I/O port (P37) or the buzzer output pin(BZ).

Bz:

This pin outputs a square wave at the specified buzzer frequency. the P37/BZ pinautomatically functions as the BZ pin when a buzzer output frequency is set(BZCR:BZ2,BZ1,BZ0 = other than 000B), regardless of the output latch setting.

Block diagram of buzzer output pin

Figure 9.3-1 Block Diagram Of P37/bz Pin

Note:


From buzzer output

From buzzer output enable signal

P37/BZ

Pin

Pch

Nch

Pull-up resistor (option) 50 k approx. (at 5 V)

Pch

PDR read


PDR write

DDR write

DDR read

Output latch



DDR

Inte

rnal

dat

a bu

s




To peripheral input

211


9.4 Buzzer Output Register

This section describes the buzzer output register.

Buzzer output register

Figure 9.4-1 Buzzer Output Register


0 0 0 FH

Address

XXXXX000B

Initial value

R/WR/W

BZ0BZ1BZ2

R/W

BZCR (Buzzer register)

R/W: Readable and writable-: UnusedX: Undefined

212

9.4 Buzzer Output Register

9.4.1 Buzzer Register (BZCR)

The buzzer register (BZCR) is used to select the buzzer output frequency and enable buzzer output.


Figure 9.4-2 Buzzer Register (BZCR)


0 0 0 FH

Address

XXXXX000B

Initial value

R/WR/W

BZ0BZ1BZ2

R/W

BZ0BZ1BZ2

FCH/213

Use as the buzzer output pin (BZ)

Timebase timer output

Watch prescaler output

0001111

1

0

1

11

1

1

1

1

0 0

00

0

0

0

0

General-purpose output port (P37)

Buzzer select bits(for FCH = 3.58 MHz, FCL = 32 kHz)

R/W: Readable and writable - : Unused X : Undefined : Initial valueFCH: Main clock oscillation frequencyFCL: Sub-clock oscillation frequency

FCL/23FCL/24

FCL/25FCH/210FCH/211FCH/212

213


Table 9.4-1 Function of each serial mode register (SMR) bit

Bit Description

bit7bit6bit5bit4bit3

Unused bits

• The read values are undefined.• Writing has no effect on operation.

bit2bit1bit0

BZ2, BZ1, BZ0: Buzzer select bits

• These bits select the buzzer output and enable output.• Setting these bits to "000B" disables buzzer output. In this case, the

pin functions as a general-purpose port (P37). Setting other than "000B" sets the pin as the buzzer output pin (BZ) and outputs a square wave at the selected frequency.

• The buzzer output frequency can be selected from four divided outputs of the timebase timer and three divided outputs of the watch prescaler.

Caution:• Do not select the divided output of the timebase timer in sub-clock

mode.• For the MB89170L series, the divided output of the watch prescaler

cannot be selected.Note:

The sub-clock oscillates in main-stop mode.Consequently, if the divided output of the watch prescaler is selected as the buzzer output (BZ2, BZ1, BZ0 = 101B to 111B) and the pin state set bit (STBC:SPL) is "0", buzzer output can continue in main-stop mode.

214

9.5 Buzzer Output Program Example

9.5 Buzzer Output Program Example

This section shows an example program using the buzzer output.

Buzzer output program example


• Output a buzzer tone of approximately 0.437 KHz from the BZ pin, and then turn off thebuzzer output.

• The buzzer output frequency for the case when the main clock source oscillation is 3.58 MHz

and 213/FCH (FCH: Main clock source oscillation) is selected is as follows.

• Buzzer output frequency = 3.58 MHz/213 = 3.58 MHz/8192 = 0.437 KHz

Coding Example

BZCR EQU 000FH ;Address of the buzzer register ;-----------MAIN PROGRAM-------------------------------------------- CSEG ;[CODE SEGMENT] :BUZON MOV BZCR,#00000001B ;Turn on buzzer output. ;(Approx. 0.437 kHz for a 3.58 MHz ;Main clock) : :BUZOFF MOV BZCR,#00000000B ;Turn off buzzer output. : ENDS ;------------------------------------------------------------------- END

215


216

CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)

This chapter describes the functions and operation of external interrupt circuit 1 (edge).

10.1 "Overview of External Interrupt Circuit 1 (Edge)"

10.2 "Structure of External Interrupt Circuit 1"

10.3 "External Interrupt Circuit 1 Pins"

10.4 "External Interrupt Circuit 1 Registers"

10.5 "External Interrupt Circuit 1 Interrupts"

10.6 "Operation of External Interrupt Circuit 1"

10.7 "Sample Programs of External Interrupt Circuit 1"

217


10.1 Overview of External Interrupt Circuit 1 (Edge)

External interrupt circuit 1 detects the specified edges of the signals that are input to three external interrupt pins and outputs the corresponding interrupt requests to the CPU.

External interrupt circuit 1 functions (edge detection)

External interrupt circuit 1 detects the specified edges of the signals that are input to theexternal input pins and outputs interrupt requests to the CPU. These interrupts can be used towake up from standby mode and return the normal operating state (the main-RUN or sub-RUNstate).

• External interrupt pins: 3 pins (P34/T0/INT0 to P36/INT2)

• External interrupt sources: Signals input to the external interrupt pins on the specified edge(leading edge, trailing edge, or both)

• Interrupt control: Output of interrupt requests can be enabled or disabled by using theinterrupt request enable bits of the interrupt request output external interrupt 1 controlregisters 1 and 2 (EIC1, EIC2).

• Interrupt flags: The specified edges are detected by using the external interrupt request flagbits of the interrupt request output external interrupt 1 control registers 1 and 2 (EIC1, EIC2)

• Interrupt requests: Generated independently of each external interrupt source (IRQ0, IRQ1,IRQ2).

218

10.2 Structure of External Interrupt Circuit 1


External interrupt circuit 1 consists of three blocks that have the same functions. Each block consists of the following two elements• Edge detection circuits (0 to 2)• External interrupt 1 control registers 1 and 2 (EIC1, EIC2)

Block diagram of external interrupt circuit 1

Figure 10.2-1 Block diagram of external interrupt circuit 1

Edge detection circuit

When the edge polarity of the signal that is input to the external interrupt pin (INT0 to INT2)matches the edge polarity selected by the EIC1 or EIC21 register, the corresponding externalinterrupt request flag bit (EIR0 to EIR2) is set to 1.

External interrupt 1 control registers 1 and 2 (EIC1, EIC2)

The EIC1 and EIC2 registers select edges, enable and disable interrupt requests, and checkinterrupt requests.

EIR1

External interrupt 1 control register 1

External interrupt 1 control register 2

EIC2

P35/INT1

P34/TO/INT0




SL10 SL01SL11 EIE1 EIR0 SL00 EIE0

Edge detection circuit 1 Edge detection circuit 0S

elec

tor

Sel

ecto

rS

elec

tor

Edge detection circuit 2

Pin

Pin

P36/INT2

SL21EIR2 SL20 EIE2

Pin

EIC1

1X

00

01

1X

00

01

1X

00

01

219


External interrupt circuit 1 interrupt requests

IRQ0:

This interrupt request is generated, if interrupt request output is enabled (EIC1: EIE0 = 1),when an edge with the specified polarity is input to the external interrupt pin INT0.

IRQ1:


IRQ2:


220

10.3 External Interrupt Circuit 1 Pins

10.3 External Interrupt Circuit 1 Pins

This section describes the pins for external interrupt circuit 1 and shows their block diagram.

Pins for external interrupt circuit 1

The pins for external interrupt circuit 1 are P34/T0/INT0, P35/INT1, and P36/INT2.

P34/T0/INT0 pin

The P34/T0/INT0 pin functions as a general-purpose I/O port (P34), a square wave output pinfor the 8/16-bit timer/counter (T0), or an external interrupt input pin (INT0).

The P34/T0/INT0 pin functions as an external interrupt input (INT0) if square wave output fromthe 8/16-bit timer/counter is disabled in the timer 1 control register (T1CR) and the pin is set asan input port in the port data direction register (DDR3). However, interrupt requests are notoutput if output of interrupt requests is not enabled in external interrupt 1 control registers 1 and2 (EIC1, EIC2). The pin state can be always read from the port data register (PDR3).

P35/INT1 and P36/INT2 pins

The P35/INT1 and P36/INT2 pins function as general-purpose I/O ports (P35, P36) or externalinterrupt input (hysteresis input) pins (INT1, INT2).

The P35/INT1 and P36/INT2 pins function as external interrupt input pins (INT0 to INT2) if thepins are set as input ports in the port data direction register (DDR3). However, interruptrequests are not output if external interrupt requests are not enabled in external interrupt 1control registers 1 and 2 (EIC1, EIC2).

The pin state can be always read from the port data register (PDR3).

Table 10.3-1 "Pins for external interrupt circuit 1" lists the pins for external interrupt circuit 1.

Table 10.3-1 Pins for external interrupt circuit 1

External interrupt pin

Used as an external interrupt input pin (interrupt request output enabled)

Used as a general-purpose I/O port(interrupt request output disabled)

P34/T0/INT0 INT0 (EIC1:EIE0=1), DDR3:bit4=0, T1CR:T1OS1, T1OS0=00B)

P34 (EIC1:EIE0=0)

P35/INT1 INT1 (EIC1:EIE1=1, DDR3:bit5=0) P35 (EIC1:EIE1=0)

P36/INT2 INT2 (EIC2:EIE2=1, DDR3:bit6=0) P36 (EIC2:EIE2=0)

INT0 to INT2: These pins generate the corresponding interrupt request when detecting an edge with the selected polarity.

221


Block diagram of pins for external interrupt circuit 1

Figure 10.3-1 Block diagram of pins for external interrupt circuit 1

Note:

When a pull-up resistor is selected optionally, the pin is kept high during a reset, stop mode,or watch mode (SPL = 1).

From square wave output of the 8/16-bit timer/counter (P34 only)

From the output enable signal of the 8/16-bit timer/counter (P34 only)

To edge detection circuit

P34/TO/INT0P35/INT1P36/INT2

Pin

Pch

Nch

Pull-up resistor (optional)50 k approx. (at 5V)

Pch

PDR read

PDR read (during bit manipulation instruction execution)

PDR write

DDR write

DDR read

Output latch


PDR (port data register)

DDR

Inte

rnal

dat

a bu

s

(port data direction register)


SPL: Pin state specification bit of the standby control register (STBC)

To resource input

External interrupt input enable

222

10.4 External Interrupt Circuit 1 Registers


This section describes the registers for external interrupt circuit 1.

Registers for external interrupt circuit 1

Figure 10.4-1 Registers for external interrupts

EIR1 SL10SL11 SL00SL01

SL20SL21


0 0 2 3H

Address

00000000B

XXXX0000B

Initial value

R/WR/W

EIE0

R/W R/W R/W R/W R/W

EIE1 EIR0

R/W

INT1 INT0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0Address Initial value

EIE2

R/W R/W R/W

EIR2

R/W

INT2

EIC1 (External interrupt 1 control register 1)

EIC2 (external interrupt 1 control register 2)

0 0 2 4H

R/W: Can be read and written : Unused X : Undefined

223


10.4.1 External interrupt 1 control register 1 (EIC1)

External interrupt 1 control register 1 (EIC1) is used to select the edge polarity and control interrupts for the external interrupt pins INT0 and INT1.

External interrupt 1 control register 1 (EIC1)

Figure 10.4-2 Functions of external interrupt 1 control register 1 (EIC1) bits

External interrupt request flag bit 0

R/W

EIR1


0 0 2 3H

Address

00000000B

Initial value

EIE0

R/W

Interrupt request enable bit 1

Disables interrupt request outputEnables interrupt request output

SL10SL11 SL00SL01

R/W R/WR/WR/W

EIE101

EIE1 EIR0

R/W R/W

EIR1External interrupt request flag bit 1

01

EIR0

01

SL010011

SL000101

EIE001

Read Write

The specified edge has not been input

The specified edge has been input

ReadClears this bit

Has no other effect

The specified edge has not been input

The specified edge has been input

Clears this bit

Has no other effect

Write

Edge polarity selection bits 0

Leading edge

Trailing edgeBoth edges

Both edges

SL110011

SL100101


Leading edge

Trailing edgeBoth edges

Both edges

Interrupt request enable bit 0

Disables interrupt request output

Enables interrupt request output

INT0 (IRQ0)

INT1 (IRQ1)

R/W: Can be read and written - : Unused X : Undefined : Initial value

224


Table 10.4-1 Functions of external interrupt 1 control register 1 (EIC1) bits

Bit Description

bit7 EIR1: External interrupt request flag bit 1

• This bit is set to 1 if the edge selected by edge polarity selection bit 1 (SL10, SL11) is input to the external interrupt pin INT1.

• An interrupt request is output when this bit and interrupt request enable bit 1 (EIE1) are 1.

• Writing 0 clears the bit. Writing 1 does not change the bit value.

bit6bit5

SL11, SL10:Edge polarity selection bit 1

• These bits specify which edge polarity of pulses sent to the external interrupt pin INT1 is used to trigger an interrupt.

• When these bits are set to 00B, an interrupt is detected on the leading edge. When set to 01B, it is detected on the trailing edge. When set to 10B or 11B, it is detected on both the leading and trailing edges.

bit4 EIE1:Interrupt request enable bit 1

This bit enables or disables interrupt request output to the CPU. An interrupt request is output if this bit and external interrupt request flag bit 1 (EIR1) are 1.

bit3 EIR0:External interrupt request flag bit 0

• This bit is set to 1 if the edge selected by the edge polarity selection bits 0 (SL00, SL01) is input to the external interrupt pin INT0.



bit2bit1

SL01, SL00: Edge polarity selection bits 0

• These bits specify which edge polarity of pulses sent to the external interrupt pin INT0 is used to trigger an interrupt.



• This bit enables or disables an interrupt request output to the CPU. An interrupt request is output if this bit and external interrupt request flag bit 0 (EIR0) are 1.

225


10.4.2 External interrupt 1 control register 2 (EIC2)

External Interrupt 1 control register 2 (EIC2) is used to select the edge polarity and control interrupts for the external interrupt pin INT2.

External interrupt 1 control register 2 (EIC2)

Figure 10.4-3 Functions of external interrupt 1 control register 2 (EIC2) bits

R/W


0 0 2 4H

Address

XXXX0000B

Initial value

EIE2

R/W

SL20SL21EIR2

R/W R/W

EIR2 External interrupt request flag bit 2

01

SL210011

SL200101

EIE201

The specified edge has not been inputThe specified edge has been input

ReadClears this bitHas no other effect

Write


Leading edgeTrailing edgeBoth edgesBoth edges

Interrupt request enable bit 2Disables interrupt request outputEnables interrupt request output

INT2 (IRQ2)

R/W: Can be read and written - : Unused X : Undefined : Initial value

226


Table 10.4-2 Functions of external interrupt 1 control register 2 (EIC2) bits

Bit Description

bit7bit6bit5bit4

Unused bits • These bit values are undefined during read operation.• Writing these bits has no effect on operation.

bit3 EIR2:External interrupt request flag bit 2

• This bit is set to 1 if the edge selected by the edge polarity selection bits 2 (SL20, SL21) is input to the external interrupt pin INT2.



bit2bit1

SL21, SL20:Edge polarity selection bits 2

• These bits specify which edge polarity of pulses sent to the external interrupt pin INT2 to use to trigger an interrupt.



This bit enables or disables interrupt request output to the CPU. An interrupt request is output if this bit and external interrupt request flag bit 2 (EIR2) are 1.

227


10.5 External Interrupt Circuit 1 Interrupts

External interrupt circuit 1 triggers an interrupt when detecting the specified edge of the signals that are input to the external interrupt pins.

Interrupts during external interrupt circuit 1 operation

Detection of the specified edge of an external interrupt input sets the corresponding externalinterrupt request flag bit (EIC1, EIC2: EIR0 to EIR2) to 1. An interrupt request (IRQ0 to IRQ2)is output to the CPU if the corresponding interrupt request enable bit is enabled (EIC1, EIC2:EIE0 to EIE2 = 1) at this time. Write 0 to the corresponding external interrupt request flag bitwith the interrupt processing routine to clear the interrupt request.

Caution:

When enabling interrupts (EIE0 to EIE2 = 1) after a reset, always clear the external interruptrequest flag bits (EIR0 to EIR2 = 0) at the same time. The system cannot return frominterrupt processing, if the external interrupt request flag bit is 1 and the interrupt requestenable bit is enabled. Be sure to clear the external interrupt request flag bit in the interruptprocessing routine.

Note:

• The external interrupt request flag bit is always set when the specified edge is detected,regardless of the value of the interrupt request enable bit (EIE0 to EIE2).

• Waking up the device from stop mode via an interrupt can be done using only externalinterrupt circuits 1 and 2

• An interrupt request is generated immediately after the interrupt request enable bit isswitched from disabled to enabled (from 0 to 1) when the external interrupt request flag bit is1.

Registers and vector tables for external interrupt circuit 1 interrupts


Table 10.5-1 Registers and vector tables for external interrupt circuit 1 interrupts

InterruptInterrupt level set register Vector table address


IRQ0 ILR1 (007CH) L01 (bit1) L00 (bit0) FFFAH FFFBH



228

10.6 Operation of External Interrupt Circuit 1


External interrupt circuit 1 can be used to detect the specified edges of the signals that are input to the external interrupt pins.

Operation of external interrupt circuit 1

Figure 10.6-1 "External interrupt circuit 1 settings" shows the settings required for operatingexternal interrupt circuit 1.

Figure 10.6-1 External interrupt circuit 1 settings

If an edge of the signal that is input to an external interrupt pin (INT0 to INT2) matches the edgepolarity selected in the external interrupt 1 control register (EIC1, EIC2: SL00 to SL21), thecorresponding external interrupt request flag bit (EIC1, EIC2: EIR0 to EIR2) is set to 1.

Figure 10.6-2 "External interrupt (INT0) operation" shows the operation when the INT0 pin isused as an external interrupt input.


EIC2

DDR3

EIE2EIR2

EIC1

: Used bit: Bit that is set to 0 when the corresponding pin is used: Unused bit

EIR1 EIE0EIR0EIE1SL10SL11 SL00SL01

SL20SL21

229


Figure 10.6-2 External interrupt (INT0) operation

Note:

Even when the INT0 pin is used as an external interrupt input, the pin state can still be readdirectly from the port data register (PDR3).

Input waveform to the INT0 pin

SL00 bit

SL01 bit

Leading edge Trailing edge Both edges

EIE0 bit

EIR0 bit

Interrupt request flag bit is cleared by the program

IRQ0

Cleared at the same time that the EIE0 bit is set

230

10.7 Sample Programs of External Interrupt Circuit 1

10.7 Sample Programs of External Interrupt Circuit 1

This section shows a sample program for external interrupt circuit 1.

Sample programs of external interrupt circuit 1

Program specification

Generates an interrupt upon detection of the leading edge of a pulse that is input to the INT0pin.

Coding example

DDR3 EQU 000DH ;Address of the port data direction register EIC1 EQU 0023H ;Address of the external interrupt 1 control register 1ILR1 EQU 007CH ;Address of the interrupt level set register

EIR0 EQU EIC1:3 ;External interrupt request flag bit definitionSL01 EQU EIC1:2 ;Edge polarity selection bit definition SL00 EQU EIC1:1 ;Edge polarity selection bit definitionEIE0 EQU EIC1:0 ;Interrupt request enable bit definition

INT_V DSEG ABS ;[DATA SEGMENT] ORG 0FFFAH IRQ0 DW WARI ;Interrupt vector settingINT_V ENDS ;------Main program----------------------------------------------- CSEG ;[CODE SEGMENT] ;Assume the stack pointer (SP) and other registers are already initialized. : CLRI ;Interrupts disabled MOV DDR3,#00000000B ;Setting P34 as an input (#XXX0XXXXB) CLRB EIR0 ;External interrupt request flag bit cleared MOV ILR1,#11111110B ;Setting interrupt level to 2 CLRB SL01 ;Leading edges selected CLRB SL00 ; SETB EIE0 ;Output of interrupt requests enabled. SETI ;Interrupts enabled :;------Interrupt program--------------------------------------------WARI CLRB EIE0 ;External interrupt request flag cleared

231


PUSHW A XCHW A,T PUSHW A : User processing : POPW A XCHW A,T POPW A RETI ENDS ;------------------------------------------------------------------- END

232

CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)

This chapter describes the functions and operation of external interrupt circuit 2 (level).

11.1 "Overview of External Interrupt Circuit 2 (Level)"

11.2 "Structure of External Interrupt Circuit 2"

11.3 "Pins of External Interrupt Circuit 2"

11.4 "Registers of External Interrupt Circuit 2"

11.5 "Interrupts from External Interrupt Circuit 2"

11.6 "Operation of External Interrupt Circuit 2"

11.7 "Sample Programs for External Interrupt Circuit 2"

233


11.1 Overview of External Interrupt Circuit 2 (Level)

External interrupt circuit 2 detects the level of the signals that are input from eight external interrupt pins and outputs one interrupt request to the CPU.

External interrupt circuit 2 functions (level detection)

External interrupt circuit 2 detects an L level signal that is input from the external interrupt pinsand outputs an interrupt request to the CPU. This interrupt can be used to wake up the devicefrom standby mode and restore the normal operating state (the main-RUN or sub-RUN state).

• External interrupt pins: 8 pins (P00/INT20 to P07/INT27)

• External interrupt sources: Input of an L level signal to an external interrupt pin.

• Interrupt control: The external interrupt inputs can be enabled or disabled using the externalinterrupt 2 control register (EIE2).

• Interrupt flag: The external interrupt request flag bit of the external interrupt 2 flag register(EIF2) indicates detection of an L level.

• Interrupt requests: An interrupt request is generated by ORing the individual externalinterrupt sources (IRQA).

Caution:

Use the MB89PV170A to evaluate the functions of external interrupt circuit 2.

234



External interrupt circuit 2 consists of the following three blocks.• Interrupt request generation circuit • External interrupt 2 control register (EIE2) • External interrupt 2 flag register (EIF2)

Block diagram of external interrupt circuit 2

Figure 11.2-1 Block diagram of external interrupt circuit 2

Interrupt request generation circuit

The interrupt request generation circuit generates the interrupt request signal based on the inputfrom the external interrupt pins INT20 to INT27 and the external interrupt input enable bits.

External interrupt 2 control register (EIE2)

The external interrupt input enable bits (IE20 to IE27) enable or disable L level inputs from thecorresponding external interrupt pins.

External interrupt 2 flag register (EIF2)

The external interrupt request flag bit (IF20) is used to store or clear generated interrupt requestsignals.

Interrupt request generation circuit

IF20IE27 IE25IE24 IE23 IE21IE20IE26 IE22

P00/INT20 Pin

P01/INT21 Pin

P02/INT22 Pin

P03/INT23 Pin

P04/INT24 Pin

P05/INT25 Pin

P06/INT26 Pin

P07/INT27 Pin

External interrupt request IRQA



8

235


External interrupt circuit 2 interrupt sources

IRQA:

An Interrupt request is generated if an L level signal is input to any of the external interruptpins INT20 to INT27and the external interrupt input enable bit corresponding to that pin is 1.

236

11.3 Pins of External Interrupt Circuit 2

11.3 Pins of External Interrupt Circuit 2

This section describes the pins for external interrupt circuit 2 and provides their block diagram.

Pins for external interrupt circuit 2

There are eight external interrupt pins for external interrupt circuit 2.

P00/INT20 to P07/INT27

These external interrupt pins function as either external interrupt inputs (hysteresis inputs) orgeneral-purpose I/O ports.

The P00/INT20 to P07/INT27 pins function as external interrupt input pins (INT20 to INT27) ifthe corresponding pin is set as an input port in the port data direction register (DDRO) andexternal interrupt input is enabled in the external interrupt 2 control register (EIE2). If a pin isset as an input port, the pin state can always be read from the port data register (PDR0).

Table 11.3-1 "Pins for external interrupt circuit 2" lists the pins for external interrupt circuit 2.

Table 11.3-1 Pins for external interrupt circuit 2

External interrupt pin Used as external interrupt input (interrupt input enabled)

Used as general-purpose I/O port (interrupt input disabled)

P00/INT20 INT20 (EIE2:IE20=1 DDR0:bit0=0) P00 (EIE2:IE20=0)

P01/INT21 INT21 (EIE2:IE21=1, DDR0:bit1=0) P01 (EIE2:IE21=0)







237


Block diagram of pins for external interrupt circuit 2

Figure 11.3-1 Block diagram of pins for external interrupt circuit 2

Note:

When a pull-up resistor is selected optionally, the pin state goes high during a reset, stopmode, or watch mode (SPL = 1).

Correspondence between the interrupt enable bits and external interrupt pins in external interrupt circuit 2

Table 11.3-2 "Correspondence between the interrupt enable bits and the external interrupt pins"lists the correspondence between the interrupt enable bits and the external interrupt pins.

PDR read

PDR write

Output latch


PDR (port data register)

Inte

rnal

dat

a bu

s

Pin

Pch

NchDDR

PDR read

Pull-up resistor (optional)

50 k approx. (at 5V)

To external interrupt circuit From external interrupt input enable


DDR write

Pch

(port data direction register)

SPL: Pin state set bit of standby control register (STBC)

P00/INT20P01/INT21P02/INT22P03/INT23P04/INT24P05/INT25P06/INT26P07/INT27

(during bit manipulation instruction execution)

Table 11.3-2 Correspondence between the interrupt enable bits and the external interrupt pins

Register Bit External interrupt pin

EIE2

bit0 IE20 INT20

bit1 IE21 INT21

bit2 IE22 INT22

bit3 IE23 INT23

bit4 IE24 INT24

bit5 IE25 INT25

bit6 IE26 INT26

bit7 IE27 INT27

238

11.4 Registers of External Interrupt Circuit 2


This section describes the registers for external interrupt circuit 2.

Registers for external interrupt circuit 2

Figure 11.4-1 Registers for external interrupts 2

IE27 IE25IE26


0 0 3 2H

Address

00000000B

Initial value

R/W

IE21 IE20

R/W R/W R/W R/W

IE24 IE23 IE22

R/W


0 0 3 3H

Address

XXXXXXX0B

Initial value

IF20

R/W

R/W : Can be read and written- : UnusedX : Undefined

EIE2 (external interrupt 2 control register)

EIF2 (external interrupt 2 flag register)

R/W R/W

239


11.4.1 External interrupt 2 control register (EIE2)

The external interrupt 2 control register (EIE2) is used to enable and disable the interrupt inputs from the external interrupt pins INT20 to INT27.


Figure 11.4-2 External interrupt 2 control register (EIE2)

R/W

IE27


0 0 3 2H

Address

00000000B

Initial value

IE21 IE20

R/W

IE25

R/W R/WR/W

IE26 IE22IE24 IE23

R/W

R/W : Can be read and written

: Initial value

R/WR/W

External interrupt input enable bit

0

1

Disables external interrupt input

Enables external interrupt input

IE20to

IE27

Table 11.4-1 Correspondence between each bit of external interrupt 2 control register (EIE2) and external interrupt pin

Bit External interrupt pin

bit7 IE27 INT27

bit6 IE26 INT26

bit5 IE25 INT25

bit4 IE24 INT24

bit3 IE23 INT23

bit2 IE22 INT22

bit1 IE21 INT21

bit0 IE20 INT20

240


Table 11.4-2 Functions of external interrupt 2 control register (EIE2) bits

Bit Description

bit7bit6bit5bit4bit3bit2bit1bit0

IE20 to IE27: External interrupt input enable bits

• These bits enable or disable interrupt inputs from the external interrupt pins INT20 to INT27.

• Setting these bits to 1 sets the corresponding external interrupt pin to function as an external interrupt input pin and to accept input of external interrupts.

• Setting these bits to 0 sets the corresponding external interrupt pin to function as a general-purpose port and not to accept input of external interrupts.

Note:• If using a pin as an external interrupt pin, write 0 to the

corresponding bit of the port data direction register (DDRO) to set the pin as an input.

• The state of external interrupt pins can be read directly from the port data register (PDR0) regardless of the value of the corresponding external interrupt input enable bits.

241


11.4.2 External interrupt 2 flag register (EIF2)

The external interrupt 2 flag register (EIF2) is used to indicate detection of a level interrupt and to clear the interrupt request flag.


Figure 11.4-3 External interrupt 2 flag register (EIF2)

Table 11.4-3 Functions of external interrupt 2 flag register (EIF2) bits

Bit Description

bit7bit6bit5bit4bit3bit2bit1

Unused bit• These bit values are undefined during read operation.• Writing these bits has no effect on operation.

bit0 IF20:External interrupt request flag bit

• Set to 1 if an L level is input to an external interrupt input pin (INT20 to INT27) for which external interrupt input is enabled.

• Writing 0 clears the bit. Writing 1 does not change the bit value and has no other effect.

Note:The external interrupt input enable bits of the external interrupt 2 control register (EIE2: IE20 to IE27) only enable or disable external interrupt input. Interrupt requests are output continuously until the IF20 bit is cleared to 0.

External interrupt request flag bit


0 0 3 3H

Address

XXXXXXX0B

Initial value

IF20

R/W

IF20

0

1 Interrupt request not detected (an L level not detected)

Read

Interrupt request detected (an L level detected)

Write

R/W : Can be read and written- : UnusedX : Undefined

: Initial value

Has no other effect.

Clears this bit

242

11.5 Interrupts from External Interrupt Circuit 2

11.5 Interrupts from External Interrupt Circuit 2

Input of an L level signal to an external interrupt pin triggers an interrupt from external interrupt circuit 2.

Interrupt during external interrupt circuit 2 operation

Input of an L level to an external interrupt input pin for which interrupt input has been enabledsets the external interrupt request flag bit (EIF2: IF20) to 1 and outputs an interrupt request(IRQA) to the CPU. Write 0 to the IF20 bit in the interrupt processing routine to clear theinterrupt request.

If the external interrupt request flag bit (IF20) is set to 1, the interrupt request is outputcontinuously until the IF20 bit is cleared to 0. Output of the interrupt request continues even ifinput of external interrupts is disabled by the interrupt enable bits (IE20 to IE27) in the externalinterrupt 2 control register (EIE2). Therefore, always clear the IF20 bit.

Also, if an external interrupt pin is still at the L level when the IF20 bit is cleared with no externalinterrupt input disabled, the IF20 bit is set again immediately. If necessary, disable the externalinterrupt input or clear the external interrupt source itself.

Caution:

Always clear the IF20 bit before enabling CPU interrupts after a reset.

Notes:

• An L level input to any of the external interrupt pins (INT20 to INT27) generates the sameinterrupt request (IRQA). To determine which external interrupt input pin triggered theinterrupt, you must read the port data register (PDR0) before the input changes to an H level.

• Waking up the device from stop mode with an interrupt can be done using only externalinterrupt circuits 1 and 2.

Register and vector table for the external interrupt circuit 2 interrupt


Table 11.5-1 Register and vector table for the external interrupt circuit 2 interrupt



IRQA ILR3 (007EH) LA1 (bit5) LA0 (bit4) FFE6H FFE7H

243



External interrupt circuit 2 can be used to detect an L level on the input to the external interrupt pins and output an interrupt request to the CPU.

Operation of external interrupt circuit 2

Figure 11.6-1 "External interrupt circuit 2 settings" shows the settings required for operatingexternal interrupt circuit 2.

Figure 11.6-1 External interrupt circuit 2 settings

Input of an L level signal to any external interrupt input pin (INT20 to INT27) for which interruptinput has been enabled by the IE20 to IE27 bits outputs an IRQA interrupt request to the CPU.

Figure 11.6-2 "External interrupt 2 (INT20) operation" shows the operation of external interruptcircuit 2 (using the INT20 pin).

Figure 11.6-2 External interrupt 2 (INT20) operation

Note:

The states of the external interrupt pins can be read directly from the port data register(PDR0) even when used as external interrupt inputs.


EIF2 IF20

EIE2 IE27 IE26 IE20IE21IE22IE23IE24IE25

DDR0

: Used bit: Bit that is set to 0 when the corresponding pin is used

Input waveform to the INT20 pin

Interrupt handling routine operation in response to IRQA

EIF2 IF20(same as IRQA state)

EIE2 IE20

PDR0 bit0

Interrupt handling Interrupt handling

Cleared by the interrupt processing routine

External interrupt input enabled

Can be read at any timing

RETI RETI

244

11.7 Sample Programs for External Interrupt Circuit 2

11.7 Sample Programs for External Interrupt Circuit 2

This section shows a sample program for external interrupt circuit 2.

Sample programs for external interrupt circuit 2

Program specification

Generates an interrupt upon detection of an L level signal that is input to the INT20 pin.

Coding example

DDR3 EQU 0001H ;Address of the port data direction register EIE2 EQU 0032H ;Address of the external interrupt 2 control register 1EIF2 EQU 0033H ;Address of the external interrupt 2 flag register

IF20 EQU EIF2:0 ;External interrupt request flag bit definitionILR3 EQU 007EH ;Address of the interrupt level set register

INT_V DSEG ABS ;[DATA SEGMENT] ORG 0FFE6H IRQA DW WARI ;Interrupt vector settingINT_V ENDS ;------Main program----------------------------------------------- CSEG ;[CODE SEGMENT] ;Assume stack pointer (SP) or other registers are already initialized. : ; CLRI ;Interrupts disabled CLRB IF20 ;External interrupt request flag cleared MOV ILR3,#11101111B ;Setting interrupt level to 2. MOV DDR0,#00000000B ;Setting the INT20 pin as an input MOV EIE2,#00000001B ;External interrupt input of the INT20 pin enabled SETI ;Interrupts enabled :;------Interrupt program--------------------------------------------WARI MOV EIE2,#00000000B ;External interrupt input of the INT20 pin disabled CLRB IF20 ;External interrupt request flag cleared PUSHW A XCHW A,T PUSHW A : User processing

245


: POPW A XCHW A,T POPW A RETI ENDS ;------------------------------------------------------------------- END

246

CHAPTER 12 WATCH PRESCALER

This chapter describes the functions and operation of the watch prescaler.

12.1 "Overview of the Watch Prescaler"

12.2 "Structure of the Watch Prescaler"

12.3 "Watch Prescaler Control Register (WPCR)"

12.4 "Watch Prescaler Interrupt"

12.5 "Operation of the Watch Prescaler"

12.6 "Notes on Using the Watch Prescaler"

12.7 "Watch Prescaler Program Example"

247


12.1 Overview of the Watch Prescaler

The watch prescaler is a 15-bit free-run counter which counts up on the sub-clock produced by the clock generator. The watch prescaler has an interval timer function with four available interval times.The watch prescaler is also used to generate the oscillation stabilization delay time for the sub-clock and to supply the operating clock for the watchdog timer and other blocks.

Interval timer function (watch interrupt)

The interval timer function uses the sub-clock as its count clock and repeatedly generatesinterrupts at fixed time intervals.

• A divided output for the interval timer of the watch prescaler generates interrupts.

• The divided output (interval time) used for the interval timer can be selected from fouroptions.

• The counter of the watch prescaler can be cleared.

Table 12.1-1 "Watch prescaler interval times" lists the interval times for the watch prescaler.

Caution:

The watch prescaler is not available if a single-clock system is selected as an option setting.

Table 12.1-1 Watch prescaler interval times

Sub-clock period Interval time

1/FCL(30.5 µs approx.)

210/FCL (31.25 ms)

213/FCL (0.25 s)

214/FCL (0.50 s)

215/FCL (1.00 s)

FCL: Sub-clock source oscillationThe figures in parentheses () are the values when the sub-clock source oscillation is 32.768 kHz.

248

12.1 Overview of the Watch Prescaler

Clock supply function

The clock supply function of the watch prescaler supplies the timer output used to generate theoscillation stabilization delay time for the sub-clock (one available setting) and the clock for thewatchdog timer and buzzer output (three available settings).

Table 12.1-2 "Clocks supplied by the watch prescaler" lists the periods of the clocks suppliedfrom the watch prescaler to the various peripherals.

Note:

As the period of the oscillation is unstable immediately after oscillation starts, the listedoscillation stabilization delay time is a guide only.

Table 12.1-2 Clocks supplied by the watch prescaler

Sub-clock supply destination Sub-clock period Remarks

Sub-clock oscillation stabilization delay time 215/FCL (1.00 s)

Do not change to sub-clock mode during the oscillation stabilization delay time.

Watchdog timer214/FCL (0.50 s)

The count-up clock for the watchdog timer

Buzzer output 23/FCL to 25/FCL(Approx. 0.24 ms to approx. 0.98 ms)

See Chapter 9 "BUZZER OUTPUT".

FCL: Sub-clock source oscillationThe figures in parentheses ( ) are the values when the sub-clock source oscillation is 32.768 kHz.

249


12.2 Structure of the Watch Prescaler

The watch prescaler consists of the following four blocks.• Watch prescaler counter• Counter clear circuit• Interval timer selector• Watch prescaler control register (WPCR)

Block diagram of watch prescaler

Figure 12.2-1 Block diagram of watch prescaler

Watch prescaler counter

This is a 15-bit up-counter which uses the sub-clock source oscillation as its count clock.


Clears the counter when WCLR = 0 is set in the WPCR register, when the device switches tosub-stop mode (STBC:STP = 1), or when a power-on reset (option) occurs.

Interval timer selector

This circuit selects one of the four divided outputs of the watch prescaler counter to use for theinterval timer and generates an interrupt on the trailing edge of the selected divided output.

FCL: Sub-clock source oscillationThe figures in parentheses ( ) are the values when the sub-clock source oscillation is 32.768 kHz.

×21

WCLRWIEWIF WS1 WS0


Inte

rval

tim

er s

elec

tor

10 32 54 76 8 109 1211 1413

Power-on resetStop mode activation(in sub-clock mode)

FCL

Watchdog timer clear

To oscillation stabilization delay time selector in clock controller

(0.25 s)(0.5 s)

(1.0 s)

(31.25 ms)

Watch interruptIRQ7

To buzzer outputWatch prescaler counter

To watchdog timer

Watch prescaler control register (WPCR)

×22 ×23 ×24 ×25 ×26 ×27 ×28 ×29 ×211 ×212 ×213 ×214 ×215×210

250

12.2 Structure of the Watch Prescaler


Used to select the interval time, clear the counter, control interrupts, and check the status.

251


12.3 Watch Prescaler Control Register (WPCR)

The watch prescaler control register (WPCR) is used to select the interval time, clear the counter, control interrupts, and check the status.


Figure 12.3-1 Watch prescaler control register (WPCR)

WIE

0

1

WS1

0

0

1

1

210/FCL

213/FCL

214/FCL

215/FCL

WS0

0

1

0

1


0 0 0 BH

Address

00XXX000B

Initial value

WS0 WCLRWS1

R/W R/W R/WR/WR/W

WIE

Disable output of interrupt requests.

Enable output of interrupt requests.

WIFWatch interrupt request flag bit

No interval interrupt

Interval interrupt present

Clear this bit.0

1

Interval time select bit for the watch interrupt

Read

FCL : Sub-clock source oscillation

WIF

R/W : Readable and writable- : UnusedX : Undefined

: Initial value

WCLRWatch prescaler clear bit

0

1

Clear the watch prescaler.

No change. No other effect.Always read as "1".

Read Write

Write



252

12.3 Watch Prescaler Control Register (WPCR)

Table 12.3-1 Function of each watch prescaler control register (WPCR) bit

Bit Description

bit7 WIF: Watch interrupt request flag bit

• This bit is set to "1" on the trailing edge of the divided output selected for the interval timer.

• An interrupt request is output if this bit and the interrupt request enable bit (WIE) are "1".

• Writing "0" clears the bit. Writing "1" does not change the bit value and has no other effect.

bit6 WIE:Interrupt request enable bit

This bit enables or disables output of interrupt requests to the CPU. An interrupt request is output if both this bit and the watch interrupt request flag bit (WIF) are "1".

bit5bit4bit3

Unused bit • The read values are undefined.• Writing has no effect on operation.

bit2bit1

WS1, WS0:Interval time select bits for the watch interrupt

• These bits select the period of the interval timer.• These bits specify the bit (divided output) of the watch prescaler

counter to use for the interval timer.• Four different interval times are available.

bit0 WCLR:Watch prescaler clear bit

• This bit clears the counter of the watch prescaler.• Writing "0" to this bit clears the counter to "0000H". Writing "1" does

not change the bit value and has no other effect.Note:

Reading the bit always returns "1".

253


12.4 Watch Prescaler Interrupt

The watch prescaler outputs an interrupt request on the trailing edge of the selected divided output (interval timer function).

Interrupts during the interval timer function (watch interrupt)

The counter of the watch prescaler counts up on the source oscillation of the sub-clock. If thedevice is not in main-stop mode, the watch interrupt request flag bit is set to "1" (WPCR:WIF =1) after the specified interval timer time has elapsed. An interrupt request (IRQ7) is output tothe CPU if the interrupt request enable bit is enabled (WPCR:WIE = 1) at this time. Write "0" tothe WIF bit in the interrupt processing routine to clear the interrupt request. Note that the WIFbit is set to "1" on the trailing edge of the specified divided output, regardless of the value of theWIE bit.

Caution:

When enabling interrupts after a reset (WIE = 1), always clear the WIF bit (WIF = 0) at thesame time.

Note:

• An interrupt request is generated immediately if the WIE bit is switched from disabled toenabled (0 --> 1) when the WIF bit is "1".

• The WIF bit is not set if an overflow occurs on the selected bit at the same time that thecounter is cleared (WPCR:WCLR = 0).

Oscillation stabilization delay time and watch interrupt

If you set an interval time that is shorter than the oscillation stabilization delay time for the sub-clock, a watch interrupt request from the watch prescaler (WPCR:WIF = 1) will occur whenwaking up from sub-stop mode via an external interrupt. In this case, disable watch prescalerinterrupts (WPCR:WIE = 0) before switching to sub-stop mode.

Register and vector table for the watch prescaler interrupt

Table 12.4-1 "Register and vector table for the watch prescaler interrupt" lists the register andvector table for the watch prescaler interrupt.


Table 12.4-1 Register and vector table for the watch prescaler interrupt



IRQ7 ILR2 (007DH) L71 (bit7) L70 (bit6) FFECH FFEDH

254

12.5 Operation of the Watch Prescaler

12.5 Operation of the Watch Prescaler

The watch prescaler has an interval timer function and a clock supply function.

Operation of the interval timer function (watch prescaler)

Figure 12.5-1 "Interval timer function settings" shows the settings required for operating thewatch prescaler as an interval timer.

Figure 12.5-1 Interval timer function settings

If the sub-clock is oscillating, the 15-bit counter of the watch prescaler counts up continuouslyusing the sub-clock as its count clock.

Clearing the counter (WCLR = 0) restarts counting from "0000H". Counting also restarts from"0000H" after the count reaches "7FFFH". During counting, and if the device is not in main-stopmode, the watch interrupt request flag bit (WIF) is set to "1" each time a trailing edge occurs onthe divided output selected for the interval timer. In other words, watch interrupt requests aregenerated at the selected interval relative to the time when the counter was cleared.

Operation of the clock supply function

The watch prescaler is also used as a timer to supply the oscillation stabilization delay time forthe sub-clock. The oscillation stabilization delay time for the sub-clock begins when the watch

prescaler starts to count up from zero, and ends when a trailing edge occurs on the MSB (215/FCL, FCL: sub-clock source oscillation).

The watch prescaler supplies clocks to the watchdog timer and buzzer output. Clearing thecounter of the watch prescaler has an effect on the operation of the buzzer output. Also, if theoutput of the watch prescaler is selected for the watchdog timer counter (WDTC:CS = 1),clearing the watch prescaler also clears the watchdog timer.


WPCR WS0 WCLRWS1

1 00

WIEWIF : Used bit 1 : Set "1". 0 : Set "0".

255


Operation of the watch prescaler

Figure 12.5-2 "Operation of the watch prescaler" shows the counter value for the interval timerfunction operating in sub-clock mode when the device enters sleep mode, when the deviceenters stop mode, and when a counter clear request occurs.

The operation when switching to watch mode is the same as that for switching to sub sleepmode.

Figure 12.5-2 Operation of the watch prescaler

WIF bit

7FFFH

0000H

Counter value

Power-on reset (option)

Interval period

Cleared by the interrupt processing routine

SLP bit(STBC register)

STP bit(STBC register)

Counter cleared(WPCR:WCLR=0)

Cleared by switching to sub-stop mode

Wake-up from sleep mode via IRQ7

WIE bit

Wake-up from stop mode via external interrupt

Sub-clock oscillation stabilization delay time

Sub-clock oscillation stabilization delay time

Sub-sleep

Sub-stop

For the case when the interrupt interval time selection bits in the watch prescaler control register (WPCR:WS1, WS0) are set to "11"(215/FCL)

256

12.6 Notes on Using the Watch Prescaler

12.6 Notes on Using the Watch Prescaler

This section describes points to note when using the watch prescaler.This watch prescaler is not available if a single-clock system is selected as an option setting.

Notes on using the watch prescaler

Notes on setting by using the program

The system cannot return from interrupt processing if the interrupt request flag bit (WPCR:WIF)is "1" and the interrupt request enable bit is enabled (WPCR:WIE = 1). Always clear the WIFbit.

Clearing the watch prescaler

In addition to clearing the watch prescaler using the watch prescaler clear bit (WPCR:WCLR =0), the watch prescaler is also cleared when an oscillation stabilization delay time is required forthe sub-clock.

When the watch prescaler is selected as the count clock for the watchdog timer (WDTC:CS =1), clearing the watch prescaler also clears the watchdog timer.

When used as the timer for the oscillation stabilization delay time

The sub-clock source oscillation is halted at power-on and during sub-stop mode.Consequently, the watch prescaler is used to provide an oscillation stabilization delay time forthe sub-clock when the oscillator starts operating.

Do not switch from main clock mode to sub-clock mode while the oscillation stabilization delay isstill in progress for the sub-clock, for example, at power-on.

The oscillation stabilization delay time for the sub-clock is fixed.

See Section 3.6.5 "Oscillation stabilization delay time" for more information.

Notes on the watch interrupt

The count operation continues on the watch prescaler during main-stop mode but the watchinterrupt (IRQ7) is not generated.

Notes on peripheral functions which receive a clock from the watch prescaler

As the output starts from the initialized state when the counter of the watch prescaler is cleared,the length of the "H" level on the clocks supplied from the watch prescaler may be shortenedand the "L" level lengthened by up to one half the period.

Output of the clock to the watchdog timer also starts from the initialized state. However, as thecounter of the watchdog timer is cleared at the same time, the watchdog timer operates underits normal period.

Figure 12.6-1 "Effect on the buzzer output of clearing the watch prescaler" shows the effect onthe buzzer output of clearing the watch prescaler.

257


Figure 12.6-1 Effect on the buzzer output of clearing the watch prescaler

Counter value001FH

0010H

0000H

Counter cleared by the program (WPCR:WCLR=0)

Clock supplied to the buzzer output

For the case when "101" is set in the buzzer selection bits of the buzzer register (BZCR:BZ2, BZ1, BZ0)(Sub-clock source oscillation divided by 32. Outputs 1024 Hz for a 32.768 kHz sub-clock.)

258

12.7 Watch Prescaler Program Example

12.7 Watch Prescaler Program Example

This section describes an example program using the watch prescaler.

Watch prescaler program example


Repeatedly generates watch interrupts at 215/FCL (FCL: sub-clock source oscillation) intervals.The interval time in this case is one second (at 32.768 kHz).

Coding example

WPCR EQU 000BH ;Address of the watch prescaler control register WIF EQU WPCR:7 ;Watch interrupt request flag bit definitionILR2 EQU 007DH ;Address of the interrupt level set register INT_V ENDS ABS ;[DATA SEGMENT] ORG 0FFEAHIRQ7 DW WARI ;Interrupt vector setting INT_V ENDS ;------Main program----------------------------------------------- CSEG ;[CODE SEGMENT] ;Assume stack pointer (SP), etc., are already initialized. : CLRI ;Disable interrupts. MOV ILR2,#10111111B ;Set interrupt level to 2. MOV WPCR,#01000110B ;Clear interrupt request flag bit, enable output of interrupt requests, select 215/FCL, and clear watch prescaler. SETI ;Enable interrupts. :;------Interrupt program--------------------------------------------WARI CLRB WIF ;Clear interrupt request flag. PUSHW A XCHW A,T PUSHW A : User processing : POPW A XCHW A,T POPW A RETI ENDS ;------------------------------------------------------------------- END

259


260

CHAPTER 13 DTMF GENERATOR

This chapter describes the functions and operation of the DTMF generator.

13.1 "Overview of the DTMF Generator"

13.2 "Structure of the DTMF Generator"

13.3 "DTMF Generator Pin"

13.4 "DTMF Generator Registers"

13.5 "Operation of the DTMF Generator"

13.6 "DTMF Generator Program Example"

261


13.1 Overview of the DTMF Generator

The DTMF generator is a dialing tone generation circuit suitable for telephony and related equipment. The circuit can continuously output the full set of ITU-T (formerly CCITT) tones ("0" to "9", "*", "#", and "A" to "D").

DTMF generator functions

• The circuit generates dialing tone signals suitable for telephony and related equipment andoutputs the signals from the DTMF pin.

• DTMF signals can be output continuously (single tone output is also supported).

• All ITU-T (formerly CCITT) tones recommended are available.

• The standard DTMF signals can be generated only when using a 3.58 MHz or 7.16 MHzmain clock source oscillation.

• Table 13.1-1 "Correspondence between setting value and output frequency (for a 3.579545MHz main clock source oscillation)" lists the correspondence between the setting value andoutput frequency. Table 13.1-2 "Frequency tolerance from standard frequency" lists thefrequency tolerance from the standard frequency.

Table 13.1-1 Correspondence between setting value and output frequency (for a 3.579545 MHz main clock source oscillation)

Dial numberRow tone Column tone

ROW Frequency (Hz) COL Frequency (Hz)

1 ROW1 696.95 COL1 1209.31

2 ROW1 696.95 COL2 1335.65

3 ROW1 696.95 COL3 1476.71

4 ROW2 770.13 COL1 1209.31

5 ROW2 770.13 COL2 1335.65

6 ROW2 770.13 COL3 1476.71

7 ROW3 852.27 COL1 1209.31

8 ROW3 852.27 COL2 1335.65

9 ROW3 852.27 COL3 1476.71

0 ROW4 940.99 COL1 1335.65

* ROW4 940.99 COL2 1209.31

# ROW4 940.99 COL3 1476.71

A ROW1 696.95 COL4 1633.01

B ROW2 770.13 COL4 1633.01

C ROW3 852.27 COL4 1633.01

D ROW4 940.99 COL4 1633.01

262

13.1 Overview of the DTMF Generator

Table 13.1-2 Frequency tolerance from standard frequency

Standard frequency(ITU-T recommendations)

DTMF output frequency(*1)

Frequency tolerance(*1)

ROW1 697Hz 696.95Hz -0.01%

ROW2 770Hz 770.13Hz +0.02%

ROW3 852Hz 852.27Hz +0.03%

ROW4 941Hz 940.99Hz -0.01%

COL1 1209Hz 1209.31Hz +0.03%

COL2 1336Hz 1335.65Hz -0.03%

COL3 1477Hz 1476.71Hz -0.02%

COL4 1633Hz 1633.01Hz +0.01%

*1 For a 3.579545 MHz main clock source oscillation

263


13.2 Structure of the DTMF Generator

The DTMF generator consists of the following nine blocks.• Voltage data addition circuit• COL-stage waveform generation circuit• ROW-stage waveform generation circuit• ROW/COL decoder• Frequency divider circuit• Selector• Control signal generator• DTMF control register (DTMC)• DTMF data register (DTMD)

Block diagram of DTMF generator

Figure 13.2-1 Block diagram of DTMF Generator

Voltage data adder

Adds the column and row tone signals and outputs the dialing tone.

COL-stage wave generator

Generates the column tone signal.

Internal data bus

Internal data bus

22/FCH Frequency divider circuit

Control signal generator

(DTMD)

(DTMC)

DTMFFrequency selection

Frequency selection

FCH: Main clock source oscillation

Count clock

COL-stage wave generator

Voltage data adder

ROW-stage wave generator

ROW/COL decoder

Selector

Clock

Dial data

Pin

4

DDAT3 DDAT1DDAT0 DDAT2

CSEL RDIS OUTE CDIS

*1 This bit is present only in the MB89170A series. The bit is unused on the MB89170 series.

(*1)

DTMF data register

DTMF control register

264

13.2 Structure of the DTMF Generator

ROW-stage wave generator

Generates the row tone signal.

ROW/COL decoder

Selects the frequencies to generate based on the DTMD data.

Frequency divider circuit

Divides the main clock to produce the clock used to operate the DTMF generator.

Selector

Selects the operating clock for the DTMF generator.

Control signal generator

Controls output of the column tone and row tone.

DTMF control register (DTMC)

The DTMC enables or disables output of the column and row tones, enables or disables outputof the DTMF signal, and selects the frequency being used for the main clock source oscillation.

DTMF data register (DTMD)

The DTMD specifies which dialing tone to output. The data in this register selects thefrequencies at which to generate the column and row tones and determines the output DTMFsignal.

265


13.3 DTMF Generator Pin

This section describes the DTMF generator pin and the pin block diagram.

DTMF generator pin

The DTMF generator pin is the DTMF pin.

This pin is used exclusively as the DTMF output.

Block diagram of DTMF generator pin

Figure 13.3-1 Block diagram of DTMF pin

Pin

DTMFOPAMP

From voltage data addition circuit

266

13.4 DTMF Generator Registers


This section describes the DTMF generator registers.

DTMF generator registers

Figure 13.4-1 DTMF pin registers


0 0 2 1H

Address

XXXX0000B

Initial value


0 0 2 0H

Address

XXXX0000B

Initial value

CSEL RDIS OUTECDIS

R/W R/WR/WR/W

R/W R/WR/WR/W

DTMC (DTMF control register)

DTMD (DTMF data register)

DDAT3 DDAT1 DDAT0DDAT2

R/W: Readable and writable -: Unused X: Undefined


*2 The initial value on the MB89170 series is "XXXXX000B".

*1

*2

267


13.4.1 DTMF control register (DTMC)

The DTMF control register is used to enable or disable output of the column and row tones, enable or disable output of the DTMF signal, and select the frequency being used for the main clock source oscillation.

DTMF control register (DTMC)

Figure 13.4-2 DTMF control register (DTMC)

OUTE01

DTMF output control bit


0 0 2 0H

Address

XXXX0000B

Initial value

CSEL RDIS OUTECDIS

R/W R/WR/WR/W*1

*2

Disable DTMF signal outputEnable DTMF signal output

RDIS01

Row tone generation control bitEnable row tone generationDisable row tone generation

CDIS01

Column tone generation control bitEnable column tone generationDisable column tone generation

CSEL01

Frequency selection bitMain clock source oscillation = 3.58 MHzMain clock source oscillation = 7.16 MHz


*2 The initial value on the MB89170 series is "XXXXX000B".

R/W: Readable and writable-: UnusedX: Undefined

268


Table 13.4-1 Function of each DTMF control register (DTMC) bit

Bit Description

bit7bit6bit5bit4


bit3 CSEL:Frequency select bit

• This bit selects the operating clock of the DTMF generator. Set the frequency being used for the main clock source oscillation.

• This bit is present only in the MB89170A series.Caution:

The standard DTMF signals can be generated only when using a 3.58 MHz or 7.16 MHz (A series only) main clock source oscillation.

bit2 CDIS:Column tone generation control bit

• This bit enables or disables generation of the column tone signal.• The column tone is generated when this bit is "0" and not generated

when this bit is "1".

bit1 RDIS:Row tone generation control bit

• This bit enables or disables generation of the row tone signal.• The row tone is generated when this bit is "0" and not generated

when this bit is "1".

bit0 OUTE:DTMF output control bit

• This bit enables or disables output of the DTMF signal.• The DTMF signal is output when this bit is "1" and not output when

this bit is "0".

269


13.4.2 DTMF data register (DTMD)

The DTMF data register specifies which dialing tone to output.

DTMF data register (DTMD)

Figure 13.4-3 DTMF data register (DTMD)


0 0 2 1H

Address

XXXX0000B

Initial value

R/WR/W

DDAT0DDAT1DDAT2DDAT3

R/WR/W

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 11 0 1 01 1 0 01 1 0 11 1 1 01 1 1 10 0 0 0

ROW1ROW1ROW1

Row toneFrequency (Hz) Frequency (Hz)

DTMF data register (DTMD)DDAT0DDAT1DDAT2DDAT3

ROW2ROW2ROW2ROW3ROW3ROW3ROW4ROW4ROW4ROW1ROW2ROW3ROW4

696.95696.95696.95770.13770.13770.13852.27852.27852.27940.99940.99940.99696.95770.13852.27940.99

Column tone

COL1COL2

COL2

COL3

COL1ROW COL

COL3

COL2COL1

COL2

COL3COL4COL4

COL1

COL3

COL4COL4

1209.31

1209.31

1335.65

1335.65

1476.71

1476.711209.31

1209.31

1335.65

1335.651476.71

1476.71

1633.011633.01

1633.011633.01

Dial number

1

32

4

65

7

98

0

A

CD

B

R/W: Readable and writable- : UnusedX: Undefined

270

13.5 Operation of the DTMF Generator

13.5 Operation of the DTMF Generator

This DTMF generator can generate dialing tone signals.

Operation of the DTMF generator

To operate the DTMF generator, the following settings are required:

Figure 13.5-1 DTMF generator settings

Enabling DTMF signal output outputs the dialing tone set in the DTMF data register (DTMD)from the DTMF pin.

Caution:

If the mode is switched to stop mode or watch mode when DTMF signal output is enabled(OUTE = 1), the DTMF pin outputs the value set immediately before the mode switch as itwas, and consumes power at all times.


DTMC

DTMD

: Used bit 1 : Set "1" 0 : Set "0"

DDAT0DDAT1DDAT2DDAT3

OUTERDISCDISCSEL

(*1)

*1 Setting is required only on the MB89170A series.

271


13.6 DTMF Generator Program Example

This section describes an example program using the DTMF generator.

DTMF generator program example


Generate the dialing tone for dial number "7" (row tone: ROW3 852.27 MHz, column tone:COL1 1209.31 MHz) for a main clock source oscillation of 3.58 MHz.

Coding example

DTMC EQU 0020H ;Address of the DTMF control register DTMD EQU 0021H ;Address of the DTMF data register

CSEL EQU DTMC:3 ;Frequency selection bit definition CDIS EQU DTMC:2 ;Column tone generation control bit definition RDIS EQU DTMC:1 ;Row tone generation control bit definitionOUTE EQU DTMC:3 ;DTMF output control bit definition ;------Main program----------------------------------------------- CSEG ;[CODE SEGMENT] : MOV DTMD,#00000111B ;Set dial number "7" in the DTMF data register. CLRB CSEL ;Set the frequency select bit for a 3.58 MHz main clock source oscillation. CLRB CDIS ;Enable generation of the column tone. CLRB RDIS ;Enable generation of the row tone. SETB OUTE ;Enable DTMF output. : ENDS ;------------------------------------------------------------------- END

272

APPENDIX

This appendix includes I/O maps, instruction lists, and other information.

APPENDIX A "I/O MAP"

APPENDIX B "INSTRUCTION SUMMARY"

APPENDIX C "MASK OPTIONS"

APPENDIX D "PROM PROGRAMMING"

APPENDIX E "PIN STATES FOR THE MB89170/170A/170L SERIES"

273

APPENDIX A I/O MAP

APPENDIX A I/O MAP

Table A-1 "I/O map for the MB89170/170A series " and Table A-2 "I/O map for the MB89170L series " list the addresses assigned to the registers for the internal peripheral functions of the MB89170/170A/170L series.

I/O map

Table A-1 I/O map for the MB89170/170A series

AddressRegister

abbreviationRegister name Read/write Initial value

00H PDR0 Port 0 data register R/W XXXXXXXXB

01H DDR0 Port 0 direction register W 00000000B



04H PDR2 Port 2 data register R/W 00000000B

05H(Vacant area) XXXXXXXXB

06H

07H SYCC System clock control register R/W XXXMM100B

08H STBC Standby control register R/W 00010XXXB

09H WDTC Watchdog control register R/W 0XXXXXXXB

0AH TBTC Timebase timer control register R/W 00XXX000B

0BH WPCR Watch prescaler control register R/W 00XXX000B

0CH PDR3 Port 3 data register R/W XXXXXXXXB

0DH DDR3 Port 3 direction register R/W 00000000B

0EH PDR4 Port 4 data register R/W XXX11111B

0FH BZCR Buzzer register R/W XXXXX000B

10Hto

17H

(Vacant area) XXXXXXXXB

18H T2CR Timer 2 control register R/W X000XXX0B


1AH T2DR Timer 2 data register R/W XXXXXXXXB

1BH T1DR Timer 1 data register R/W XXXXXXXXB

1CH SMR Serial mode register R/W 00000000B

274

APPENDIX A I/O MAP

1DH SDR Serial data register R/W XXXXXXXXB

1EH(Vacant area) XXXXXXXXB

1FH

20H DTMC DTMF control register R/W

MB89170 seriesXXXXX000B

MB89170A seriesXXXX0000B

21H DTMD DTMF data register R/W XXXX0000B

22H (Vacant area) XXXXXXXXB

23H EIC1 External interrupt 1 control register 1 R/W 00000000B

24H EIC2 External interrupt 1 control register 2 R/W XXXX0000B

25Hto

31H


32H EIE2 External interrupt 2 control register R/W 00000000B

33H EIF2 External interrupt 2 flag register R/W XXXXXXX0B

34Hto

7BH


7CH ILR1 Interrupt level set register 1 W 11111111B

7DH ILR2 Interrupt level set register 2 W 11111111B

7EH ILR3 Interrupt level set register 3 W 11111111B

7FH (Vacant area) XXXXXXXXB

Table A-1 I/O map for the MB89170/170A series (Continued)

AddressRegister


275

APPENDIX A I/O MAP

Table A-2 I/O map for the MB89170L series

AddressRegister






04H PDR2 Port 2 data register R/W 00000000B

05H(Vacant area) XXXXXXXXB

06H

07H SYCC System clock control register R/W XXXMM100B

08H STBC Standby control register R/W 00010XXXB

09H WDTC Watchdog control register R/W 0XXXXXXXB

0AH TBTC Timebase timer control register R/W 00XXX000B

0BH (vacant area) XXXXXXXXB

0CH PDR3 Port 3 data register R/W XXXXXXXXB

0DH DDR3 Port 3 direction register R/W 00000000B

0EH PDR4 Port 4 data register R/W XXX11111B

0FH BZCR Buzzer register R/W XXXXX000B

10Hto

17H

(vacant area) XXXXXXXXB



1AH T2DR Timer 2 data register R/W XXXXXXXXB

1BH T1DR Timer 1 data register R/W XXXXXXXXB

1CH SMR Serial mode register R/W 00000000B

1DH SDR Serial data register R/W XXXXXXXXB

1EH(Vacant area) XXXXXXXXB

1FH


21H (Vacant area) XXXXXXXB


23H EIC1 External interrupt 1 control register 1 R/W 00000000B

24H EIC2 External interrupt 1 control register 2 R/W XXXX0000B

276

APPENDIX A I/O MAP

Read/write column symbols

• R/W: Read/write possible

• R: Read only

• W: Write only

Initial value column symbols

• 0: The initial value of this bit is 0.

• 1: The initial value of this bit is 1.

• X: The initial value of this bit is undefined.

• M: The initial value of this bit is determined by a mask option.

Caution:

• Do not use the vacant areas.

• With the MB89170L series, the areas corresponding to the WPCR register (0BH), DTMCregister (20H), and DTMD register (21H) are vacant.

25Hto

31H


32H EIE2 External interrupt 2 control register R/W 00000000B

33H EIF2 External interrupt 2 flag register R/W XXXXXXX0B

34Hto

7BH


7CH ILR1 Interrupt level set register 1 W 11111111B

7DH ILR2 Interrupt level set register 2 W 11111111B

7EH ILR3 Interrupt level set register 3 W 11111111B

7FH (Vacant area) XXXXXXXXB

Table A-2 I/O map for the MB89170L series (Continued)

AddressRegister


277

APPENDIX B INSTRUCTION SUMMARY


Appendix B describes the instructions used by the F 2MC-8L.

B.1 "Summary of F2MC-8L instructions"

B.2 "Addressing"

B.3 "Special Instructions"

B.4 "Bit Manipulation Instructions (SETB, CLRB)"

B.5 "F2MC-8L Instructions"

B.6 "Instruction Map"

278


B.1 Summary of F 2MC-8L instructions

The F2MC-8L supports 140 types of instructions.

Summary of F2MC-8L instructions

The F2MC-8L has 140 1-byte machine instructions (256-byte instruction map). An instructioncode consists of an instruction and zero or more operands that follow.

Figure B.1-1 "Relationship between the instruction codes and the instruction map" shows therelationship between the instruction codes and the instruction map.

Figure B.1-1 Relationship between the instruction codes and the instruction map

• The instructions are classified into four types: transfer, arithmetic, branch, and other.

• A variety of addressing methods is available. One of ten addressing modes can be selecteddepending on the selected instruction and specified operand(s).

• Bit manipulation instructions are provided. They can be used for read-modify-writeoperations.

• Some instructions are used for special operations.

0 to 2 bytes, which are assigned depending on the instruction

1 byte

Instruction code Machine instruction Operand Operand

Higher 4 bits [Instruction map]

Low

er 4

bits

279


Symbols used with instructions

Table B.1-1 "Symbols in the instruction list" lists the symbols used in the instruction codedescriptions in Appendix B.

Table B.1-1 Symbols in the instruction list

Symbol Meaning

dir Direct address (8 bits)

off Offset (8 bits)

ext Extended address (16 bits)

#vct Vector table number (3 bits)

#d8 Immediate data (8 bits)

#d16 Immediate data (16 bits)

dir:16 Bit direct address (8 bits:3 bits)

rel Branch relative address (8 bits)

@ Register indirect addressing (examples: @A, @IX, @EP)

A Accumulator (8 or 16 bits, which are determined depending on the instruction being used)

AH Higher 8 bits of the accumulator (8 bits)

AL Lower 8 bits of the accumulator (8 bits)

T Temporary accumulator (8 or 16 bits, which are determined depending on the instruction being used)

TH Higher 8 bits of the temporary accumulator (8 bits)

TL Lower 8 bits of the temporary accumulator (8 bits)

IX Index register (16 bits)

EP Extra pointer (16 bits)

PC Program counter (16 bits)

SP Stack pointer (16 bits)

PS Program status (16 bits)

dr Either accumulator or index register (16 bits)

CCR Condition code register (8 bits)

RP Register bank pointer (5 bits)

Ri General-purpose register (8 bits, i = 0 to 7)

X X is immediate data (8 or 16 bits, which are determined depending on the instruction being used).

(X) The content of X is to be accessed (8 or 16 bits, which are determined depending on the instruction being used).

((X)) The address indicated by the X is to be accessed (8 or 16 bits, which are determined depending on the instruction being used).

280


Items in the instruction list

Table B.1-2 Items in the instruction list

Item Description

MNEMONIC This column shows the instruction in assembly language.

to This column shows the number of cycles required by the instruction (instruction cycle count).

# This column shows the number of bytes for the instruction.

Operation This column shows the operation performed by the instruction.

TL, TH, AH These columns indicate a change in the contents of TL, TH, and AH (automatic transfer from A to T) upon the execution of the instruction.The meanings of symbols in each column are as follows:• "-" indicates that no change is made.• "dH" indicates the higher 8 bits of data in the operation column.• "AL" and "AH" indicate that the contents of AL and AH immediately before the execution of

the instruction are set.• "00" indicates that 00 is set.

N, Z, V, C These columns indicate whether their respective flags are changed upon the execution of the instruction.A plus (+) sign indicates that the instruction changes the corresponding flag.

OP CODE This column shows the operation code(s) of the instruction. When the instruction uses two or more operation codes, the following notation is used:[Example] 48 to 4F: This represents from 48 to 4F.

281


B.2 Addressing

The F2MC-8L has the following ten addressing modes:• Direct addressing• Extended addressing• Bit direct addressing• Index addressing• Pointer addressing• General-purpose register addressing• Immediate addressing• Vector addressing• Relative addressing• Inherent addressing

Explanation of addressing

Direct addressing

Direct addressing is indicated by dir in the instruction list. This addressing is used to access thearea between 0000H and 00FFH. In this addressing mode, the higher byte of the address is 00Hand the lower byte is specified by the operand. Figure B.2-1 "Example of direct addressing"shows an example.

Figure B.2-1 Example of direct addressing

Extended addressing

Extended addressing is indicated by ext in the instruction list. This addressing is used to accessthe entire 64-KB area. In this addressing mode, the first operand specifies the higher byte ofthe address, and the second operand specifies the lower byte.

Figure B.2-2 "Example of extended addressing" shows an example.

Figure B.2-2 Example of extended addressing

Bit direct addressing

Bit direct addressing is indicated by dir:b in the instruction list. This addressing is used toaccess a particular bit in the area between 0000H and 00FFH. In this addressing mode, the

MOV 12H, A

4 5H 4 5HA0 0 1 2 H

1 2 3 4H

MOVW A, 1 2 3 4H

5 6 7 8HA5 6H

7 8H1 2 3 5H

282


higher byte of the address is 00H and the lower byte is specified by the operand. The bitposition at the address is specified by the lower three bits of the operation code.

Figure B.2-3 "Example of bit direct addressing" shows an example.

Figure B.2-3 Example of bit direct addressing

Index addressing

Index addressing is indicated by @IX+off in the instruction list. This addressing is used toaccess the entire 64-KB area. In this addressing mode, the address is the value resulting fromsign-extending the contents of the first operand and adding them to IX (index register). FigureB.2-4 "Example of index addressing" shows an example.

Figure B.2-4 Example of index addressing

Pointer addressing

Pointer addressing is indicated by @EP in the instruction list. This addressing is used to accessthe entire 64-KB area. In this addressing mode, the address is contained in EP (extra pointer).Figure B.2-5 "Example of pointer addressing" shows an example.

Figure B.2-5 Example of pointer addressing

General-purpose register addressing

General-purpose register addressing is indicated by Ri in the instruction list. This addressing isused to access a register bank in the general-purpose register area. In this addressing mode,the higher byte of the address is always 01 and the lower byte is specified based on thecontents of RP (register bank pointer) and the lower three bits of the operation code. FigureB.2-6 "Example of general-purpose register addressing" shows an example.

Figure B.2-6 Example of general-purpose register addressing

Immediate addressing

Immediate addressing is indicated by #d8 in the instruction list. This addressing is used when

SETB 34H : 2

X X X X X 1 X X B0 0 3 4H

7 6 5 4 3 2 1 0

2 7 F FH

MOVW A, @IX+5 AH

1 2 3 4HA1 2H

3 4H2 8 0 0 H

2 7 A 5 HIX

2 7 A 5H

MOVW A, @EP

1 2 3 4HA1 2 H

3 4 H2 7 A 6 H

2 7 A 5HEP

0 1 5 6H

MOV A, R 6

ABHAA BH0 1 0 1 0 BRP

283


immediate data is required. In this addressing mode, the operand is used as immediate data.Whether the data is specified in bytes or words is determined by the operation code. FigureB.2-7 "Example of immediate addressing" shows an example.

Figure B.2-7 Example of immediate addressing

Vector addressing

Vector addressing is indicated by vct in the instruction list. This addressing is used to branch toa subroutine address stored in the vector table. In this addressing mode, vct information iscontained in the operation codes, and the corresponding table addresses are created as shownin Table B.2-1 "Vector table addresses corresponding to vct".

Figure B.2-8 "Example of vector addressing" shows an example.

Figure B.2-8 Example of vector addressing

Relative addressing

Relative addressing is indicated by rel in the instruction list. This addressing is used to branchto within the area between the address 128 bytes higher and that 128 bytes lower relative to theaddress contained in the PC (program counter). In this addressing mode, the result of a signedaddition of the contents of the operand to the PC is stored in the PC. Figure B.2-9 "Example of

MOV A, #56H

5 6 HA

Table B.2-1 Vector table addresses corresponding to vct

#vct Vector table address (higher address:lower address of branch destination)

0 FFC0H : FFC1H

1 FFC2H : FFC3H

2 FFC4H : FFC5H

3 FFC6H : FFC7H

4 FFC8H : FFC9H

5 FFCAH : FFCBH

6 FFCCH : FFCDH

7 FFCEH : FFCFH

F F C AH

CALLV #5

F E D CHPCF EH

D CH F F C BH

(Conversion)

284


relative addressing" shows an example.

Figure B.2-9 Example of relative addressing

In this example, a branch to the address of the BNE operation code occurs, thus resulting in aninfinite loop.

Inherent addressing

Inherent addressing is indicated as the addressing without operands in the instruction list. Thisaddressing is used to perform the operation determined by the operation code. In thisaddressing mode, different operations are performed via different instructions. Figure B.2-10"Example of inherent addressing" shows an example.

Figure B.2-10 Example of inherent addressing

9 A B AH

BNE F EH

Current PC9 A B CHPrevious PC9ABCH + FFFEH

9 A B DH

NOP

9 A B CH Current PCPrevious PC

285


B.3 Special Instructions

This section describes the special instructions used for other than addressing.

Special instructions

JMP @A

This instruction sets the contents of A (accumulator) to PC (program counter) as the address,and causes a branch to that address. One of the N branch destination addresses is selectedfrom a table, and then transferred to A. The instruction can be executed to perform N-branchprocessing.

Figure B.3-1 "JMP @A" shows a summary of the instruction.

Figure B.3-1 JMP @A

MOVW A, PC

This instruction performs the operation which is the reverse of that performed by JMP @A. Thatis, the instruction stores the contents of PC in A. When the instruction is executed in the mainroutine, so that a specific subroutine is called, whether A contains a predetermined value can bechecked by the subroutine. This can be used to determine that the branch source is not anyunexpected section of the program and to check for program runaway.

Figure B.3-2 "MOVW A, PC" shows a summary of the instruction.

Figure B.3-2 MOVW A, PC

After the MOVW A, PC instruction is executed, A contains the address of the operation code ofthe next instruction, rather than the address of the operation code of MOVW A, PC.Accordingly, Figure B.3-2 "MOVW A, PC" shows that A contains 1234H, which is the address ofthe operation code of the instruction that follows MOVW A, PC.

MULU A

This instruction performs an unsigned multiplication of AL (lower eight bits of the accumulator)and TL (lower eight bits of the temporary accumulator), and stores the 16-bit result in A. Thecontents of T (temporary accumulator) do not change. The contents of AH (higher eight bits ofthe accumulator) and TH (higher eight bits of the temporary accumulator) before execution ofthe instruction are not used for the operation. The instruction does not change the flags, and

1 2 3 4HA

X X X XHPrevious PC

A

Current PC

(Before execution) (After execution)

1 2 3 4H

1 2 3 4H

A AX X X XH

1 2 3 4H 1 2 3 4H

1 2 3 4H

Previous PC Current PC

286


therefore care must be taken when a branch may occur depending on the result of amultiplication.

Figure B.3-3 "MULU" shows a summary of the instruction.

Figure B.3-3 MULU

DIVU A

This instruction divides the 16-bit value in T by the unsigned 8-bit value in AL, and stores the 8-bit result and the 8-bit remainder in AL and TL, respectively. A value of 0 is set to both AH andTH. The contents of AH before execution of the instruction are not used for the operation. Anunpredictable result is produced from data that results in more than eight bits. In addition, thereis no indication of the result having more than eight bits. Therefore, if it is likely that data willcause a result of more than eight bits, the data must be checked to ensure that the result will nothave more than eight bits before it is used.

The instruction does not change the flags, and therefore care must be taken when a branchmay occur depending on the result of a division.

Figure B.3-4 "DIVU A" shows a summary of the instruction.

Figure B.3-4 DIVU A

XCHW A, PC

This instruction swaps the contents of A and PC, resulting in a branch to the address containedin A before execution of the instruction. After the instruction is executed, A contains the addressthat follows the address of the operation code of MOVW A, PC. This instruction is effectiveespecially when it is used in the main routine to specify a table for use in a subroutine.

Figure B.3-5 "XCHW A, PC" shows a summary of the instruction.

Figure B.3-5 XCHW A, PC

After the XCHW A, PC instruction is executed, A contains the address of the operation code ofthe next instruction, rather than the address of the operation code of XCHW A, PC.Accordingly, Figure B.3-5 "XCHW A, PC" shows that A contains 1235H, which is the address ofthe operation code of the instruction that follows XCHW A, PC. This is why 1235H is storedinstead of 1234H.

1 2 3 4H

A

T

1 8 6 0HA

T


1 2 3 4H

5 6 7 8H

1 8 6 2H

A

T

0 0 3 4HA

T


0 0 0 2H

5 6 7 8H

1 2 3 4H

A

PC

1 2 3 5HA

PC


5 6 7 8H

5 6 7 8H

287


Figure B.3-6 "Example of using XCHW A, PC" shows an assembly language example.

Figure B.3-6 Example of using XCHW A, PC

CALLV #vct

This instruction is used to branch to a subroutine address stored in the vector table. Theinstruction saves the return address (contents of PC) in the location at the address contained inSP (stack pointer), and uses vector addressing to cause a branch to the address stored in thevector table. Because CALLV #vct is a 1-byte instruction, the use of this instruction forfrequently used subroutines can reduce the entire program size.

Figure B.3-7 "Example of executing CALLV #3" shows a summary of the instruction.

Figure B.3-7 Example of executing CALLV #3

After the CALLV #vct instruction is executed, the contents of PC saved on the stack area arethe address of the operation code of the next instruction, rather than the address of theoperation code of CALLV #vct. Accordingly, Figure B.3-7 "Example of executing CALLV #3"shows that the value saved in the stack (1232H and 1233H) is 5679H, which is the address ofthe operation code of the instruction that follows CALLV #vct (return address).

MOVW

XCHW

DB

MOVW

A, #PUTSUB

A, PC

'PUT OUT DATA', EOL

A, 1234 H

(Main routine)

XCHW A, EP

PUSHW A

MOV A, @EP

INCW EP

MOV IO, A

CMP A, #EOL

BNE PTS1

POPW A

XCHW A, EP

JMP @A

PUTSUB

PTS1

(Subroutine)

Output table data here

1 2 3 4H

PC

SP

F E D CHPC

SP


1 2 3 2H

5 6 7 8H

1 2 3 2H

1 2 3 3H

X XH

X XH

F EH

D CH

F F C 6H

F F C 7H

1 2 3 2H

1 2 3 3H

5 6H

7 9H

F EH

D CH

F F C 6H

F F C 7H

(-2)

288


B.4 Bit Manipulation Instructions (SETB, CLRB)

Some bits of peripheral function registers include bits that are read by a bit manipulation instruction differently than usual.

Read-modify-write operation

By using these bit manipulation instructions, only the specified bit in a register or RAM locationcan be set to 1 (SETB) or cleared to 0 (CLRB). However, as the CPU operates on data in 8-bitunits, the actual operation (read-modify-write operation) involves a sequence of steps: 8-bitdata is read, the specified bit is changed, and the data is written back to the location at theoriginal address.

Table B.4-1 "Bus operation for bit manipulation instructions" shows bus operation for bitmanipulation instructions.

Read operation upon the execution of bit manipulation instructions

For some I/O ports and for the interrupt request flag bits, the value to be read differs between anormal read operation and a read-modify-write operation.

I/O ports (during a bit manipulation)

From some I/O ports, an I/O pin value is read during a normal read operation, while an outputlatch value is read during a bit manipulation. This prevents the other output latch bits frombeing changed accidentally, regardless of the I/O directions and states of the pins.

Interrupt request flag bits (during a bit manipulation)

An interrupt request flag bit functions as a flag bit indicating whether an interrupt request existsduring a normal read operation. However, 1 is always read from this bit during a bitmanipulation. This prevents the flag from being cleared accidentally by a value of 0 whichwould otherwise be written to the interrupt request flag bit when another bit is manipulated.

Table B.4-1 Bus operation for bit manipulation instructions

CODE MNEMONIC TO Cycle Address bus Data bus RD WR RMW

A0 to A7 CLRB dir:b 4 1 N+1 Dir 0 1 0

2 dir address Data 0 1 1

A8 to AF SETB dir:b 3 dir address Data 1 0 0

4 N+2 Next instruction 0 1 0

289


B.5 F2MC-8L Instructions

Table B.5-1 "Transfer Instructions" to Table B.5-4 "Other instructions" list the

instructions used with the F 2MC-8L.

Transfer instructions

Table B.5-1 Transfer Instructions

No. MNEMONIC ~ # Operation TL TH AH N Z V C OP CODE

1 MOV dir, A 3 2 (dir)<--(A) - - - - - - - 45

2 MOV @IX+off, A 4 2 ((IX)+off)<--(A) - - - - - - - 46

3 MOV ext, A 4 3 (ext)<--(A) - - - - - - - 61

4 MOV @EP, A 3 1 ((EP))<--(A) - - - - - - - 47

5 MOV Ri, A 3 1 (Ri)<--(A) - - - - - - - 48 to 4F

6 MOV A, #d8 2 2 (A)<--d8 AL - - + + - - 04

7 MOV A, dir 3 2 (A)<--(dir) AL - - + + - - 05

8 MOV A, @IX+off 4 2 (A)<--((IX)+off) AL - - + + - - 06

9 MOV A, ext 4 3 (A)<--(ext) AL - - + + - - 60

10 MOV A, @A 3 1 (A)<--((A)) AL - - + + - - 92

11 MOV A, @EP 3 1 (A)<--((EP)) AL - - + + - - 07

12 MOV A, Ri 3 1 (A)<--(Ri) AL - - + + - - 08 to 0F

13 MOV dir, #d8 4 3 (dir)<--d8 - - - - - - - 85

14 MOV @IX+off, #d8 5 3 ((IX)+off)<--d8 - - - - - - - 86

15 MOV @EP, #d8 4 2 ((EP))<--d8 - - - - - - - 87

16 MOV Ri, #d8 4 2 (Ri)<--d8 - - - - - - - 88 to 8F

17 MOVW dir, A 4 2 (dir)<--(AH), (dir+1)<--(AL) - - - - - - - D5

18 MOVW @IX+off, A 5 2 ((IX)+off )<--(AH), ((IX)+off+1)<--(AL)

- - - - - - - D6

19 MOVW ext, A 5 3 (ext)<--(AH), (ext+1)<--(AL) - - - - - - - D4

20 MOVW @EP, A 4 1 ((EP))<--(AH), ((EP)+1)<--(AL)

- - - - - - - D7

21 MOVW EP, A 2 1 (EP)<--(A) - - - - - - - E3

22 MOVW A, #d16 3 3 (A)<--d16 AL AH dH + + - - E4

23 MOVW A, dir 4 2 (AH)<--(dir), (AL)<--(dir+1) AL AH dH + + - - C5

290


Caution:

In automatic transfer to T during byte transfer to A, AL is transferred to TL.

If an instruction has two or more operands, they are assumed to be saved in the orderindicated by MNEMONIC.

24 MOVW A, @IX+off 5 2 (AH)<--((IX)+off), (AL)<--((IX)+off+1)

AL AH dH + + - - C6

25 MOVW A, ext 5 3 (AH)<--(ext), (AL)<--(ext+1) AL AH dH + + - - C4

26 MOVW A, @A 4 1 (AH)<--((A)), (AL)<--((A)+1) AL AH dH + + - - 93

27 MOVW A, @EP 4 1 (AH)<--((EP)), (AL)<--((EP)+1)

AL AH dH + + - - C7

28 MOVW A, EP 2 1 (A)<--(EP) - - dH - - - - F3

29 MOVW EP, #d16 3 3 (EP)<--d16 - - - - - - - E7

30 MOVW IX, A 2 1 (IX)<--(A) - - - - - - - E2

31 MOVW A, IX 2 1 (A)<--(IX) - - dH - - - - F2

32 MOVW SP, A 2 1 (SP)<--(A) - - - - - - - E1

33 MOVW A, SP 2 1 (A)<--(SP) - - dH - - - - F1

34 MOV @A, T 3 1 ((A))<--(T) - - - - - - - 82

35 MOVW @A, T 4 1 ((A))<--(TH), ((A)+1)<--(TL) - - - - - - - 83

36 MOVW IX, #d16 3 3 (IX)<--d16 - - - - - - - E6

37 MOVW A, PS 2 1 (A)<--(PS) - - dH - - - - 70

38 MOVW PS, A 2 1 (PS)<--(A) - - - + + + + 71

39 MOVW SP, #d16 3 3 (SP)<--d16 - - - - - - - E5

40 SWAP 2 1 (AH)<-- -->(AL) - - AL - - - - 10

41 SETB dir:b 4 2 (dir):b <--1 - - - - - - - A8 to AF

42 CLRB dir:b 4 2 (dir):b <--0 - - - - - - - A0 to A7

43 XCH A, T 2 1 (AL)<-- -->(TL) AL - - - - - - 42

44 XCHW A, T 3 1 (A)<-- -->(T) AL AH dH - - - - 43

45 XCHW A, EP 3 1 (A)<-- -->(EP) - - dH - - - - F7

46 XCHW A, IX 3 1 (A)<-- -->(IX) - - dH - - - - F6

47 XCHW A, SP 3 1 (A)<-- -->(SP) - - dH - - - - F5

48 MOVW A, PC 2 1 (A)<--(PC) - - dH - - - - F0

Table B.5-1 Transfer Instructions (Continued)


291


Arithmetic instructions

Table B.5-2 Arithmetic Operation Instructions


1 ADDC A, Ri 3 1 (A)<--(A)+(Ri)+C - - - + + + + 28 to 2F

2 ADDC A, #d8 2 2 (A)<--(A)+d8+C - - - + + + + 24

3 ADDC A, dir 3 2 (A)<--(A)+(dir)+C - - - + + + + 25

4 ADDC A, @IX+off 4 2 (A)<--(A)+((IX)+off)+C - - - + + + + 26

5 ADDC A, @EP 3 1 (A)<--(A)+((EP))+C - - - + + + + 27

6 ADDCW A 3 1 (A)<--(A)+(T)+C - - dH + + + + 23

7 ADDC A 2 1 (AL)<--(AL)+(TL)+C - - - + + + + 22

8 SUBC A, Ri 3 1 (A)<--(A)-(Ri)-C - - - + + + + 38 to 3F

9 SUBC A, #d8 2 2 (A)<--(A)-d8-C - - - + + + + 34

10 SUBC A, dir 3 2 (A)<--(A)-(dir)-C - - - + + + + 35

11 SUBC A, @IX+off 4 2 (A)<--(A)-((IX)+off)-C - - - + + + + 36

12 SUBC A, @EP 3 1 (A)<--(A)-((EP))-C - - - + + + + 37

13 SUBCW A 3 1 (A)<--(T)-(A)-C - - dH + + + + 33

14 SUBC A 2 1 (AL)<--(TL)-(AL)-C - - - + + + + 32

15 INC Ri 4 1 (Ri)<--(Ri)+1 - - - + + + - C8 to CF

16 INCW EP 3 1 (EP)<--(EP)+1 - - - - - - - C3

17 INCW IX 3 1 (IX)<--(IX)+1 - - - - - - - C2

18 INCW A 3 1 (A)<--(A)+1 - - dH + + - - C0

19 DEC Ri 4 1 (Ri)<--(Ri)-1 - - - + + + - D8 to DF

20 DECW EP 3 1 (EP)<--(EP)-1 - - - - - - - D3

21 DECW IX 3 1 (IX)<--(IX)-1 - - - - - - - D2

22 DECW A 3 1 (A)<--(A)-1 - - dH + + - - D0

23 MULU A 19 1 (A)<--(AL)x(TL) - - dH - - - - 01

24 DIVU A 21 1 (A)<--(T)/(AL), MOD -->(T) dL 00 00 - - - - 11

25 ANDW A 3 1 (A)<--(A) (T) - - dH + + R - 63

26 ORW A 3 1 (A)<--(A) (T) - - dH + + R - 73

27 XORW A 3 1 (A)<--(A) (T) - - dH + + R - 53

28 CMP A 2 1 (TL)-(AL) - - - + + + + 12

29 CMPW A 3 1 (T)-(A) - - - + + + + 13

30 RORC A 2 1 - - - + + - + 03C --> A

292


31 ROLC A 2 1 - - - + + - + 02

32 CMP A, #d8 2 2 (A)-d8 - - - + + + + 14

33 CMP A, dir 3 2 (A)-(dir) - - - + + + + 15

34 CMP A, @EP 3 1 (A)-((EP)) - - - + + + + 17

35 CMP A, @IX+off 4 2 (A)-((IX)+off) - - - + + + + 16

36 CMP A, Ri 3 1 (A)-(Ri) - - - + + + + 18 to 1F

37 DAA 2 1 decimal adjust for addition - - - + + + + 84

38 DAS 2 1 decimal adjust for subtraction - - - + + + + 94

39 XOR A 2 1 (A)<--(AL) (TL) - - - + + R - 52

40 XOR A, #d8 2 2 (A)<--(AL) d8 - - - + + R - 54

41 XOR A, dir 3 2 (A)<--(AL) (dir) - - - + + R - 55

42 XOR A, @EP 3 1 (A)<--(AL) ((EP)) - - - + + R - 57

43 XOR A, @IX+off 4 2 (A)<--(AL) ((IX)+off) - - - + + R - 56

44 XOR A, Ri 3 1 (A)<--(AL) (Ri) - - - + + R - 58 to 5F

45 AND A 2 1 (A)<--(AL) (TL) - - - + + R - 62

46 AND A, #d8 2 2 (A)<--(AL) d8 - - - + + R - 64

47 AND A, dir 3 2 (A)<--(AL) (dir) - - - + + R - 65

48 AND A, @EP 3 1 (A)<--(AL) ((EP)) - - - + + R - 67

49 AND A, @IX+off 4 2 (A)<--(AL) ((IX)+off) - - - + + R - 66

50 AND A, Ri 3 1 (A)<--(AL) (Ri) - - - + + R - 68 to 6F

51 OR A 2 1 (A)<--(AL) (TL) - - - + + R - 72

52 OR A, #d8 2 2 (A)<--(AL) d8 - - - + + R - 74

53 OR A, dir 3 2 (A)<--(AL) (dir) - - - + + R - 75

54 OR A, @EP 3 1 (A)<--(AL) ((EP)) - - - + + R - 77

55 OR A, @IX+off 4 2 (A)<--(AL) ((IX)+off) - - - + + R - 76

56 OR A, Ri 3 1 (A)<--(AL) (Ri) - - - + + R - 78 to 7F

57 CMP dir, #d8 5 3 (dir)-d8 - - - + + + + 95

58 CMP @EP, #d8 4 2 ((EP))-d8 - - - + + + + 97

59 CMP @IX+off, #d8 5 3 ((IX)+off)-d8 - - - + + + + 96

60 CMP Ri, #d8 4 2 (Ri)-d8 - - - + + + + 98 to 9F

61 INCW SP 3 1 (SP)<--(SP)+1 - - - - - - - C1

62 DECW SP 3 1 (SP)<--(SP)-1 - - - - - - - D1

Table B.5-2 Arithmetic Operation Instructions (Continued)


C <-- A

293


Branch instructions

Table B.5-3 Branch instructions


1 BZ/BEQ rel 3 2 if Z=1 then PC<--PC+rel - - - - - - - FD

2 BNZ/BNE rel 3 2 if Z=0 then PC<--PC+rel - - - - - - - FC

3 BC/BLO rel 3 2 if C=1 then PC<--PC+rel - - - - - - - F9

4 BNC/BHS rel 3 2 if C=0 then PC<--PC+rel - - - - - - - F8

5 BN rel 3 2 if N=1 then PC<--PC+rel - - - - - - - FB

6 BP rel 3 2 if N=0 then PC<--PC+rel - - - - - - - FA

7 BLT rel 3 2 if V N=1 then PC<--PC+rel - - - - - - - FF

8 BGE rel 3 2 if V N=0 then PC<--PC+rel - - - - - - - FE

9 BBC dir:b, rel 5 3 if (dir:b)=0 then PC<--PC+rel - - - - + - - B0 to B7

10 BBS dir:b, rel 5 3 if (dir:b)=1 then PC<--PC+rel - - - - + - - B8 to BF

11 JMP @A 2 1 (PC)<--(A) - - - - - - - E0

12 JMP ext 3 3 (PC)<--ext - - - - - - - 21

13 CALLV #vct 6 1 vector call - - - - - - - E8 to EF

14 CALL ext 6 3 subroutine call - - - - - - - 31

15 XCHW A, PC 3 1 (PC)<--(A), (A)<--(PC)+1 - - dH - - - - F4

16 RET 4 1 return from subroutine - - - - - - - 20

17 RETI 6 1 return from interrupt - - - restore 30

294


Other instructions

Table B.5-4 Other Instructions


1 PUSHW A 4 1 - - - - - - - 40

2 POPW A 4 1 - - dH - - - - 50

3 PUSHW IX 4 1 - - - - - - - 41

4 POPW IX 4 1 - - - - - - - 51

5 NOP 1 1 - - - - - - - 00

6 CLRC 1 1 - - - - - - R 81

7 SETC 1 1 - - - - - - S 91

8 CLRI 1 1 - - - - - - - 80

9 SETI 1 1 - - - - - - - 90

295


B.6 Instruction Map

Table B.6-1 "F 2MC-8L Instruction Map" shows the F 2MC-8L instruction map.

Instruction map

Table B.6-1 F 2MC-8L Instruction Map

0 1 2 3 4 5 6 7 8 9 A B C D E F

NOP

MUL

U

A

ROLC

A

RORC

A

MO

V

A, #

d8

MO

V

A,

dir

MO

V

A, @

IX+d

MO

V

A, @

EP

MO

V

A

, R0

MO

V

A

, R1

MO

V

A

, R2

MO

V

A

, R3

MO

V

A

, R4

MO

V

A

, R5

MO

V

A

, R6

MO

V

A

, R7

SWAP

DIVU

A

CMP

A

CMPW

A

CMP

A, #

d8

CMP

A

, dir

CMP

A, @

IX+d

CMP

A, @

EP

CMP

A

, R0

CMP

A

, R1

CMP

A

, R2

CMP

A

, R3

CMP

A

, R4

CMP

A

, R5

CMP

A

, R6

CMP

A

, R7

RET

JMP

add

r16

ADDC

A

ADDC

W

A

ADDC

A, #

d8

ADDC

A

, dir

ADDC

A, @

IX+d

ADDC

A, @

EP

ADDC

A

, R0

ADDC

A

, R1

ADDC

A

, R2

ADDC

A

, R3

ADDC

A

, R4

ADDC

A

, R5

ADDC

A

, R6

ADDC

A

, R7

RETI

CALL

add

r16

SUBC

A

SUBC

W

A

SUBC

A, #

d8

SUBC

A,

dir

SUBC

A, @

IX+d

SUBC

A, @

EP

SUBC

A

, R0

SUBC

A

, R1

SUBC

A

, R2

SUBC

A

, R3

SUBC

A

, R4

SUBC

A

, R5

SUBC

A

, R6

SUBC

A

, R7

PUSH

W

A

PUSH

W

IX

XCH

A

, T

XCHW

A

, T

MO

V

d

ir, A

MO

V

@IX

+d, A

MO

V

@EP

, A

MO

V

R

0, A

MO

V

R

1, A

MO

V

R

2, A

MO

V

R

3, A

MO

V

R

4, A

MO

V

R

5, A

MO

V

R

6, A

MO

V

R

7, A

POPW

A

POPW

IX

XOR

A

XORW

A

XOR

A, #

d8

XOR

A

, dir

XOR

A, @

IX+d

XOR

A, @

EP

XOR

A

, R0

XOR

A

, R1

XOR

A

, R2

XOR

A

, R3

XOR

A

, R4

XOR

A

, R5

XOR

A

, R6

XOR

A

, R7

MO

V

A,

ext

MO

V

ex

t, A

AND

A

ANDW

A

AND

A, #

d8

AND

A

, dir

AND

A, @

IX+d

AND

A, @

EP

AND

A

, R0

AND

A

, R1

AND

A

, R2

AND

A

, R3

AND

A

, R4

AND

A

, R5

AND

A

, R6

AND

A

, R7

MO

VW

A,

PS

MO

VW

PS

, A

OR

A

ORW

A

OR

A, #

d8

OR

A,

dir

OR

A, @

IX+d

OR

A, @

EP

OR

A

, R0

OR

A

, R1

OR

A

, R2

OR

A

, R3

OR

A

, R4

OR

A

, R5

OR

A

, R6

OR

A

, R7

CLRI

CLRC

MO

V

@A,

T

MO

VW

@A,

T

DAA

MO

V

dir,

#d8

MO

V

@IX

+d,#

d8

MO

V

@EP

#, d

8

MO

V

R0, #

d8

MO

V

R1, #

d8

MO

V

R2, #

d8

MO

V

R3, #

d8

MO

V

R4, #

d8

MO

V

R5, #

d8

MO

V

R6, #

d8

MO

V

R7, #

d8

SETI

SETC

MO

V

A, @

A

MO

VW

A, @

A

DAS

CMP

dir,

#d8

CMP

@IX

+d,#

d8

CMP

@EP

#, d

8

CMP

R0, #

d8

CMP

R1, #

d8

CMP

R2, #

d8

CMP

R3, #

d8

CMP

R4, #

d8

CMP

R5, #

d8

CMP

R6, #

d8

CMP

R7, #

d8

CLRB

d

ir : 0

CLRB

d

ir : 1

CLRB

d

ir : 2

CLRB

d

ir : 3

CLRB

d

ir : 4

CLRB

d

ir : 5

CLRB

d

ir : 6

CLRB

d

ir : 7

SETB

d

ir : 0

SETB

d

ir : 1

SETB

d

ir : 2

SETB

d

ir : 3

SETB

d

ir : 4

SETB

d

ir : 5

SETB

d

ir : 6

SETB

d

ir : 7

BBC

di

r : 0

, rel

BBC

di

r : 1

, rel

BBC

di

r : 2

, rel

BBC

di

r : 3

, rel

BBC

di

r : 4

, rel

BBC

di

r : 5

, rel

BBC

di

r : 6

, rel

BBC

di

r : 7

, rel

BBS

di

r : 0

, rel

BBS

di

r : 1

, rel

BBS

di

r : 2

, rel

BBS

di

r : 3

, rel

BBS

di

r : 4

, rel

BBS

di

r : 5

, rel

BBS

di

r : 6

, rel

BBS

di

r : 7

, rel

INCW

A

INCW

SP

INCW

IX

INCW

EP

MO

VW

A,

ext

MO

VW

A,

dir

MO

VW

A, @

IX+d

MO

VW

A, @

EP

INC

R0

INC

R1

INC

R2

INC

R3

INC

R4

INC

R5

INC

R6

INC

R7

DECW

A

DECW

SP

DECW

IX

DECW

EP

MO

VW

ex

t, A

MO

VW

d

ir, A

MO

VW

@IX

+d, A

MO

VW

@EP

, A

DEC

R0

DEC

R1

DEC

R2

DEC

R3

DEC

R4

DEC

R5

DEC

R6

DEC

R7

JMP

@A

MO

VW

SP

, A

MO

VW

IX

, A

MO

VW

EP

, A

MO

VW

A, #

d16

MO

VW

S

P, #

d16

MO

VW

I

X, #

d16

MO

VW

E

P, #

d16

CALL

V

#0

CALL

V

#1

CALL

V

#2

CALL

V

#3

CALL

V

#4

CALL

V

#5

CALL

V

#6

CALL

V

#7

MO

VW

A,

PC

MO

VW

A,

SP

MO

VW

A,

IX

MO

VW

A,

EP

XCHW

A,

PC

XCHW

A,

SP

XCHW

A,

IX

XCHW

A,

EP

BNC

rel

BC

rel

BP

rel

BN

rel

BNZ

rel

BZ

rel

BGE

rel

BLT

rel

01

23

45

67

89

AB

CD

EF

LH

296

APPENDIX C MASK OPTIONS

APPENDIX C MASK OPTIONS

Table C-1 "Mask options" lists the mask options for the MB89170/170A/170L series.

Mask options

Table C-1 Mask options

No.

ModelMB89173LMB89174L

MB89P173MB89173

MB89174AMB89P173-201 MB89P175A MB89PV170

Specification method Specify when ordering masking

Standard option product

Set with EPROM programmer

Cannot be set

1

Pull-up resistorP00 to P07, P10 to P17, P30 to P37, P40 to P44

Can be selected for each individual pin

No pull-up resistors for all ports at all times

Can be selected for each individual pin, but no pull-up resistors for P40 to P44

No pull-up resistors for all ports at all times

2

Power-on reset• Power-on reset

enabled• Power-on reset

disabled

Can be selected Power-on reset disabled at all times

Can be set Power-on reset enabled at all times

3

Selection of initial value for oscillation stabilization time (when Fc = 3.58 MHz)• 3: 218/Fc (approx.

73.2 ms)• 2: 216/Fc (approx.

18.3 ms)• 1: 212/Fc (approx.

1.1 ms)• 0: 23/Fc (approx. 0

ms)

Can be selected 216/Fc at all times Can be set 218/Fc at all times

4

Reset pin output• Reset pin output

enabled• Reset pin output

disabled

Can be selected Reset pin output disabled at all times

Can be set Reset pin output enabled at all times

5Clock mode selection• Dual-clock mode• Single-clock mode

Single-clock mode at all times

Can be selected

Dual-clock mode at all times

Can be set Dual-clock mode at all times

Note:Reset input is asynchronous to the internal clock, regardless of whether power-on reset is enabled or not.

297

APPENDIX D PROM PROGRAMMING


Appendix D describes the PROM programming.

D.1 "PROM Programming "

D.2 "Programming the One-Time PROM"

D.3 "Programming the EPROM on a Piggyback/Evaluation Chip"

298


D.1 PROM Programming

The MB89P173 and MB89P175A have an MBM27C256A-equivalent PROM mode. The PROM can be programmed using a general-purpose ROM programmer via a dedicated adapter. Note, however, that electronic signature mode is not supported.

One-time PROM products

The MB89P173 and MB89P175A are one-time PROM products.

The CPU of these models contains the PROM that can be programmed using a general-purpose ROM programmer via a dedicated adapter. However, the characteristics of the one-time PROM make it impossible to perform an all-bit-write test. Therefore, a write yield of 100%cannot always be guaranteed. See D.2 "Programming the One-Time PROM" for moreinformation.

Piggyback/evaluation products

The MB89PV170A is a piggyback/evaluation product.

The CPU of this model does not contain a PROM.

The external ROM (MBM27C256A-20TVM) can be removed, and programmed using a general-purpose ROM programmer via a dedicated adapter.

See D.3 "Programming the EPROM on a Piggyback/Evaluation Chip" for more information.

299


D.2 Programming the One-Time PROM

This section describes how to program the PROM in the MB89P173 and MB89P175A.

Memory map in PROM mode

Figure D.2-1 "Memory map in PROM mode (MB89P173)" and Figure D.2-2 "Memory map inPROM mode (MB89P175A)" show the memory maps in PROM mode. See "PROM optionbitmap" to write option data to the option setting area.

Figure D.2-1 Memory map in PROM mode (MB89P173)

Vacant area

Program area(PROM)

0000 H

6000 H

7FFF H

Normal operation mode(MB89P173)

PROM mode (Corresponding addresses in the ROM programmer)

Program area(PROM)

0000 H

Not available

FFFF H

8000 H

Not available

0200 H

RAM

I/O0080 H

E000 H

300


Figure D.2-2 Memory map in PROM mode (MB89P175A)

Programming the EPROM

Programming method for the MB89P173

1. Set the EPROM programmer for the MBM27C256A.

2. Load the program data into the area at addresses 6000H to 7FFFH in the EPROMprogrammer. (Note that addresses E000H to FFFFH during single-chip operation correspondto addresses 6000H to 7FFFH in EPROM mode.)

3. Program the EPROM with the EPROM programmer.

Programming method for the MB89P175A


2. Load the program data into the area at addresses 4000H to 7FFFH in the EPROMprogrammer. (Note that addresses C000H to FFFFH during single-chip operation correspondto addresses 4000H to 7FFFH in EPROM mode.) Load the option information into the areaat addresses 3FF0H to 3FF6H in the EPROM programmer. (See "PROM option bitmap" forinformation on correspondence between the addresses and options.)

3. Program the EPROM with the EPROM programmer.

Vacant area

Program area(PROM)

0000 H

3FF0 HOption

setting area

Vacant area3FF6 H

4000 H

7FFF H

Normal operation mode(MB89P175A)

PROM mode (Corresponding addresses in the ROM programmer)

Not available

Program area(PROM)

0000 H

Not available

Not available

FFFF H

8000 H

Not available

0280 H

RAM

I/O0080 H

C000 H

BFF0 H

BFF6 H

301


PROM option bitmap

Table D.2-1 PROM option bitmap (MB89P175A)

7 6 5 4 3 2 1 0

3FF0H VacantRead/write possible

VacantRead/write possible


Clock mode selection1: Single-clock0: Dual-clock

Reset pin output1: Enabled0: Disabled

Power-on reset1: Enabled0: Disabled

Oscillation stabilization time

00: 23/FCH01: 212/FCH

10: 216/FCH11: 218/FCH

3FF1H P07Pull-up1: Provided0: Not provided

P06Pull-up1: Provided0: Not provided















































After erasure, each bit is 1. This means that each port is provided with a pull-up resistor.FCH: Frequency of the main clock source oscillator

302


Recommended screening conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a one-time PROM with no microcomputer program.

Figure D.2-3 "Screening flow" shows a screening flow.

Figure D.2-3 Screening flow

Write yield

The characteristics of a one-time PROM with no microcomputer program make it impossible toperform an all-bit-write test. Therefore, a write yield of 100% cannot always be guaranteed.

Program, verify

High-temperature aging+150˚C, 48 hours

Read

Mount

303


D.3 Programming the EPROM on a Piggyback/Evaluation Chip

This section describes how to program the EPROM on a piggyback/evaluation chip.

EPROM used

MBM27C256A-20TVM

Programming socket adapter

When programming the EPROM with a ROM programmer, use the programming socket adapter(Sun Hayato) below.

Memory space

Figure D.3-1 Memory map for piggyback/evaluation chips

EPROM programming method


2. Load the program data into the area at addresses 0000H to 7FFFH in the EPROMprogrammer.

3. Program the area at addresses 0000H to 7FFFH in the EPROM programmer.

Table D.3-1 Programming socket adapter

Package Adapter socket model

LCC-32 (Square type) ROM-32LC-28DP-S

Contact: Sun Hayato Co., Ltd.: TEL 03-3986-0403

Program area(PROM)

0000 H

7FFF H

Normal operation mode (Corresponding addresses in the ROM programmer)

Program area(PROM)

0000 H

FFFF H

8000 H

Not available

0480 H

RAM

I/O0080 H

304

APPENDIX E PIN STATES FOR THE MB89170/170A/170L SERIES


Table E-1 "Pin states for the MB89170/170A series in each operating mode" lists the pin states for the MB89170/170A series in each operating mode. Table E-2 "Pin states for the MB89170L series in each operating mode" lists the pin states for the MB89170L series in each operating mode.

Pin states for the MB89170/170A series in each operating mode

Table E-1 Pin states for the MB89170/170A series in each operating mode

PinNormal Sleep Stop (SPL=0) Stop (SPL=1) Watch

mode(SPL=0)

Watch mode

(SPL=1)

During a resetMain-

runSub-run

Main-sleep

Sub-sleep

Main-stop

Sub-stop

Main-stop

Sub-stop

X0Oscilla-tion input

Hi-zOscilla-tion input

Hi-z Hi-z Hi-z Hi-z Hi-zOscilla-tion input

X1Oscilla-tion output

High level output

Oscilla-tion output

High level output

High level output High level outputHigh level output

High level output

Oscilla-tion output

X0A*3 Oscillation input Oscillation inputOscilla-tion input



Oscilla-tion input

Oscilla-tion input

X1A*3 Oscillation output Oscillation outputOscilla-tion output

High level output

Oscilla-tion output

High level output

Oscilla-tion output

Oscilla-tion output

Oscilla-tion output

MOD0MOD1

Mode input Mode input Mode input Mode inputMode input

Mode input

Mode input

RST Reset input Reset input Reset input Reset inputReset input

Reset input

Reset input*2

P00/INT20

|P07/

INT27

Port I/O or resource I/O



Hi-z


Hi-z Hi-z

P10-P17 Port I/O

305


P20-P27 Port output Port output Port output Hi-zPort output

Hi-z

Hi-z

P30/SCK

|P37/BZ




Hi-z*1


Hi-z*1

P40-P44 Port output Port output Port output Hi-zPort output

Hi-z

DTMF DTMF output DTMF output Previous state Previous statePrevious state

Previous state

*1: The input level is held constant to prevent a leak current due to open input pins.*2: The reset pin may be used as an output pin, depending on the option setting.*3: Connect this pin to GND when the single-clock option is selected.Hi-z: High impedanceSPL: Pin state setting bit of the standby control register (STBC)Note:• To allow interrupt input, the input level of an external interrupt enable pin is not held constant.• When a mask option is used to provide a pull-up resistor for a pin, the high impedance of the pin is set to

the pull-up state.• "Previous state" indicates the value immediately before stop or watch mode is entered.

Table E-1 Pin states for the MB89170/170A series in each operating mode (Continued)

PinNormal Sleep Stop (SPL=0) Stop (SPL=1) Watch

mode(SPL=0)

Watch mode

(SPL=1)

During a resetMain-

runSub-run

Main-sleep

Sub-sleep

Main-stop

Sub-stop

Main-stop

Sub-stop

306


Pin states for the MB89170L series in each operating mode

Table E-2 Pin states for the MB89170L series in each operating mode

Pin

Normal Sleep Stop (SPL=0) Stop (SPL=1)During a

resetMain-run Sub-runMain-sleep

Sub-sleep Main-stop Sub-stop Main-stop Sub-stop

X0Oscillation input

Hi-zOscillation input

Hi-z Hi-z Hi-zOscillation input

X1Oscillation output

High level output

Oscillation output

High level output

High level output High level outputOscillation output

MOD0MOD1

Mode input Mode input Mode input Mode inputMode input

RST Reset input Reset input Reset input Reset inputReset input*2

P00/INT20|

P07/INT27Port I/O or resource I/O

Port I/O or resource I/O Port I/O or resource I/O Hi-z Hi-z

P10-P17 Port I/O

P20-P27 Port output Port output Port output Hi-z

Hi-zP30/SCK

|P37/BZ

Port I/O or resource I/O Port I/O or resource I/O Port I/O or resource I/O Hi-z*1

P40-P44 Port output Port output Port output Hi-z

*1: The input level is held constant to prevent a leak current due to open input pins.*2: The reset pin may be used as an output pin, depending on an option setting.Hi-z: High impedanceSPL: Pin state setting bit of the standby control register (STBC)Note:• To allow interrupt input, the input level of an external interrupt enable pin is not held constant.• When a mask option is used to provide a pull-up resistor for a pin, the high impedance of the pin is set to

the pull-up state.

307


308

INDEX

INDEX

The index follows on the next page.This is listed in alphabetic order.

309

INDEX

Index

Numerics

16-bit data on RAM, storage of ..............................288/16-bit timer/counter interrupt .............................1648/16-bit timer/counter interrupt, register and vector

table for ......................................................1658/16-bit timer/counter pin .....................................1538/16-bit timer/counter pin, Block diagram of.........1548/16-bit timer/counter register ..............................1558/16-bit timer/counter, block diagram of ...............1518/16-bit timer/counter, notes on using the............1758-bit serial I/O interrupt, register and

vector table for the .....................................1928-bit serial I/O pin .................................................1858-bit serial I/O register..........................................187

A

arithmetic instruction ............................................292

B

bi-directional serial I/O .........................................201bit manipulation instruction, read operation upon the

execution of................................................289bits that control the acceptance of interrupt ...........33block diagram of 8-bit serial I/O............................183block diagram of 8-bit serial I/O pin......................186block diagram of buzzer output ............................210block diagram of buzzer output pin ......................211Block diagram of DTMF generator .......................264block diagram of DTMF generator pin..................266block diagram of external interrupt circuit 1..........219block diagram of external interrupt circuit 2..........235block diagram of external reset pin ........................49block diagram of pins for external interrupt

circuit 1.......................................................222block diagram of pins for external interrupt

circuit 2.......................................................238block diagram of watch prescaler.........................250block diagram of watchdog timer..........................140branch instruction.................................................294buzzer output function..........................................208buzzer output pin..................................................211buzzer output program example ..........................215buzzer output register ..........................................212buzzer register (BZCR) ........................................213

C

clock controller, block diagram of........................... 58clock generator ...................................................... 56clock mode operation state.................................... 62clock supply function.................................... 124, 249clock supply function, operation of the......... 131, 255clock supply map ................................................... 53condition code register (CCR), structure of the...... 32correspondence between the interrupt enable bit 238counter function ................................................... 150counter function, operation of the ........................ 168counter function, program example for the .......... 179

D

dedicated register, functions of .............................. 30dedicated register, structure of the ........................ 29differences between model ...................................... 6DTMF control register (DTMC) ............................ 268DTMF data register (DTMD) ................................ 270DTMF generator function..................................... 262DTMF generator pin............................................. 266DTMF generator program example...................... 272DTMF generator register...................................... 267DTMF generator, operation of the........................ 271

E

effect of a reset on RAM content ........................... 51EPROM programming method............................. 304EPROM used....................................................... 304explanation of addressing.................................... 282external interrupt 1 control register 1 (EIC1)........ 224external interrupt 1 control register 2 (EIC2)........ 226external interrupt 2 control register (EIE2) ........... 240external interrupt 2 flag register (EIF2) ................ 242external interrupt circuit 1 function

(edge detection)......................................... 218external interrupt circuit 1 interrupt, registers and

vector tables for ......................................... 228external interrupt circuit 1 operation,

interrupts during......................................... 228external interrupt circuit 1, operation of................ 229external interrupt circuit 1, pins for....................... 221external interrupt circuit 1, registers for................ 223external interrupt circuit 2 function

310

INDEX

(level detection) ......................................... 234external interrupt circuit 2 interrupt, register and

vector table for the ..................................... 243external interrupt circuit 2, pins for....................... 237external interrupt pins in external interrupt

circuit 2 ...................................................... 238external reset pin, functions of the ......................... 49external shift clock, when using an ...................... 198

F

features to consider when selecting a model........... 6FPT-48P-M16 package dimension ........................ 13FPT-48P-M16 pin assignment ............................... 10

G

gear function (main clock speed select function) ... 63general-purpose register area................................ 26general-purpose register feature............................ 37general-purpose register, structure of the.............. 36

H

halt during operation ............................................ 174halting .................................................................. 173

I

I/O circuit type ........................................................ 18I/O map ................................................................ 274I/O pins and their function ...................................... 15I/O port function ..................................................... 94I/O port program example .................................... 120instruction cycle (tinst) ........................................... 61instruction map..................................................... 296internal shift clock, when using an ....................... 197interrupt during external interrupt circuit 2

operation.................................................... 243interrupt level setting registers (ILR1, ILR2, and

ILR3), structure of the .................................. 39interrupt processing time........................................ 44interrupt requests from peripheral function ............ 38interrupt when operating the interval timer

function ...................................................... 130interrupts ................................................................ 87interrupts during serial I/O operation.................... 192interrupts during the interval timer function

(watch interrupt)......................................... 254interval timer function................................... 124, 148interval timer function (timebase timer),

operation of the.......................................... 131

interval timer function (watch interrupt) ................248interval timer function (watch prescaler),

operation of the ..........................................255interval timer function, interrupt when

operating the ..............................................130interval timer function, operation of the ................166interval timer function, program example of the ...177items in the instruction list ....................................281

M

main clock mode operation.....................................63mask option ..........................................................297MB89170/170A/170L series feature .........................2MB89170/170A/170L series product lineup..............4memory map...........................................................25memory space ......................................................304memory space, structure of the ..............................24mode data...............................................................90mode fetch..............................................................51mode pin.................................................................51mode pin (MOD1, MOD0).......................................89MQP-48C-P01 package dimension ........................14MQP-48C-P01 pin assignment...............................12multiple interrupt .....................................................43

N

notes on handling device........................................22notes on using 8-bit serial I/O...............................200notes on using the timebase timer........................133notes on using the watch prescaler ......................257notes on using the watchdog timer.......................145

O

operating states in standby mode...........................70operation during sub-clock ...................................174operation for selecting the memory access mode ..90operation in sub-clock mode...................................63operation of external interrupt circuit 2 .................244operation result indicator bit ...................................32Oscillation stabilization delay time..........................88oscillation stabilization delay time...................65, 254oscillation stabilization delay time for

the main clock ........................................48, 66oscillation stabilization delay time for

the sub-clock ................................................66other instruction ....................................................295overall block diagram of MB89170/170A series .......8overall block diagram of MB89170L series...............9

311

INDEX

P

piggyback/evaluation product...............................299pin states after the mode data is read....................52pin states during a reset.........................................52pin states for the MB89170L series in each

operating mode ..........................................307pin states in standby mode ....................................85port 0 block diagram...............................................97port 0 operation ......................................................99port 0 pin ................................................................96port 0 register .........................................................97port 0 register, functions of the...............................98port 0 structure .......................................................96port 1 block diagram.............................................102port 1 operation ....................................................104port 1 pin ..............................................................101port 1 register .......................................................102port 1 register, functions of the.............................103port 1 structure .....................................................101port 2 block diagram.............................................107port 2 operation ....................................................109port 2 pin ..............................................................106port 2 register .......................................................107port 2 register, functions of the.............................108port 2 structure .....................................................106port 3 block diagram.............................................111port 3 operation ....................................................114port 3 pin ..............................................................110port 3 register .......................................................111port 3 register, functions of the.............................112port 3 structure .....................................................110port 4 block diagram.............................................117port 4 operation ....................................................119port 4 pin ..............................................................116port 4 register .......................................................117port 4 register, functions of the.............................118port 4 structure .....................................................116processing during an interrupt................................41program example for serial input..........................205program example for serial output........................203programming socket adapter ...............................304programming the EPROM....................................301PROM mode, memory map in..............................300PROM option bitmap............................................302PROM product, one-time .....................................299

R

read-modify-write operation..................................289

recommended screening condition ...................... 303register and vector table for the timebase timer

interrupt...................................................... 130register bank pointer (RP), structure of the............ 35registers for external interrupt circuit 2................. 239reset cause ............................................................ 48reset causes........................................................... 47reset operation, overview of................................... 50reset state during oscillation stabilization delay ..... 51restarting the timer ............................................... 173

S

sample programs for external interrupt circuit 2... 245sample programs of external interrupt circuit 1.... 231serial data register (SDR) .................................... 191serial I/O function................................................. 182serial input is completed, operation when............ 196serial input operation............................................ 195serial mode register (SMR).................................. 188serial output is completed, operation when.......... 194serial output operation ......................................... 193single-chip mode.................................................... 89sleep mode operation ............................................ 72special instruction ................................................ 286square wave output initialization function,

operation of the.......................................... 171stack area for interrupt processing......................... 46stack operation at start of interrupt processing...... 45stack operation when interrupt return .................... 45standby control register (STBC)............................. 76standby mode ................................................ 68, 174state transition diagram 1

(power-on reset, dual-clock) ........................ 78state transition diagram 2

(no power-on reset, dual-cnck) .................... 80state transition diagram 3 (single-clock) ................ 83stop mode operation .............................................. 73storing 16-bit data on the stack.............................. 28summary of F2MC-8L instruction......................... 279switching to standby mode..................................... 87symbols used with instruction .............................. 280system clock control register (SYCC),

structure of the............................................. 60

T

timebase timer control register (TBTC)................ 128timebase timer interrupt ....................................... 130timebase timer program example ........................ 135timebase timer, block diagram of ......................... 126

312

INDEX

timebase timer, operation of the .......................... 132timer 1 control register (T1CR) ............................ 156timer 1 data register (T1DR) ................................ 160timer 2 control register (T2CR) ............................ 158timer 2 data register (T2DR) ................................ 162transfer instruction ............................................... 290

U

using an interrupt to wake up from a standby mode ........................................... 87

V

vector table area .................................................... 26vector table for the timebase timer interrupt ........ 130

W

watch interrupt ......................................................254watch mode operation ............................................75watch prescaler control register (WPCR) .............252watch prescaler interrupt, register and

vector table for the......................................254watch prescaler program example .......................259watch prescaler, operation of the .........................256watchdog control register (Wdtc)..........................142watchdog timer program example ........................146watchdog timer, function of the.............................138watchdog timer, operation of the ..........................144write yield..............................................................303

313

INDEX

314

CM25-10115-3E

FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL

F2MC-8L

8-BIT MICROCONTROLLER

MB89170/170A/170L Series

HARDWARE MANUAL

March 2001 the third edition

Published FUJITSU LIMITED Electronic Devices

Edited Technical Information Dept.

FUJITSU SEMICONDUCTOR F2MC-8L 8-BIT MICROCONTROLLERS MB89170/170A/170L Series HARDWARE MANUAL

Documents

CONTROLLER MANUAL - Fujitsui PREFACE Objectives and Intended Readers Thank you for purchasing FUJITSU semiconductor products. The MB89170/170A/170L series products have been developed