Computing Faster without CPUs

Storaasli 5/9/03Analytical and Computational Methods

Computing Faster without CPUs

Scientific Applications on FPGA-based* Reconfigurable Hypercomputers

byDr. Olaf Storaasli

Analytical & Computational Methods BranchStructures and Materials

for

May Seminar, Electronic Systems Branch

*Field-Programmable Gate Array

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Analytical and Computational Methods

NASA Research BackgroundFEA: NASTRAN

Viking ==> Mars

IPAD: Integrated Design

Finite Element Machine: Early // Computer

Cray GigaFLOP Award: Shuttle SRBMatrix Equation Solver: FORTRAN, C, Java

Lanczos Eigensolver: 88x Speedup

Intel: Supercomputer Users Board, P6 Award

Symposia: Large-Scale Apps. (5)NASA Software of the Year Award

Creativity & Innovation Awards

NASA Fellowship: Norway

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Exploring Scientific Applicationson Reconfigurable Hypercomputers

‘02 ‘03Creativity & Innovation62K gates/FPGA 6M gates/FPGA

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Computing Faster Without CPUsGOAL: Evaluate FPGA*-based Hypercomputer Potential

for NASA Scientific Computations TEAM: Dr. Olaf Storaasli, Principal Investigator

PARTNERS: Star Bridge Systems, NSA, USAF, MSFC

, William Fithian-Harvard, Siddhartha Krishnamurthy-VT Shaun Foley-MIT, Cris Kania-GS, Neha Dandawate-GS, Patrick Butler-VT Kristin Barr-JPMorgan, Robert Lewis-Morehouse , Vincent Vance-VT

Jarek Sobieski, Robert Singleterry, Dave Rutishauser, Joe RehderGarry Qualls

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William Fithian* (Harvard, Merit Scholar, Oracle Award)

*NASA-NHGS mentorship ‘00-’02

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First Langley Hypercomputers10 FPGAs each

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FPGA Programming• User controls gates: middle man removed• Code options:

– 1-D Text, sequential FORTRAN-like: C-to-Gate, VHDL• parallelism esoteric

– 3-D Graphic, parallel drag & drop: Viva • Parallelism inherent • data flow like analog computer

NASA Hypercomputers

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FPGA: New Computing ParadigmTraditional CPU

Gateware: VIVA Icons & Transports

26 MFLOPS/250 MHz SGI

Reconfigurable FPGA

Sequential: 1 operation/cycle

Fixed gates & data types

Wasteful: 99% gates idle/cycle yet all draw power

Software: Text - 1Ddo i = 1, billion

c= a+b

end do

Parallel: Inherent

Dynamic gates & data types

Efficient: Optimizes gates to task

392+ MFLOPS/64 MHz FPGA3.92+ GFLOPS/10 FPGA board

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Select-Drag-Drop to Code “icon”

Primitives

Add new code to libraryComplex algorithms “drill in”

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VIVA:Custom Chip Design GatewareWhat: Graphics tool to “route” FPGAs (VHDL cumbersome)

Growth in VIVA Capability

Extensive Data Types

Trig, Logs, Transcendentals

File Input/Output

Vector-Matrix Support

Access to Multiple FPGAs

Extensive Documentation

Stable Development

Few “bugs”

NO Floating Point

NO Scientific Functions

NO File Input/Output

NO Vector-Matrix Support

Access to One FPGA

Primitive Documentation

Weekly Changes

Frequent “bugs”

VIVA 1 (Feb ’01) VIVA2 (July ’02)

How: Converts icon-transport “gateware” to circuit logic

Why: Achieve near-ASIC speed (w/o chip design $)

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VivaUser1

VivaUser2

VivaUser3

VivaUser4

VivaUser5

VivaUser6

Windows Server

HC-38m Hypercomputer 7 FPGAs 6M Gates

Parallel Use of Parallel FPGAs

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Algorithms Developed*

* In AIAA & Military & Aerospace Programmable Logic Device (MAPLD) papers

.

• n! => Probability: Combinations/Permutations AirSC

• Cordic => Transcendentals: sin, log, exp, cosh… ∂y/∂x & ∫f(x)dx => Runge-Kutta: CFD, Newmark Beta: CSM

Matrix Equation Solver: [A]{x} = {b} - Gauss & Jacobi

• Nonlinear Analysis: Analog simulation avoids NLT devp’t time

Matrix Algebra: {V}, [M], {V}T{V}, [M]x[M],GCD,…

• Dynamic Analysis: [M]{ü} + [C]{u} + [K]{u} + NLT = {P(t)}

• Analog Computing: digital accuracy

QuickTime™ and aMicrosoft Video 1 decompressorare needed to see this picture.QuickTime™ and aMicrosoft Video 1 decompressorare needed to see this picture.

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Numeric Integration

f(x)=x2 f(x)*xx

f(x)*xxi+1=xi+x

Control

Output (Area under curve)

f(x)

xx

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VIVA Sparse Matrix Equation SolverJacobi Iterative (3x3 Demo)

Control 3 Row Loads 3 // Dot Products[A]{x}={b}x1 = 1/A11*(b1 - A12*x2 - A13*x3)

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zbPa

x-

/

ydMe

x-

/ z

y yi = (P - b zi-1)/a

zi = (M - dyi-1)/e

- initializedoutput y

output z

Analog Diagram of 2x2 Equations Solutionin

put

inpu

t

bz P-bzbz

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Fixed-Point Iteration: VIVA Diagram

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Year 2: Exploit Latest FPGAs

Plans: - Millions of Matrix Equations: Structures, Electromagnetics & Acoustics - Rapid Static & Dynamic Structural Analyses - Cray Vector Computations in Weather Code (VT PhD) - Robert on Administrator’s Fellowship at Star Bridge Systems - Simulate advanced computing concepts using VIVA - Collaborate with SBS, NSA, A&T… to expand VIVA libraries - Tailor VIVA development for NASA applications - Target applications to NASA programs (e.g. EDB Collaboration??)

Rapid Growth in FPGA Capability

FPGA (Feb ’01) FPGA (Oct ’02)

Xilinx FPGAGatesMultiplies on chipClock Speed MHzMemory on chipMemory SpeedReconfigure TimeGFLOPS

Total GFLOPs

XC406262K010020Kb466 Gb/s100ms0.4

4 (10 FPGAs)

XC2V60006 million (97x)144300 (3x)3.5 Mb (175x)5 Tb/s (11x)40ms (2.5x)47 (120x)

329 (7 FPGAs)

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SummaryWhat We’re Learning

We like FPGA promise – accomplished much

Hardware: Testing 3 futuristic FPGA systems

FPGAs: Inherently //, flexible, efficient, & fast, dramatic advances

VIVA: Powerful & growing (tailor to NASA needs)

Applications: ‘02 - Diverse “pathfinder” algorithms developed

Speed: Year 1: 4 GFLOPS => Year 2: 329 GFLOPSFuture: exploit capability on NASA “cutting edge” innovations

‘03 - Comprehensive NASA engineering applications

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Langley Reconfigurable Computing Research1. Singleterry, Robert C., Jaroslav Sobieszczanski-Sobieski, and Samuel Brown. “Field-Programmable Gate Array Computer in Structural Analysis: an Initial

Exploration.” 43rd American Institute of Aeronautics and Astronautics (AIAA) Structures, Structural Dynamics, and Materials Conference . April 22-25, 2002. 2. Storaasli, Olaf O., Robert C. Singleterry, and Samuel Brown. “Scientific Computations on a NASA Reconfigurable Hypercomputer.” Abstract accepted for 5th

Military and Aerospace Programmable Logic Devices (MAPLD) Conference, Paper in preparation . September 10-12, 2002.3. Fithian, William, Samuel Brown, and Tyler Reed. “Object Synchronization in VIVA 1.5.” Briefing prepared for VIVA users at NASA Marshall, Eglin AFB,

Progress Forge, Inc., and Star Bridge Systems, Inc. March 26, 2002.4. Barr, Kristen, Shaun Foley, and Robert A. Lewis II. “Hypercomputing with the CORDIC Algorithm.” August, 2001. Presentation of research conducted under Dr.

Olaf O. Storaasli, June-August, 2001.5. Butler, Patrick. New Horizons Governors School Mentorship Project. May, 2001. Presentation of research conducted under Dr. Olaf O. Storaasli, September 2000 –

May 2001.6. Dandawate, Neha. “Reckless Speeding: The Investigation of the Programming Capabilities of the HAL Hypercomputer.” July, 2002. Presentation of research

conducted under Dr. Olaf O. Storaasli, June – July, 2002.7. Dandawate, Neha. “The Investigation of the Programming Capabilities of the HAL-15 Hypercomputer.” July, 2002. Paper on research conducted under Dr. Olaf O.

Storaasli, June – July, 2002.8. Fithian, William. “Developing a Matrix Equation Solver for the HAL-15 Hypercomputer.” December, 2001. Proposal for research to be conducted under Dr. Olaf O.

Storaasli, September 2001 – May 2002.9. Fithian, William. “Developing a Matrix Equation Solver for the HAL-15.” May, 2002. Presentation of research conducted under Dr. Olaf O. Storaasli, September

2001 – May 2002.10. Fithian, William. “Jacobi Iterative Matrix Equation Solver for Star Bridge Systems FPGA Hypercomputer.” September, 2002. In preparation.11. Foley, Shaun. “Scientific Hypercomputing.” August, 2001. Paper describing research conducted under Dr. Olaf O. Storaasli, June – August, 2001.12. Krishnamurthy, Siddhartha. “Development of an Integration Algorithm for Field Programable Gate Arrays using VIVA.” July, 2002. Paper describing research

conducted under Dr. Robert C. Singleterry, June – Aug 2002.

Further Information: Google: “olaf acmb”

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Computing Faster without CPUs