8
JNTUWORLD Code No: 55021 Set No. 1 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD III B.Tech. I Sem., I Mid-Term Examinations, Aug/Sept– 2013 COMPUTER ORGANIZATION Objective Exam Name: ______________________________ Hall Ticket No. Answer All Questions. All Questions Carry Equal Marks.Time: 20 Min. Marks: 10. I Choose the correct alternative: 1. Which among the following is not a system software [ ] A) Compiler B) Word Processor C) Assembler D) Linker 2. Parity generator and checker networks are logic circuits constructed with [ ] A) NAND B) NOR C) Exclusive-OR D) OR 3. Zero address instructions in a stack organized computer are ________ mode. [ ] A) Immediate B) Implied C) Direct D) Indirect 4. In computers, subtraction is generally carried out by [ ] A) 9’s Complement B) 10’s Complement C) 1’s Complement D) 2’s Complement 5. The address of microinstruction is specified in [ ] A) Memory Address Register B) Control Address Register C) Program Counter D) None 6. The number of bits required to represent a character from ASCII code set is [ ] A) 7 B) 8 C) 2 D) 5 7. The Interrupt cycle is hardware representation of [ ] A) BUN B) ISZ C) BSA D) SNZ 8. Using 2’s Complement, subtraction, of (1010) 2 from (0011) 2 [ ] A) (0111) 2 B) (1001) 2 C) –(0111) 2 D) –(1001) 2 9. Half Adder consists of _________ gates [ ] A) Ex-OR, AND B) Ex-OR, OR C) Ex-OR, NOT D) Ex-OR, NAND 10. For a memory unit with 4096 words we need how many address bits? [ ] A) 6 B) 15 C) 12 D) 8 Cont…..2 A www.jntuworld.com || www.android.jntuworld.com || www.jwjobs.net || www.android.jwjobs.net www.jntuworld.com || www.jwjobs.net

Computer Organization

Embed Size (px)

DESCRIPTION

co bit paper

Citation preview

  • JNTU

    WORL

    D

    Code No: 55021 Set No. 1

    JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD III B.Tech. I Sem., I Mid-Term Examinations, Aug/Sept 2013

    COMPUTER ORGANIZATION Objective Exam

    Name: ______________________________ Hall Ticket No.

    Answer All Questions. All Questions Carry Equal Marks.Time: 20 Min. Marks: 10. I Choose the correct alternative: 1. Which among the following is not a system software [ ]

    A) Compiler B) Word Processor C) Assembler D) Linker 2. Parity generator and checker networks are logic circuits constructed with [ ]

    A) NAND B) NOR C) Exclusive-OR D) OR 3. Zero address instructions in a stack organized computer are ________ mode. [ ]

    A) Immediate B) Implied C) Direct D) Indirect 4. In computers, subtraction is generally carried out by [ ]

    A) 9s Complement B) 10s Complement C) 1s Complement D) 2s Complement 5. The address of microinstruction is specified in [ ]

    A) Memory Address Register B) Control Address Register C) Program Counter D) None

    6. The number of bits required to represent a character from ASCII code set is [ ]

    A) 7 B) 8 C) 2 D) 5 7. The Interrupt cycle is hardware representation of [ ]

    A) BUN B) ISZ C) BSA D) SNZ 8. Using 2s Complement, subtraction, of (1010)2 from (0011)2 [ ]

    A) (0111)2 B) (1001)2 C) (0111)2 D) (1001)2 9. Half Adder consists of _________ gates [ ]

    A) Ex-OR, AND B) Ex-OR, OR C) Ex-OR, NOT D) Ex-OR, NAND 10. For a memory unit with 4096 words we need how many address bits? [ ] A) 6 B) 15 C) 12 D) 8

    Cont..2

    A

    www.jntuworld.com || www.android.jntuworld.com || www.jwjobs.net || www.android.jwjobs.net

    www.jntuworld.com || www.jwjobs.net

  • JNTU

    WORL

    D

    Code No: 55021 :2: Set No. 1 II Fill in the blanks 11. When the control signals are generated by hardware, the control unit is said to be

    ____________________ 12. A floating point number is said to be normalized if the most significant bit of the mantissa is __________________ 13. The operations executed on data stored in registers are called ____________________. 14. The translation of a symbolic program into binary is done by an _________________. 15. A sequence of microinstructions constitutes a __________________. 16. The stack organization is effective for evaluating __________________ . 17. The basic performance equation is T=____________. 18. _______________ register stores the address of the next instruction to be read from memory. 19. Internal interrupts are also called as _______________. 20. ________________ architecture has a simplified instruction set with reduced execution time.

    -o0o-

    www.jntuworld.com || www.android.jntuworld.com || www.jwjobs.net || www.android.jwjobs.net

    www.jntuworld.com || www.jwjobs.net

  • JNTU

    WORL

    D

    Code No: 55021 Set No. 2

    JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD III B.Tech. I Sem., I Mid-Term Examinations, Aug/Sept 2013

    COMPUTER ORGANIZATION Objective Exam

    Name: ______________________________ Hall Ticket No.

    Answer All Questions. All Questions Carry Equal Marks.Time: 20 Min. Marks: 10. I Choose the correct alternative: 1. In computers, subtraction is generally carried out by [ ]

    A) 9s Complement B) 10s Complement C) 1s Complement D) 2s Complement 2. The address of microinstruction is specified in [ ]

    A) Memory Address Register B) Control Address Register C) Program Counter D) None

    3. The number of bits required to represent a character from ASCII code set is [ ]

    A) 7 B) 8 C) 2 D) 5 4. The Interrupt cycle is hardware representation of [ ]

    A) BUN B) ISZ C) BSA D) SNZ 5. Using 2s Complement, subtraction, of (1010)2 from (0011)2 [ ]

    A) (0111)2 B) (1001)2 C) (0111)2 D) (1001)2 6. Half Adder consists of _________ gates [ ]

    A) Ex-OR, AND B) Ex-OR, OR C) Ex-OR, NOT D) Ex-OR, NAND 7. For a memory unit with 4096 words we need how many address bits? [ ] A) 6 B) 15 C) 12 D) 8 8. Which among the following is not a system software [ ]

    A) Compiler B) Word Processor C) Assembler D) Linker 9. Parity generator and checker networks are logic circuits constructed with [ ]

    A) NAND B) NOR C) Exclusive-OR D) OR 10. Zero address instructions in a stack organized computer are ________ mode. [ ]

    A) Immediate B) Implied C) Direct D) Indirect

    Cont..2

    A

    www.jntuworld.com || www.android.jntuworld.com || www.jwjobs.net || www.android.jwjobs.net

    www.jntuworld.com || www.jwjobs.net

  • JNTU

    WORL

    D

    Code No: 55021 :2: Set No. 2 II Fill in the blanks 11. The translation of a symbolic program into binary is done by an _________________. 12. A sequence of microinstructions constitutes a __________________. 13. The stack organization is effective for evaluating __________________ . 14. The basic performance equation is T=____________. 15. _______________ register stores the address of the next instruction to be read from memory. 16. Internal interrupts are also called as _______________. 17. ________________ architecture has a simplified instruction set with reduced execution time. 18. When the control signals are generated by hardware, the control unit is said to be

    ____________________ 19. A floating point number is said to be normalized if the most significant bit of the mantissa is __________________ 20. The operations executed on data stored in registers are called ____________________.

    -o0o-

    www.jntuworld.com || www.android.jntuworld.com || www.jwjobs.net || www.android.jwjobs.net

    www.jntuworld.com || www.jwjobs.net

  • JNTU

    WORL

    D

    Code No: 55021 Set No. 3

    JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD III B.Tech. I Sem., I Mid-Term Examinations, Aug/Sept 2013

    COMPUTER ORGANIZATION Objective Exam

    Name: ______________________________ Hall Ticket No.

    Answer All Questions. All Questions Carry Equal Marks.Time: 20 Min. Marks: 10. I Choose the correct alternative: 1. The number of bits required to represent a character from ASCII code set is [ ]

    A) 7 B) 8 C) 2 D) 5 2. The Interrupt cycle is hardware representation of [ ]

    A) BUN B) ISZ C) BSA D) SNZ 3. Using 2s Complement, subtraction, of (1010)2 from (0011)2 [ ]

    A) (0111)2 B) (1001)2 C) (0111)2 D) (1001)2 4. Half Adder consists of _________ gates [ ]

    A) Ex-OR, AND B) Ex-OR, OR C) Ex-OR, NOT D) Ex-OR, NAND 5. For a memory unit with 4096 words we need how many address bits? [ ] A) 6 B) 15 C) 12 D) 8 6. Which among the following is not a system software [ ]

    A) Compiler B) Word Processor C) Assembler D) Linker 7. Parity generator and checker networks are logic circuits constructed with [ ]

    A) NAND B) NOR C) Exclusive-OR D) OR 8. Zero address instructions in a stack organized computer are ________ mode. [ ]

    A) Immediate B) Implied C) Direct D) Indirect 9. In computers, subtraction is generally carried out by [ ]

    A) 9s Complement B) 10s Complement C) 1s Complement D) 2s Complement 10. The address of microinstruction is specified in [ ]

    A) Memory Address Register B) Control Address Register C) Program Counter D) None

    Cont..2

    A

    www.jntuworld.com || www.android.jntuworld.com || www.jwjobs.net || www.android.jwjobs.net

    www.jntuworld.com || www.jwjobs.net

  • JNTU

    WORL

    D

    Code No: 55021 :2: Set No. 3 II Fill in the blanks 11. The stack organization is effective for evaluating __________________ . 12. The basic performance equation is T=____________. 13. _______________ register stores the address of the next instruction to be read from memory. 14. Internal interrupts are also called as _______________. 15. ________________ architecture has a simplified instruction set with reduced execution time. 16. When the control signals are generated by hardware, the control unit is said to be

    ____________________ 17. A floating point number is said to be normalized if the most significant bit of the mantissa is __________________ 18. The operations executed on data stored in registers are called ____________________. 19. The translation of a symbolic program into binary is done by an _________________. 20. A sequence of microinstructions constitutes a __________________.

    -o0o-

    www.jntuworld.com || www.android.jntuworld.com || www.jwjobs.net || www.android.jwjobs.net

    www.jntuworld.com || www.jwjobs.net

  • JNTU

    WORL

    D

    Code No: 55021 Set No. 4

    JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD III B.Tech. I Sem., I Mid-Term Examinations, Aug/Sept 2013

    COMPUTER ORGANIZATION Objective Exam

    Name: ______________________________ Hall Ticket No.

    Answer All Questions. All Questions Carry Equal Marks.Time: 20 Min. Marks: 10. I Choose the correct alternative: 1. Using 2s Complement, subtraction, of (1010)2 from (0011)2 [ ]

    A) (0111)2 B) (1001)2 C) (0111)2 D) (1001)2 2. Half Adder consists of _________ gates [ ]

    A) Ex-OR, AND B) Ex-OR, OR C) Ex-OR, NOT D) Ex-OR, NAND 3. For a memory unit with 4096 words we need how many address bits? [ ] A) 6 B) 15 C) 12 D) 8 4. Which among the following is not a system software [ ]

    A) Compiler B) Word Processor C) Assembler D) Linker 5. Parity generator and checker networks are logic circuits constructed with [ ]

    A) NAND B) NOR C) Exclusive-OR D) OR 6. Zero address instructions in a stack organized computer are ________ mode. [ ]

    A) Immediate B) Implied C) Direct D) Indirect 7. In computers, subtraction is generally carried out by [ ]

    A) 9s Complement B) 10s Complement C) 1s Complement D) 2s Complement 8. The address of microinstruction is specified in [ ]

    A) Memory Address Register B) Control Address Register C) Program Counter D) None

    9. The number of bits required to represent a character from ASCII code set is [ ]

    A) 7 B) 8 C) 2 D) 5 10. The Interrupt cycle is hardware representation of [ ]

    A) BUN B) ISZ C) BSA D) SNZ

    Cont..2

    A

    www.jntuworld.com || www.android.jntuworld.com || www.jwjobs.net || www.android.jwjobs.net

    www.jntuworld.com || www.jwjobs.net

  • JNTU

    WORL

    D

    Code No: 55021 :2: Set No. 4 II Fill in the blanks 11. _______________ register stores the address of the next instruction to be read from memory. 12. Internal interrupts are also called as _______________. 13. ________________ architecture has a simplified instruction set with reduced execution time. 14. When the control signals are generated by hardware, the control unit is said to be

    ____________________ 15. A floating point number is said to be normalized if the most significant bit of the mantissa is __________________ 16. The operations executed on data stored in registers are called ____________________. 17. The translation of a symbolic program into binary is done by an _________________. 18. A sequence of microinstructions constitutes a __________________. 19. The stack organization is effective for evaluating __________________ . 20. The basic performance equation is T=____________.

    -o0o-

    www.jntuworld.com || www.android.jntuworld.com || www.jwjobs.net || www.android.jwjobs.net

    www.jntuworld.com || www.jwjobs.net