Upload
others
View
2
Download
0
Embed Size (px)
Citation preview
UTM-RHH Slide Set 3 1
Computer Microprocessor Architecture & Programming
HCA1109
System Buses
UTM-RHH Slide Set 3 2
Program ConceptHard-wired systems are inflexibleGeneral purpose hardware can do different tasks, given correct control signalsInstead of re-wiring, supply a new set of control signals
UTM-RHH Slide Set 3 3
What is a program?A sequence of stepsFor each step, an arithmetic or logical operation is doneFor each operation, a different set of control signals is needed
UTM-RHH Slide Set 3 4
Function of Control UnitFor each operation a unique code is provided– e.g. ADD, MOVEA hardware segment accepts the code and issues the control signals
We have a computer!
UTM-RHH Slide Set 3 5
ComponentsThe Control Unit and the Arithmetic and Logic Unit constitute the Central Processing UnitData and instructions need to get into the system and results out– Input/outputTemporary storage of code and results is needed– Main memory
UTM-RHH Slide Set 3 6
Computer Components: Top Level View
UTM-RHH Slide Set 3 7
Instruction CycleTwo steps:– Fetch– Execute
UTM-RHH Slide Set 3 8
Fetch CycleProgram Counter (PC) holds address of next instruction to fetchProcessor fetches instruction from memory location pointed to by PCIncrement PC– Unless told otherwiseInstruction loaded into Instruction Register (IR)Processor interprets instruction and performs required actions
UTM-RHH Slide Set 3 9
Execute CycleProcessor-memory– data transfer between CPU and main memoryProcessor I/O– Data transfer between CPU and I/O moduleData processing– Some arithmetic or logical operation on dataControl– Alteration of sequence of operations e.g. jumpCombination of above
UTM-RHH Slide Set 3 10
Example of Program Execution
UTM-RHH Slide Set 3 11
Instruction Cycle - State Diagram
UTM-RHH Slide Set 3 12
ConnectingAll the units must be connectedDifferent type of connection for different type of unit– Memory– Input/Output– CPU
UTM-RHH Slide Set 3 13
Computer Modules
UTM-RHH Slide Set 3 14
Memory ConnectionReceives and sends dataReceives addresses (of locations)Receives control signals – Read– Write– Timing
UTM-RHH Slide Set 3 15
Input/Output Connection (1)Similar to memory from computer’s viewpointOutput– Receive data from computer– Send data to peripheralInput– Receive data from peripheral– Send data to computer
UTM-RHH Slide Set 3 16
Input/Output Connection (2)Receive control signals from computerSend control signals to peripherals– e.g. spin diskReceive addresses from computer– e.g. port number to identify peripheralSend interrupt signals (control)
UTM-RHH Slide Set 3 17
CPU ConnectionReads instruction and dataWrites out data (after processing)Sends control signals to other unitsReceives (& acts on) interrupts
UTM-RHH Slide Set 3 18
BusesThere are a number of possible interconnection systemsSingle and multiple BUS structures are most commone.g. Control/Address/Data bus (PC)e.g. Unibus (DEC-PDP)
UTM-RHH Slide Set 3 19
What is a Bus?A communication pathway connecting two or more devicesUsually broadcast Often grouped– A number of channels in one bus– e.g. 32 bit data bus is 32 separate single bit channelsPower lines may not be shown
UTM-RHH Slide Set 3 20
Data BusCarries data– Remember that there is no difference between “data” and “instruction” at this levelWidth is a key determinant of performance– 8, 16, 32, 64 bit
UTM-RHH Slide Set 3 21
Address busIdentify the source or destination of datae.g. CPU needs to read an instruction (data) from a given location in memoryBus width determines maximum memory capacity of system– e.g. 8080 has 16 bit address bus giving 64k address space
UTM-RHH Slide Set 3 22
Control BusControl and timing information– Memory read/write signal– Interrupt request– Clock signals
UTM-RHH Slide Set 3 23
Bus Interconnection Scheme
UTM-RHH Slide Set 3 24
Big and Yellow?What do buses look like?– Parallel lines on circuit boards– Ribbon cables– Strip connectors on mother boards
• e.g. PCI– Sets of wires
UTM-RHH Slide Set 3 25
Single Bus ProblemsLots of devices on one bus leads to:– Propagation delays
• Long data paths mean that co-ordination of bus use can adversely affect performance• If aggregate data transfer approaches bus capacityMost systems use multiple buses to overcome these problems
UTM-RHH Slide Set 3 26
Traditional (ISA) with cache
UTM-RHH Slide Set 3 27
High Performance Bus
UTM-RHH Slide Set 3 28
Bus TypesDedicated– Separate data & address linesMultiplexed– Shared lines– Address valid or data valid control line– Advantage - fewer lines– Disadvantages
• More complex control• Ultimate performance
UTM-RHH Slide Set 3 29
Bus ArbitrationMore than one module controlling the buse.g. CPU and DMA controllerOnly one module may control bus at one timeArbitration may be centralised or distributed
UTM-RHH Slide Set 3 30
Centralised ArbitrationSingle hardware device controlling bus access– Bus Controller– ArbiterMay be part of CPU or separate
UTM-RHH Slide Set 3 31
Distributed ArbitrationEach module may claim the busControl logic on all modules
UTM-RHH Slide Set 3 32
PCI BusPeripheral Component InterconnectionIntel released to public domain32 or 64 bit50 lines
UTM-RHH Slide Set 3 33
PCI Bus Lines (required)Systems lines– Including clock and resetAddress & Data– 32 time mux lines for address/data– Interrupt & validate linesInterface ControlArbitration– Not shared– Direct connection to PCI bus arbiterError lines
UTM-RHH Slide Set 3 34
PCI Bus Lines (Optional)Interrupt lines– Not sharedCache support64-bit Bus Extension– Additional 32 lines– Time multiplexed– 2 lines to enable devices to agree to use 64-bit transfer
UTM-RHH Slide Set 3 35
PCI CommandsTransaction between initiator (master) and targetMaster claims busDetermine type of transaction– e.g. I/O read/writeAddress phaseOne or more data phases
UTM-RHH Slide Set 3 36
ReadingsStallings, chapter 3www.pcguide.com/ref/mbsys/buses/www.pcguide.com