Computer Design Basicsviplab.cs.nctu.edu.tw/course/DSD2015_Spring/DSD_Lecture_08.pdf · Digital Systems Design Lecture 8 3 Outlines Introduction Datapaths The Arithmetic/Logic Unit

Digital Systems Design

Lecture 8

1

Lan-Da Van (范倫達), Ph. D.

Department of Computer Science National Chiao Tung University

Taiwan, R.O.C. Spring, 2015

Computer Design Basics

Source: Prof. M. Morris Mano and Prof. Charles

R. Kime, Logic and Computer Design

Fundamentals, 3rd Edition, 2004, Prentice Hall.

[email protected]

http://www.cs.nctu.edu.tw/~ldvan/


Lecture 8

Content Connections

Digital System Design Embedded System: Zedboard

DSP System: Adder, Mul, Filter

Computer Architecture

2

Embedded System: Galileo


Lecture 8

3

Outlines

Introduction

Datapaths

The Arithmetic/Logic Unit (ALU)

The Shifter

Datapath Representation

The Control Word

A Simple Computer Architecture

Single-Cycle Hardwired Control

Summary


Lecture 8

4

Introduction (1/2)

Computer Specification

— Instruction Set Architecture (ISA) - the specification of

a computer's appearance to a programmer at its

lowest level

— Computer Architecture - a high-level description of the

hardware implementing the computer derived from the

ISA

— The architecture usually includes additional

specifications such as speed, cost, and reliability.


Lecture 8

5

Introduction (2/2)

Simple computer architecture decomposed into:

— Datapath for performing operations

— Control unit for controlling datapath operations

A datapath is specified by:

— A set of registers

— The microoperations performed on the data stored in

the registers

— A control interface


Lecture 8

6

Datapaths

Guiding principles for basic datapaths:

— The set of registers

Collection of individual registers

A set of registers with common access resources called a

register file

A combination of the above

— Microoperation implementation

One or more shared resources for implementing

microoperations

Buses - shared transfer paths

Arithmetic-Logic Unit (ALU) - shared resource for implementing

arithmetic and logic microoperations

Shifter - shared resource for implementing shift

microoperations


Lecture 8

7

Four parallel-load

registers

Two mux-based

register selectors

Register destination

decoder

Mux B for external

constant input

Buses A and B with external

address and data outputs

ALU and Shifter with

Mux F for output select

Mux D for external data input

Logic for generating status bits

V, C, N, Z

Datapath Example

MD select 0 1MUX D

V

C

N

Z

n

n

n

n

n

n

n

n

n n

n

2 2

n

n

A data B data

Register file

1 0

MUX B A ddressoutDataout

BusA

Bus B

n

n

Function unit

A B nG select

4

Zero Detect

MF select

nn

nF

MUX F

H select2

n

A BS2:0 || Cin

A rithmetic/logicunit (A LU)

G

BS

Shifter

H

MUX

0

1

2

3

MUX

0

1

2

3

0 1 2 3

Decoder

Load

Load

Load

Load

Load enable

Write

D data

D address2

Destination select

Constant in

MB select

A select

A address

B select

B address

R3

R2

R1

R0

Bus Dn

Data in

ILIR0 0

0 1


Lecture 8

8 MD select 0 1

MUX D

V

C

N

Z

n

n

n

n

n

n

n

n

n n

n

2 2

n

n

A data B data

Register file

1 0

MUX B A ddressoutDataout

BusA

Bus B

n

n

Function unit

A B nG select

4

Zero Detect

MF select

nn

nF

MUX F

H select2

n

A BS2:0 || Cin

A rithmetic/logicunit (A LU)

G

BS

Shifter

H

MUX

0

1

2

3

MUX

0

1

2

3

0 1 2 3

Decoder

Load

Load

Load

Load

Load enable

Write

D data

D address2

Destination select

Constant in

MB select

A select

A address

B select

B address

R3

R2

R1

R0

Bus Dn

Data in

ILIR0 0

0 1

Microoperation: R0 ← R1 + R2

Datapath Example: Performing a Microoperation

Apply 01 to A select to place

contents of R1 onto Bus A

Apply 10 to B select to place

contents of R2 onto B data and

apply 0 to MB select to place

B data on Bus B

Apply 0010 to G select to perform

addition G = Bus A + Bus B

Apply 0 to MF select and 0 to MD

select to place the value of G onto

BUS D

Apply 00 to Destination select to

enable the Load input to R0

Apply 1 to Load Enable to force the

Load input to R0 to 1 so that R0 is

loaded on the clock pulse (not shown)

The overall microoperation requires

1 clock cycle


Lecture 8

9

Arithmetic/Logic Unit (ALU)

ALU:

— A combinational ckt

— Block diagram:

mode select

S2 = 0: arithmetic ops

S2 = 1: logic ops

— Design of the ALU:

1. Design the arithmetic section

2. Design the logic section

3. Combine the two sections


Lecture 8

10

There are only four functions of B to select as Y in G = A + Y + Cin:

Y

— 0

— B

— B

— 1

What functions are implemented with carry-in to the adder?

Arithmetic Circuit (1/5)

Cin = 0 Cin = 1

G = A

G = A + 1

G = A – 1

G = A + B

G = A

G = A + B

G = A + B + 1

G = A + B + 1

S1

S0

Bn

B inputlogic

nA

n

X

Cin

Y

nG X Y Cin

Cout

n-bitparalleladder

All 0’s

All 1’s


Lecture 8

11


Adding selection codes to the functions of B:

The useful arithmetic functions are labeled in the table.

Note that all four functions of B produce at least one useful function.

= =


Lecture 8

12


Block diagram:

Arithmetic circuit

C0

X + Y + C0


Lecture 8

13


Circuit design:

Select G

S1 S0 Cin = 0 Cin = 1

0 0 A A + 1

0 1 A + B A + B + 1

1 0 A + B A + B + 1

1 1 A 1 A

Select G = X + Y + C0

S1 S0 Cin = 0 Cin = 1

0 0 A + 0 + 0 A + 0 + 1

0 1 A + B + 0 A + B + 1

1 0 A + B + 0 A + B + 1

1 1 A + 1…1 + 0 A + 1…1 + 1

X = A

Y = S1S0 0 + S1S0 B

+ S1S0 B + S1S0 1

C0 = Cin


Lecture 8

14


B input logic for one stage of arithmetic ckt:

X = A

Y = S1S0 0 + S1S0 B

+ S1S0 B + S1S0 1

C0 = Cin


Lecture 8

15

A 4-bit Arithmetic CKT

Xi = Ai

Yi = Bi S0 + Bi S1

C0 = Cin


Lecture 8

16

Logic Circuit

One stage of logic ckt:


Lecture 8

17

Arithmetic Logic Unit (ALU)

Function Table:


Lecture 8

18

Arithmetic Logic Unit (ALU)

The next most significant select signals, S0 for the arithmetic circuit and S1

for the logic circuit, are wired together, completing the two select signals for

the logic circuit.

The remaining S1 completes the three select signals for the arithmetic circuit.


Lecture 8

19

Direction: Left, Right

Number of positions with examples:

— Single bit:

1 position

0 and 1 positions

— Multiple bit:

1 to n – 1 positions

0 to n – 1 positions

Filling of vacant positions

— Many options depending on instruction set

— Here, will provide input lines or zero fill

Combinational Shifter Parameters


Lecture 8

20

4-Bit Basic Left/Right Shifter

Serial Inputs:

— IR for right shift

— IL for left shift

Serial Outputs

— R for right shift (Same as MSB input)

— L for left shift (Same as LSB input)

Shift Functions:

(S1, S0) = 00 Pass B unchanged

01 Right shift

10 Left shift

11 Unused

B 3

I R I L

S

Serial

output L

Serial

output R

2

B 2 B 1

B 0

H 0 H 1

H 2 H 3

S

M

U

X

0 1 2 S

M

U

X

0 1 2 S

M

U

X

0 1 2 S

M

U

X

0 1 2


Lecture 8

21

Barrel Shifter (1/2)

A rotate is a shift in which the bits shifted out are inserted into the positions vacated.

The circuit rotates its contents left from 0 to 3 positions depending on S: S = 00 position unchanged S = 10 rotate left by 2 positions S = 01 rotate left by 1 positions S = 11 rotate left by 3 positions

See Table 10-3 in text for details

D 3

S 0

3 S 1 S 0

M U X

D 2 D 1 D 0

Y 0 Y 1 Y 2 Y 3

S 1

0 1 2 3 S 1 S 0

M U X

0 1 2 3 S 1 S 0

M U X

0 1 2 3 S 1 S 0

M U X

0 1 2


Lecture 8

22

Barrel Shifter (2/2)

— E.g.: 4-bit Barrel shifter


Lecture 8

23 23

Datapath Representation (1/3)

Block diagram of datapath:


Lecture 8

24


Have looked at detailed design of

ALU and shifter in the datapath

on previous slide.

Here we move up one level in the

hierarchy from that datapath.

The registers, and the multiplexer,

decoder, and enable hardware for

accessing them become a register

file .

The ALU, shifter, Mux F and

status hardware become a

function unit.

The remaining muxes and buses

which handle data transfers are at

the new level of the hierarchy.

Address out

Data out

Constant in

MB select

Bus A

Bus B

FS

V

C

N

Z

MD select

n

D data

Write

D address

A address B address

A data B data

2 m x

n Register file

m

m

m

n

n

n

n

n

A B

Function unit

F

4

MUX B

1 0

MUX D

0 1

n

n Data in


Lecture 8

25


In the register file:

— Multiplexer select inputs become A

address and B address.

— Decoder input becomes D address

— Multiplexer outputs become A data

and B data.

— Input data to the registers becomes

D data.

— Load enable becomes write.

The register file now appears like a

memory based on clocked flip-flops

(the clock is not shown).

The function unit labeling is quite

straightforward except for FS.

Address out

Data out

Constant in

MB select

Bus A

Bus B

FS

V

C

N

Z

MD select

n

D data

Write

D address

A address B address

A data B data

2 m x

n Register file

m

m

m

n

n

n

n

n

A B

Function unit

F

4

MUX B

1 0

MUX D

0 1

n

n Data in


Lecture 8

26

Boolean Equations:

MFS = F3 F2

GSi = Fi

HSi = Fi

FS(3:0)

MF

Select

G

Select(3:0)

H

Select(1:0) Micr ooperation

0000 0

0000 XX

0001 0 0001 XX

0010 0 0010 XX

0011 0 0011 XX

0100 0 0100 XX

0101 0 0101 XX

0110 0 0110 XX

0111 0 0111 XX

1000 0 1 X 00

XX

1001 0 1 X 01

XX

1010 0 1 X 10

XX

1011 0 1 X 11

XX

1100 1 XXXX 00

1101 1 XXXX 01

1110 1 XXXX 10

F A

F A 1

+

F A B

F A B 1

F A B

F A B 1

F A 1

F A

F A B

F A B

F A B

F A

F B

F sr B

F sl B

+

+ +

+

+ +

Definition of Function Unit Select (FS) Codes

Shifter


Lecture 8

27

The Control Word

The datapath has many control inputs.

The signals driving these inputs can be defined and

organized into a control word.

To execute a microinstruction, we apply control word

values for a clock cycle. For most microoperations, the

positive edge of the clock cycle is needed to perform the

register load.

The datapath control word format and the field definitions

are shown on the next slide.


Lecture 8

28

The Control Word Fields

Fields

— DA – D Address

— AA – A Address

— BA – B Address

— MB – Mux B

— FS – Function Select

— MD – Mux D

— RW – Register Write

The connections to datapath are shown on the next slide.

Control word

D A AA BA

M

B

FS

M

D

R

W

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Lecture 8

29

Control Word Block Diagram

10

8

14

0

13

11

Bus D

Constant in

n

n

MUX B

1 0

D data Write

D address

A address B address

A data B data

8 x n

Register file

A B

Function

unit

n

n

n

MUX D

0 1

n

n Data in

Bus A

Bus B

R W

12

AA

15

D A

n

BA

9

Address out

Data out

V

C

N

Z

7

MD 1

MB

6

4 FS

5

3

2

A specific version of

the datapath:

— 8 regs

— 16 binary control inputs

7 fields

a control word

a particular -op


Lecture 8

30

F A

Encoding of Control World

D A , AA, B A MB FS MD R W

Function Code Function Code Function Code Function Code Function Code

R 0 000 Register 0 0000 Function 0 No write 0

R 1 001 Constant 1 0001 Data In 1 Write 1

R 2 010 0010

R 3 011 0011

R 4 100 0100

R 5 101 0101

R 6 110 0110

R 7 111 0111

1000

1001

1010

1011

1100

1101

1110

F A

F A 1

+

B

F A B 1

F A B

F A B 1

F A 1

F A

F A B

F A B

F A B

F A

F B

F sr B

F sl B

+

+ +

+

+ +

Control Word Encoding


Lecture 8

31

Microoperations for the Datapath

D A A A B A M B F S M D R W

R 1 R 2 R 3 R e g ister F unction Write

R 4 — R 6 R e g ister F unction Write

R 7 R 7 — Re gister Function Write

R 1 R 0 — Con s tant Func tio n Write

—— R 3 R eg i s t e r — — N o Wr it e

R 4 —— — — Data in Write

R 5 R 0 R 0 R e g ister F unction Write

R 1 R 2 R 3 – F A B 1 + + =

R 4 s l R6 F sl B =

R 7 R 7 1 + F A 1 + =

R 1 R 0 2 + F A B + =

Data out R 3

R 4 D ata in

R 5 0 F A B

=

D A A A B A M B F S M D R W

0 0 1 0 1 0 011 0 010 1 0 1

10 0 XX X 110 0 111 0 0 1

11 1 1 11 XXX 0 000 1 0 1

00 1 0 00 XXX 1 001 0 0 1

XX X X XX 011 0 XXX X X 0

10 0 XX X XXX X XXX X 1 1

1 0 1 0 0 0 000 0 101 0 0 1

R 1 R 2 R 3 –

R 4 s l R6

R 7 R 7 1 +

R 1 R 0 2 +

Data out R 3

R 4 D ata in

R 5 0

Microoperation

Microoperation

——

—


Lecture 8

32

Datapath Simulation

1 4 7 1 0 4 5

2 0 7 0

3 6 0 3 0

X X

2 0 7 0

3 6 0 2 3 0

14 1 2 0 10

2 0 0 1 X

18 18

1 255 2

2

3

4 12 18

5 0

6

7 8

Clock

DA

1 4

A A

2

BA

3 6

Constant_in 2

MB

A ddress_out

Data_out

FS

5

Status_bits

Data_in

MD

RW

reg0 0

reg1

reg2

reg3

reg4

reg5

reg6

reg7

7 8

5

R1 R2 + R3 +1

R4 sl R6

R7 R7 +1

R1 R0 +2

Data out R3

R4 Data in

R5 0

VCNZ


Lecture 8

33

A Simple Computer Architecture

Programmable system

— A programmable system uses a sequence of

instructions to control its operation.

Three forms of the HW organization of a

computer:

i. Conventional datapath + hardwired control

ii. Conventional datapath + -p control

iii. Pipelined datapath + pipelined control


Lecture 8

34

An typical instruction specifies:

— Operation to be performed

— Operands to use, and

— Where to place the result, or

— Which instruction to execute next

Instructions are stored in RAM or ROM as a program

The addresses for instructions in a computer are provided by a program counter (PC) that can

— Count up

— Load a new address based on an instruction and, optionally, status information

The PC and associated control logic are part of the Control Unit.

Executing an instruction - activating the necessary sequence of operations specified by the instruction

Execution is controlled by the control unit and performed:

— In the datapath

— In the control unit

— In external hardware such as memory or input/output

Instruction Set Architecture (1/2)


Lecture 8

35

Instruction Set Architecture (2/2)

Instructions: (assembly language level)

— Instruction:

a collection of bits that instructs the computer to perform a

specific op

operation code (opcode), operands

— Instruction set:

the collection of instrs for a computer

— Instruction set architecture (ISA):

a thorough description of the instr set

— Program:

A list of instrs that specifies the ops, the operands, and the

sequence in which processing is to occur.


Lecture 8

36

Storage Resources

The storage resources are "visible" to the programmer at the

lowest software level (typically, machine or assembly language).

Storage resources

for the SC =>

Separate instruction and

data memories imply

"Harvard architecture"

Done to permit use of

single clock cycle per

instruction implementation

Due to use of "cache" in

modern computer

architectures, is a fairly

realistic model

Instruction memory

2 15 x 16

Data memory

2 15 x 16

Register file

8 x 16

Program counter

(PC)


Lecture 8

37

Instruction Format (1/5)

A instruction consists of a bit vector.

The fields of an instruction are subvectors representing

specific functions and having specific binary codes

defined.

The format of an instruction defines the subvectors and

their function.

An ISA usually contains multiple formats.

The SC ISA contains the three formats presented on the

next slide.


Lecture 8

38


The three formats are: Register, Immediate, and Jump and Branch.

All formats contain an Opcode field in bits 9 through 15.

The Opcode specifies the operation to be performed.

More details on each format are provided on the next three slides.

(c) Jump and Branch

(a) Register

Opcode

Destination register (DR)

Source register A (SA)

Source register B (SB)

15 9 8 6 5 3 2 0

(b) Immediate

Opcode

Destination register (DR)


15 9 8 6 5 3 2 0

Operand (OP)

Opcode


15 9 8 6 5 3 2 0

Address (AD) (Right)

Address (AD) (Left)


Lecture 8

39


This format supports instructions represented by:

— R1 ← R2 + R3

— R1 ← sl R2

There are three 3-bit register fields:

— DR - specifies destination register (R1 in the examples)

— SA - specifies the A source register (R2 in the first example)

— SB - specifies the B source register (R3 in the first example and R2

in the second example)

Why is R2 in the second example SB instead of SA?

— The source for the shifter in our datapath to be used in

implementation is Bus B rather than Bus A

(a) Register

Opcode

Destination

register (DR)

Source reg-

ister A (SA)

Source reg-

ister B (SB)

15 9 8 6 5 3 2 0


Lecture 8

40


(b) Immediate

Opcode

Destination

register (DR)

Source reg-

ister A (SA)

15 9 8 6 5 3 2 0

Operand (OP)

This format supports instructions described by:

— R1 ← R2 + 3

The B Source Register field is replaced by an Operand field OP

which specifies a constant.

The Operand:

— 3-bit constant

— Values from 0 to 7

The constant:

— Zero-fill (on the left of) the Operand to form 16-bit constant

— 16-bit representation for values 0 through 7


Lecture 8

41


This instruction supports changes in the sequence of instruction

execution by adding an extended, 6-bit, signed 2s-complement

address offset to the PC value.

The 6-bit Address (AD) field replaces the DR and SB fields

— Example: Suppose that a jump is specified by the Opcode and the PC

contains 45 (0…0101101) and Address contains – 12 (110100). Then

the new PC value will be:

0…0101101 + (1…110100) = 0…0100001 (45 + (– 12) = 33)

The SA field is retained to permit jumps and branches on N or Z

based on the contents of Source register A.

(c) Jump and Branch

Opcode

Source reg-

ister A (SA)

15 9 8 6 5 3 2 0

Address (AD)

(Right)

Address (AD)

(Left)


Lecture 8

42

Instruction Specifications (1/2)

The specifications provide:

— The name of the instruction

— The instruction's opcode

— A shorthand name for the opcode called a mnemonic

— A specification for the instruction format

— A register transfer description of the instruction, and

— A listing of the status bits that are meaningful during an

instruction's execution (not used in the architectures defined in

this chapter)


Lecture 8

43

Instruction Specifications (2/2)

R[DR] M[R[SA]]

M[R[SA]] R[SB]


Lecture 8

44

Example of Instructions and Data in Memory

Memory Repr esentation of Instruc t ions and Data

D eciimal

Ad d r ess Mem o r y C ontents

Dec i mal

Op cod e Other F i elds Op eration

25 00001 01 001 010 011 5 (Subtract) DR:1, SA:2, SB:3 R1 R2

R3

35 01000 00 000 100 101 32 (Store ) S A:4, SB:5 M[ R4] R5

45 10000 10 010 111 011 66 (Add

Im mediate)

DR: 2 , S A : 7 , OP :3 R 2 R7

+3

55 11000 00 101 110 100 96 (Branch

on Z e ro )

AD: 44, SA:6 If R6 = 0,

PC PC

20

70 000 000000110 00000 Data = 1 92. Aft e r execution of instruction in 35,

Data = 8 0 .

Suppose R4 contains 70 and R5 contains 80.


Lecture 8

45

Computer Operation: — is specified by an instr stored in binary, in the

computer’s memory.

— How does the control unit execute an op? The control unit in the computer uses the addr or addrs

provided by the program counter to retrieve the instr from mem.

It then decodes the opcode bits and other information in the instr to perform the required -ops for the execution of the instr.

Microoperation: — is specified by the bits in a control word produced

by hardware or read from control memory.

Computer op vs Hardware u-op


Lecture 8

46

Single-Cycle Hardwired Control

Based on the defined ISA, a computer

architecture is designed to support the ISA.

The architecture is to fetch and execute each

instruction in a single clock cycle.

The datapath from Figure 10-11 will be used.

The control unit will be defined as a part of the

design.

The block diagram is shown on the next slide.


Lecture 8

47

BusA Bus B

A ddress out

Data outMW

Data in

MUX B

1 0

MUX D0 1

DATA PATH

RWDA

A A

Constant�in

BA

MB

FS

V

C

N

Z

Function�unit

A B

F

MDBus D

IR(2:0)

Data in A ddress

Data�memory

Data out

DRegister

fileA B

Instructionmemory

A ddress

Instruction

Zero fill

DA

BA

AA

FS

MD

RW

MW

MB

Instruction decoder

JB

Extend

LP B

C

BranchControl

VCNZ

JBL

P BC

IR(8:6) || IR(2:0)

PC

CONTROL

Jump A ddress


Lecture 8

48

The Control Unit

The Data Memory has been attached to the Address Out and

Data Out and Data In lines of the Datapath.

The MW input to the Data Memory is the Memory Write signal

from the Control Unit.

For convenience, the Instruction Memory, which is not usually a

part of the Control Unit is shown within it.

The Instruction Memory address input is provided by the PC and

its instruction output feeds the Instruction Decoder.

Zero-filled IR(2:0) becomes Constant In

Extended IR(8:6) || IR(2:0) and Bus A are address inputs to the

PC.

The PC is controlled by Branch Control logic.


Lecture 8

49

PC Function (1/2)

PC function is based on instruction specifications involving jumps and

branches:

In addition to the above register transfers, the PC must also

implement: PC ← PC + 1

The first two transfers above require addition to the PC of: Address

Offset = Extended IR(8:6) || IR(2:0)

The third transfer requires that the PC be loaded with: Jump Address

= Bus A = R[SA]

The counting function of the PC requires addition to the PC of 1.

Branch on Zero BRZ if (R[ S A] = 0) PC

← PC + s e A D

Branch on Negative BRN if (R[ S A] < 0) PC PC + s e A D

J u mp JMP P C R[SA ]

←

←


Lecture 8

50

PC Function (2/2)

Branch Control determines the PC transfers based on five of its

inputs defined as follows:

— N,Z – negative and zero status bits

— PL – load enable for the PC

— JB – Jump/Branch select: If JB = 1, Jump, else Branch

— BC – Branch Condition select: If BC = 1, branch for N = 1, else

branch for Z = 1.

The above is summarized by the following table:

Sufficient information is provided here to design the PC.

PC Operation PL JB BC

Count Up 0 X X

Jump 1 1 X

Branch on Negative (else Count Up) 1 0 1

Branch on Zero (else Count Up) 1 0 0


Lecture 8

51

Encoding of Control Word


Lecture 8

52

Instruction Decoder (1/5)

The combinational instruction decoder converts the instruction into

the signals necessary to control all parts of the computer during the

single cycle execution.

The input is the 16-bit instruction.

The outputs are control signals:

— Register file addresses DA, AA, and BA,

— Function Unit Select FS

— Multiplexer Select Controls MB and MD,

— Register file and Data Memory Write Controls RW and MW, and

— PC Controls PL, JB, and BC

The register file outputs are simply pass-through signals:

— DA = DR, AA = SA, and BA = SB

Determination of the remaining signals is more complex.


Lecture 8

53


The remaining control signals do not depend on the addresses, so

must be a function of IR(15:9).

Formulation requires examining relationships between the outputs

and the opcodes.

Observe that for other than branches and jumps, FS = IR(12:9)

This implies that the other control signals should depend as much as

possible on IR(15:13) (which actually were assigned with decoding in

mind!).

To make some sense of this, we divide instructions into types as

shown in the table on the next page


Lecture 8

54


T ruth T a ble for Instruction Decoder Logic

Instruction Function T ype

Instruction Bits Contr ol W o r d Bits

15 14 13 9 M B M D R W M W P L J B B C

Function unit operations using

registers

0 0 0 X 0 0 1 0 0 X X

Memory read 0 0 1 X 0 1 1 0 0 X X

Memory write 0 1 0 X 0 X 0 1 0 X X

Function unit operations using

register and constant

1 0 0 X 1 0 1 0 0 X X

Conditional branch on zero (Z) 1 1 0 0 X X 0 0 1 0 0

Conditional branch on negative (N) 1 1 0 1 X X 0 0 1 0 1

Unconditional J ump 1 1 1 X X X 0 0 1 1 X


Lecture 8

55


The types are based on the blocks controlled and the seven signals to be

generated; types can be divided into two groups:

— Datapath and Memory Control (First 4 types)

— PC Control (Last 3 types)

In Datapath and Memory Control blocks controlled are considered:

— Mux B (1st and 4th types)

— Memory and Mux D (2nd and 3rd types)

— By assigning codes with no or only one 1 for these, implementation of MB, MD,

RW and MW are simplified.

In Control Unit more of a bit setting approach was used:

— Bit 15 = Bit 14 = 1 were assigned to generate PL.

— Bit 13 values were assigned to generate JB.

— Bit 9 was used as BC which contradicts FS = 0000 needed for branches. To

force FS(6) to 0 for branches, Bit 9 into FS(6) is disabled by PL.

Also, useful bit correlations between values in the two groups were

exploited in assigning the codes.


Lecture 8

56


The end result by use of

the types, careful

assignment of codes,

and use of don't cares,

yields very simple logic:

This completes the

design of most of the

essential parts of

the single-cycle

simple computer

19 – 17

DA

16 – 14

AA

13 – 11

BA

10

MB

9 – 6

FS

5

MD

4

RW

3

MW

2

PL

1

JB

0

BC

Instruction

Opcode DR SA SB

Control word

15 14 13 12 11 10 9 8 – 6 5 – 3 2 – 0


Lecture 8

57

Sample Instruction Execution

Decoding, control inputs and paths shown for ADI, LD

and BRZ on next 6 slides


Lecture 8

58

Decoding for ADI

19 – 17

DA

16 – 14

AA

13 – 11

BA

10

MB

9 – 6

FS

5

MD

4

RW

3

MW

2

PL

1

JB

0

BC

Instruction

Opcode DR SA SB

Control word

15 14 13 12 11 10 9 8 – 6 5 – 3 2 – 0

1 0 0 0 0 1 0

1 1 0 0 1 0 0 0 0 0 0


Lecture 8

59

Bus A Bus B

Address out

Data out MW

Data in

MUX B

1 0

MUX D

0 1

DATAPATH

RW DA

AA

Constant in

BA

MB

FS

V

C

N

Z

Function unit

A B

F

MD Bus D

IR(2:0)

Data in Address

Data memory

Data out

Register file

D

A B

Instruction memory

Address

Instruction

Zero fill

D A

B A

A A

F S

M D

R W

M W

M B

Instruction decoder

J B

Extend

L

P

B C

Branch Control

V C N Z

J B L

P B C

IR(8:6) || IR(2:0)

PC

CONTROL

Control Inputs and Paths for ADI

1 1

0 0

1 0

0 0 0 0 0 0 0 1 0

1

0

1

0

0 0 0

+

No Write

Increment

PC


Lecture 8

60

Decoding for LD

19 – 17

DA

16 – 14

AA

13 – 11

BA

10

MB

9 – 6

FS

5

MD

4

RW

3

MW

2

PL

1

JB

0

BC

Instruction

Opcode DR SA SB

Control word

15 14 13 12 11 10 9 8 – 6 5 – 3 2 – 0

0 0 1 0 0 0 0

0 1 0 0 0 0 1 0 0 1 0


Lecture 8

61

Bus A Bus B

Address out

Data out MW

Data in

MUX B

1 0

MUX D

0 1

DATAPATH

RW DA

AA

Constant in

BA

MB

FS

V

C

N

Z

Function unit

A B

F

MD Bus D

IR(2:0)

Data in Address

Data memory

Data out

Register file

D

A B

Instruction memory

Address

Instruction

Zero fill

D A

B A

A A

F S

M D

R W

M W

M B

Instruction decoder

J B

Extend

L

P

B C

Branch Control

V C N Z

J B L

P B C

IR(8:6) || IR(2:0)

PC

CONTROL

Control Inputs and Paths for LD

0 1

0 0

0 0

1 0 0 1 0 0 0 0 0

0

1

1

0

0 1 0

No Write

Increment

PC


Lecture 8

62

Decoding for BRZ

19 – 17

DA

16 – 14

AA

13 – 11

BA

10

MB

9 – 6

FS

5

MD

4

RW

3

MW

2

PL

1

JB

0

BC

Instruction

Opcode DR SA SB

Control word

15 14 13 12 11 10 9 8 – 6 5 – 3 2 – 0

1 1 0 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0


Lecture 8

63

Bus A Bus B

Address out

Data out MW

Data in

MUX B

1 0

MUX D

0 1

DATAPATH

RW DA

AA

Constant in

BA

MB

FS

V

C

N

Z

Function unit

A B

F

MD Bus D

IR(2:0)

Data in Address

Data memory

Data out

Register file

D

A B

Instruction memory

Address

Instruction

Zero fill

D A

B A

A A

F S

M D

R W

M W

M B

Instruction decoder

J B

Extend

L

P

B C

Branch Control

V C N Z

J B L

P B C

IR(8:6) || IR(2:0)

PC

CONTROL

Control Inputs and Paths for BRZ

1 0

0 0

0 0

0 1 0 0 0 0 0 0 0

1

0

0

0

1 0 0

No Write

Branch on

Z

No Write


Lecture 8

64

[R3] = 248, M[248] = 2, M[249] = 83

M[250] 83 - (2 + 3)

LD R1, R3 ;R1 M[R3] (R1 = 2)

ADI R1, R1, 3 ;R1 R1 + 3 (R1 = 5)

NOT R1, R1 ;Complement R1

INC R1, R1 ;R1 R1 + 1 (R1 = 5)

INC R3, R3 ;R3 R3 + 1 (R3 = 249)

LD R2, R3 ;R2 M[R3] (R2 = 83)

ADD R2, R2, R1 ;R2 R2 + R1 (R2 = 78)

INC R3, R3 ;R3 R3 + 1 (R3 = 250)

ST R3, R2 ;M[R3] R2 (M[250] = 78)

Program Sample


Lecture 8

65

Single-Cycle Computer Issues

Worse case delay path in a single-cycle computer:


Lecture 8

66

i. in the area of performing complex

ops multiple-cycle control

ii. with instrs and data in the same

memory multiple-cycle control

iii. has a lower limit on the clock

period based on a long worst case

delay path • 17 ns 58.8 MHz

pipelined control

Shortcomings of a Single-Cycle Computer


Lecture 8

67

Summary

Datapath:

— Major components:

Register files,

Buses,

ALUs,

Shifters

— Control word

Control design for programmed systems

— Single-cycle computer

Documents

Computer Design Basicsviplab.cs.nctu.edu.tw/course/DSD2015_Spring/DSD_Lecture_08.pdf · Digital Systems Design Lecture 8 3 Outlines Introduction Datapaths The Arithmetic/Logic Unit