Computer Architect

7/30/2019 Computer Architect

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Q. 1. What is Computer Architecture?

Ans. Computer Architecture : It isconcerned with structure and behaviourof computer as seen by theY user. It includesthe information formats, the instruction set,and techniques for addressing meiihrchitecturaldesi of a computer system isconcerned with the specifications of the various

ftmctional modules, such as processors andmemories and structuring them together into acomputer system.

Q. 2. What is Computer Organisation?

Ans. Computer Organisation: It isconcerned with the way the hardwarecomponents operate and the way they areconnected together to form the computersystem. The various components are assumedto be in place and the task is to investigate theorganisational structure to verify that thecomputer parts operate.


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Q. 3. What is the concept of layers inarchitectural design?

Ans. The concepts of layers in architecturaldesign is described as below:

1. Complex problems can be segmented intosmaller and more manageable form.

2. Each layer is specialized for specific

functioning.

3. Upper layers can share the services of alower layer. Thus layering allows us to reusefunctionality.

4. Team development is possible because oflogical segmentation. A team of programmerswill build. The system, and work has to be sub-divided of along clear boundaries.

Q. 4. Differentiate between computerarchitecture and computer organisation.

Ans. Difference between computerarchitecture and computer organisation:


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Q. 5. Draw top leveled view of computercomponents.

Ans. Computer organization includes emphasison system components, circuit design, logicaldesign, structure of instructions, computerarithmetic, processor control, assemblyprogramming and methods of performanceenhancement.


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Diagram : Top leveled view of computercomponent

Q. 6. Write typical physical realisations ofarchitecture.

Ans. Important types of bus architecture usedin a computer system are:

(i) PCI bus

(ii) ISA bus

(iii) Universal serial bus (USB)

(iv) Accelerated graphics port (AGP).


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PCI bus : PCI stands for peripheral componentinterconnect It was developed by intel. Tqdayit is a widely used bus arclirtecture. The PCI

bus can operate with either a 32 bits or 64 bitdata bus and a full 32-bit address bus.

ISA Bus : ISA stands for industry standardArchitecture. Most Pcs contain ISA slot on themain board to connect either an 8bit ISAcard or a 16bit ISA card.

USB : It is a high speed serial bus. It hashigher data .transfer rate than that of a serialport fashion. Several devices can be connectedto it in a daisy chain.

AGP: It is a 32bit expansion slot or busspecially design for video card.

Q. 7. What is Channel?

Ans. A channel is one of data transfertechnique. This technique is a traditionallyused on mainframe computers and alsobecoming more common on smaller systems.It controls multiple high speed devices. Itcombines the features of multiple and selector


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channels. This channel provides a connectionto a number of High speed devices.

Q. 8. Draw the machine architecture of8086.

Ans.

Q. 9. Explain about the computerOrganisation.

Ans. Computer organisation is concerned withthe way the hardware components operate andthe way they are connected together to form


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the computer system. The various componentsare assumed to be in place ad task is to be aorganisational structure. IL includes emphasis

on the system components, circuit design,logical design, structure of instruction,computer arithmetic, processor control,assembly programming and methods ofperformance enhancement.

Q. 10. Explain the signficance of layeredarchitecture

Ans. Significance of layered architecture: Inlayered architecture, complex problems can besegmerled into smaller and more managableform. Each layer is specialized for specificfunctioning. Team development is possiblebecause of logical segmentation. A team ofprogrammers will build. The system, and workhas to be sub-divided of along clearboundaries.

Q. 11. HOw can you evaluate theperformance of processor architecture.


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Ans. In processor architecture, there is no. ofprocessor where 8086 and 8088 has taken anaverage of 12 cycles to execute a single

instruction. XXX286 and XX386 are 4.5 cyclesper instruction XX486 and most fourthgeneration intel compatible processor such asDMD X 85, drop the rate further, about 2cycles per instruction. Latest processor arepentium pre, pentiom 11/111/4/celeron andAthlon/ Duress : These P6 and P7 processor S

can execute as many as three or moreinstructing per cycle.

Q. 12. Explain the various types ofperformance metrics.

Ans. Performance metrics include availability,response time, Channel capacity, latency,Completion time.

Q. 13. Write a short note on cost/benefitin layered Architecture design.

Or

H/W and S/W partitioning design:


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Ans. One common architectural design patternis based on layers. Layers are an architectural

design pattern that structures applications canbe decomposed into groups of subtasks suchthat each of subtasks is at a particular level ofabstraction.

A large system requires decomposition. Oneway to decompose a system is to segment it

into collaborating objects. Then these objectsare grouped to provide related types ofservices. Then these groups are interfaced witheach other for inter communication and thatresults in a layered architecture. Thetraditional 3tier client server model, whichseparates application functionality into three

distinct abstractions, is an example of layereddesign. The three layers include data, businessrules and graphical user interface. Similiar isthe 051 seven layer networking model andinternet protocol stack based on layeredarchitecture.

The following are the benefits of layeredarchitecture

1. Complex problems can be segmented intosmaller and more manageable form.


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2. Team development is possible because oflogical segmentation. A team of programmerswill build the system, and work has to be sub-

divided along cler boundaries.

3. Upper layers can share the services of alower layer. Thus layering allows us to reusefunctionality.

4. Each layer is specialized for specificfunctioning.

Late source code changes should not ripplethrough the system of layered architecture.The similar responsibilities should be groupedto help understandabilty and maintainability.Layers are implemented as software to isolate


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each disparate concept or technology. Thelayers should isolate at the conceptual level.By isolating the database from the

communication code, we can change one orthe other with minimum impact on each other.Each layer of the system deals with only oneconcept. The layered architecture can havemany beneficial effects on application, if it isapplied in proper way. The concept ofarchitecture is simple and easy to explain to

team members and so demonstrate whereeach objects role fits into the team. With theuse of layered architecture, the potential forreuse of many objects in the system cangreatly increased.

Q. 14. Explain the machine architecture of8085 processor.

Ans. The 8085 is 8-bit general micro processorcan address up to 64K words of memory. Itrequire 5V supply. It can operate at 3 MHZsingle phase clock. This processor is having 8-bit data bus and 16-bit address bus. Data busis multiplexed with address bus.


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That means 8-bit data bus is used as lower 8-bits of address bus whenever the address haveto carried in address bus.

The arithmetic logic unit includes 8-hitaccumulator, 8-bit temporary register,arithmetic and logic circuits and five plays.These five flags are used to indicate certainconditions such as overflow or carry that arisesduring arithmetic and logical operations. Thisprocessor has six general purpose named as B,

C, D, E, H and L. These registers can becombined in pairs as BC, DE and 1-IL in orderto perform 16-bit operations. The accurnulatoris named as A and one of the operand mayreside in accumulator register in an


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instructiOn. The stack pointer and programcounter is 16-bit. Stack pointer (SP) is used bythe programmer to maintain a stack in

memory. Program Counter (PC) is used tokeep track of the address of instruction inmemory that has to be executed next. Theincrement decrement address latch is also 16-bit.

The instruction of processor can be classified infollowing categories.

1. Data transfer

2. Arithmetic operations

3. Logical operations

4. Branching operations.

5. Machine control operations

6. Assembler directies.

Q. 15. Write a note on.

(a) VLIW Architecture (b) Super scalerprocessor.


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Ans. (a) Very long instruction word(VLIW) is a modification over super scalerarchitecture VLIW architecture implements

instruction level parallelism (ILP). VLIWprocessor fetches veiy long instruction workhaving several operations and dispatches it isparallel execution to different functional units.The width of instruction varies from 128 to1024 bits. VLIW architecture offers staticscheduling as super scalar architecture offers

dynamic (run time) scheduling. That meansview offers a defined plan of execution ofinstruction by functional units. Due to staticscheduling, VLIW architecture can handle up toeight operations per clock cycle. While superscaler architecture can handle up to fiveoperations at a time. VLIW architecture needs

the complete knowledge of Hardware likeprocessor and their functional units. It is fastbut inefficient for object oriented and eventdriver programming. In event driven andobject oriented programming super scalerarchitecture is used. Hence view and superscaler architecture are important in different

aspets.(b) Super Scaler Processor : The scalerprocessor executes one instruction on one set


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of operands at a time. The super scalerarchitecture allows the execution of multipleinstructions at the same time. In different

pipelines. Here multiple processing elementsare used for different instruction at the sametime. Pipelining is also implemented in eachprocessing elements.

The instruction fetching units fetch multipleinstructions at a time from cache.The instruction decoding unit check theindepedance of these instruction so that theycan be executed in parallel. There should bemultiple execution units so that multipleinstructions can be executed at same time. Theslowest stage among fetch, decode andexecute will determine the overall performanceof the system. Ideally these three stagesshould be equally fast. Practically executionstage in slowest and drastically affect theperformance of system.

Q. 16. Write a note on following:

(i) Pentium Processor - (ii) Server System


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Ans. (i) Pentium processor : Pentiumprocessor with super scaler architecture cameas modfication of 80486 and 8086. It is based

on CISC and uses two pipelines for integerprocessor so that two instructions areprocessed simultaneously one pipeline willhave same condition then another is comparedwith hardware 80486 processor had only adderin one chip floating point unit. One the otherside pentium processor is having adder,

multiplier and divide in on chip floating pointunit. That means pentiom processor can do themultiplication and division fastly. The separatedata and code cache of 8KB exits on chip. Dualindependent bus (DIB) architecture divides thebus as front side and backside bus. BacksideBus transfer the data from L2 Cache to CPU

and vice-versa. Front side bus is used totransfer the data from CPU to main memoryand to other components of system.

Pentium processor user write back policy forcache data, while 80486 uses writethrough policy for cache data. The detail other

common types of processor are AMD andcyrix Although these two types of processorare less powerful as compared toPentium Processor.


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(ii) Server System : System is formed asserver or client depending upon thesoftware used in that machine suppose window

2003 server operating system is installedon machine, that machine will be termed assever. If on the same machine Window 95 isinstaller that machine is termed as client.Although server machine uses specialisedhardware meant for faster processing serverprovides the service to other machine called

client attached to server. Different types ofservers are Network server, web server,database server, backup server. Sever systemis having powerful computing power,high performance and higher clock speed.These system are having good faulttolerance capability using disk mirroring, disk

stripping and RAID concepts. These systemhave back up power supply with hot swap. IBMand SUN servers are providing the differentserver of server for different use.

Q. 17. What is principle of performanceand scalability in Computer Architecture.

Ans. Computer Architecture have the goodperformance of computer system. It


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is implementing concurrency can enhance theperformance. The concept of concurrency canbe implemented as parallalism or multiple

processors with a computer system. Thecomputer performance is measured by thetotal time needed to execute applicationprogam. Another factor that affects theperformance is the speed of memory. That isreason the current technology processor ishaving their own cache memory. Scalability is

required in case of multiprocessor to havegood performance.

The scability means that as the cost ofmultiprocessor increase, the performanceshould also increase in proporation. The sizeaccess time and speed of memories and busesplay a major role in the performance of thesystem.

Q. 18. What is evaluation of computerarchitecture?

Ans. Computer Architecture involves bothhardware orgartisation and programmingsoftware requirements. At seen by anassembly language programmer, computer


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architecture is abstracted by an instruction set,which includes opcode (operation codes),addressing modes, register, virtual memory,

etc. from the hardware implementationpoint o1 view, the abstract machine isorganised with CPUs, caches, buses,microcode, pipelines physical memory etc.Therefore, the study of architecture coversboth instruction set architectures and machineimplementation organisation.

Over the past four decades, computerarchitecture has gone through evolutionrather than revolutional changes, sustainingfeatures are those that were provenperformance delivers. We started withNeumann architecture built as a sequentialmachine executing scalar data. The sequentialComputer was improved from bit servial toword-parallel operations, and from fixed pointto floating point operations. The vonNeumann architecture is slow due to sequentialexecution of in programs.

Q. 19. What is parallelism and 5ipeliningin computer Architecture?


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Ans. LOOK AHEAD, PARALLELISM , ANDPIPELINING IN COMPUTER ARCHITECTURE

Look ahead techniques were introduced toprefetch instruction in order to overlap I/F(Instruction fetch/decode and execution)operations and to enable functional parallelism.Functional parallelism was supported by twoapproaches : One is to use multiple functionalunits simultaneously and the other is topractice pipelining at various processing levels.

le latter includes pipelined instructionexecution, pipelined arithmetic corn pu ta tion,and memory access operations. Pipelining hasproven especially attractive inperformng identcial operations repeatedly overvector data strings. Vector operations were

originally carried out implicitly by softwarecontrolled looping using scaler pipelineprocessors.

Q. 20. How many cydes are required to

execute per instruction for 8086, 8088,intel 286, 386, 486, pentium, K6 series,pentium 11/111/4/cebron, andAthion/Athion XP/Duron?


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Ans. The time required to execute instructionsfor different processors are as follows:

8086 and 8088 : It has taken an average of12 cycles to execute a single instruction.

286 and 386 : It improve this rate to about4.5 cycles per instruction. 486 : The 486 andmost other fourth generation intel-compatibleprocessors, such as the DMD 5 x 86, drop therate further, to about 2 cycles per instruction.

Pentium, K6 Series,: The pentiumarchitecture and other fifth generationintel compatible processors, such as thosefrom AMD and cyrix, include twin instructionpipelines and other improvements that providefor operation at one or two instruction per

cycle.

Pentium pro, pentium II,fIII/4/celeron, andAthion/Athlon XP/Duron : These P6 and P7(Sixth and Seventh generation) processors canexecute as many as three or more instructionsper cycle.

Q. 21. What is cost/benefit in layeredArchitecture design?


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Or

Write functional view of computer whichare the possible computer operational.

Ans. A larger system require decomposition.Only way to decompose a system is tosegment it into collaborating objects. Theseobjects are grouped to provide related types ofservices. Then these groups are interfaced witheach other for inter communication and thatresults in a layered architecture.

The following are benefits of layeredarchitecture

1. Complex problems can be segmented into

smaller and more manageable form.2. Team development is possible because oflogical segmentation. A team of programmeswill build the system, and work has to besubdivied along clear boundaries.

3. Upper layer can share the services of a

lower layer. Thus layering allows us to reusefunctionalities.

4. Each layer is specialized for specificfunctioning.


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5. Late source code changes should not ripplethrough the system because of layeredarchitecture.

6. Similar responsibilities should be grouped tohelp understability and maintainability.

7. A message that moves downwards betweenlayers is called request. A client issues arequest to layer. I suppose layer I cannot fulfillit, then it delegates to layer J1.

8. Messages that moves upward betweenlayers are called notifications. A notificationcould start at layer I. Layer I then formulatesand sends a message (notification) to layer j+1.

9. Layers are logical placed to keep informationcaches. Requests that normally travel downthrough several layers can be cached toimprove performance.

10. A systems programming interface is oftenimplemented as a layer. Thus if two applicationor inter application elements need to

communicate placing the interfaceresponsibilities into dedicated layers. Cangreatly simplify the task and make them moreeasily reusable.


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Layers are implemented as software to isolateeach disparate concept or technology. Thelayers should isolate at conceptual level. By

isolating the data base from the communicatecode, we can change one or the other withminimum impact on each other. Each layer ofthe system deals with only one concept.

The layered architecture can have manybeneficial effects on application, if it is appliedin proper way. The concept of the architectureis simple and easy to explain to team memberand so demonstrate where each objects rolefits into the team. With the use of layerarchitecture, the potential for reuse of manyobjects in the system can be greatly increase.The best benefit of this layering is that .malwsit easy to divide work along layer boundaries iseasy to assign different teams or individuals towork of coding the layers in layeredarchitectures, since the interfaces areidentified and understood well in advance ofcoding. Performance of system is measure ofspeed, throughput. Higher is cost involves for

manufacturing of computer, High is theperformance as shown in figure.


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Personal computer is cheapest in term of costamong server, mainframe and super computer.Super computer is the costliest one. Same isthe hierarchy for the performance of thesystem. Most of simple applications can be

executed on personal computers. For fasterprocessing server, mainframe and supercomputing are used. Sometimes usingtoo much I/O devices increases the cost butdecreasing the performance in personalcomputer. That is termed as diminishing theperformance with increase in the

cost/sublinear diminshing, Like SCSI adoplerincrease the cost of system but that alsoincreases the performance of server as termedas super linear economy in case of server. Theideal case is termed as linear representationwhere performance increases in the sameproportion of cost. These are represented in

graph shown in figure.Q. 1. Define ASCII code.


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Ans. ASCII stands for American Standard codefor Information Interchange. It is greatlyaccepted standard alphanumeric code used in

microcomputers. ACII of bit code represents 2128 different characters. These characterrepresent 26 upper case letter (A to Z), 26lowercase letters (a to z), 10 numbers (0 to 9),33 special characters, symbols and 33 controlcharacters. ASCII 7-bit code is divided into twoportions. The left most 3-bits portion is called

zone bits and the 4-bit portion on the right iscalled the numeric bits. ASCII 8-bit version canbe used to represent a maximum of 256characters.

Q. 2. What is EBCDIC?

Ans. EBCDIC stands for extended Binary codedDecimal interchange code. A standard codethat uses 8-bits to represent each of 256alphanumeric characters Extended Binarycoded Decimal interchange code is an 8-bitcharacter encoding used on IBM mainframesEBCDIC having eight bits code divided into twoparts. The first four, bits (on the left) are calledzone and represent the category of thecharacter and the last four bits (on the right)


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are called the digits and identify the specificcharacter.

Q. 3. Write a short note on: (i) Excess 3(ii) Gray code.

Ans. Excess 3 : Excess 3 is a non-weighted

code used to express decimal numbers. Thecode derives its name from the fact that eachbinary code is the corresponding 8421 codeplus 0021 (3). Excess representation ofdecimal numbers 0 to 9

Example

Gray Code : Gray coding is an important codeand is known for its speed. This code isrelatively free from the errors. In binary codingor 8421 BCD, counting from 7(0111) to 8(1

000) requires 4-bits to be chargedsimultaneously. Gray coding avoids this byfollowing only one bit changes betweensubsequent numbers.


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Q. 4. What is shift register in digitalcomputer.

Ans. Shift registers are the sequential logiccircuit used to shift the data from registers inboth directions. Shift registers are designed asa group of flip-flops connected together so thatthe output from one flip-flop becomes theinput to the next flip-flop. The flip-flop aredriven by a common clock signals and can beset or reset simultaneously. Shift registers canbe connected to form different type ofcounters.

Q. 5. Which logic name is known asuniversal logic?

Ans. NAND logic and NOR logic gates areuniversal logic. It is possible to implement anylogic expression by NAND and NOR gates. Thisis because NAND and NOR gates can be usedto perform each of Boolean operations INVERT,AND and OR. NAND is same as AND gatesymbol except that it has a small circle at


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output. This a small circle represents theuniversal operations.

Q.6. What is time known when D-input ofD-FE must not change after clock is

applied?

Q. 8. Addition of (1111)2 to 4-bit binaryA results:

(1) incrementing A (ii) Addition of (F)11

(iii) No change (iv) Decrementing A.


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Ans. Addition of (F)H

Q. 9. Register A holds the 8-bit binary11011001. Determine the B operand andthe logic micro-operation to be performedin order to change the value in A to:


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Q. 13. An 8-bit register R contain thebinary value 10011100 what is theregister value after an arithmetic shift

right? Starting from the initial number10011100, determine the register valueafter an arithmetic shift left, and statewhether there is an overflow.


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Q. 15. Write instruction (8085) to load0011 in accumulator. Decrement theaccumulator.

Ans.

Q. 16. Draw the flowchart for Add andsubstract operations.

Ans. The flow chart for hardware algorithm ispresented in figure. The two signs A and are

compared by an exclusive OR gate. If theoutput of the gate is 0, The signs are identical,if it is 1, the signs are different For an addoperation, identical signs dictate thatmagnitudes be added. For a substract


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operation, different signs dictate that themagnitude be added. The magnitudes areadded with a micro-operation EA A + B

Where EA is a register that combines E and A.The carry in E after the addition is an overflowif it is equal to 1. The value of E is transformedinto the add-overflow flip-flop AVF.

Q. 17. Write the Algorithm of addition andSubstraction numbers.


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Ans. Addition (A + B) and substraction ( A - B)in floating point numbers are performedaccording to the following Algorithm:

Step 1. If any of two numbers A or B is 0,then non-zero number is the result. Normalizethe result to represent it in computer format.

Step 2. Align the mantissa of both numbers sothat exponent value of both the numbers willbe same.

Step 3. Same exponent part can be taken outcommon to do addition or substractionbetween the mantissa of two numbers.

Step 4. The sum (MA + MB) x or difference(MA M5) X r(P0flt. Step 5. Normalise theresult.

Q. 18. Discuss the Booths Algorithm forbinary multiplication.

Ans. Booths multiplication algorithm is used tomultiply two signed and unsigned .number byusing 2s complement. Aiidrew D; Booth


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invented the algorithm. Booth invented thisapproach in a quest to find a fast way tomultiples numbers. In present technology

shifting was faster than addition. Thisalgorithm is based on the shifting and is fasterone. This algorithm works for signed andunsigned numbers both. Booths algorithmworks according to following steps:

Step 1. Convert the negative multiplier andnegative multiplicand to a binary number in 2scomplement representation If the multiplier ormultiplicand is positive, simply represent it intobinary representation.

Step 2. The multiplies and multiplicand areplaced in register QR and BR.

Step 3. Add Os to the.left of multiplier in aquantify equivalent to number of bits in themultiplicand and all these Os are stored inregister AC, which is being placed logically leftto QR register.

Step 4. Flip-Flop Q1, is placed logically to theright of least significant bit Q0 (right most bit)of register QR. Sequence Counter (SC) is set toa value equal to the bits in register QR(multiplier). Initially Q1 is set to value 0.


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Step 5. Check the two right most bit (Q0 Q1)of the resultant binary number.

If Q Q1 = 00 or Q0 Q1 = 11 then bits inregister AC, QR and Q1 are shifted to right asarithmetic shift right. The arithmetic shift rightdoes no change the sign bit (left most bit ofregister AC).

Else if Q0Q1 = 01, add the contents of BR toAC and result is stored in AC. Then arithmetic

shift right operation is applied on AC, QR andQ1.

Else if Q0 Q1= 1 0, substract the contents ofBR from AC and the result is stored in AC,substraction of BR from AC is performed byadding BR + I to AC. The arithmetic shift right

operation is applied on AC, QR, and Q1.

Step 6. Sequence counter (SC) isdecremented by value 1.

Step 7. Step 5 and 6 are repeated up to thefine sequence counter (SC) value is not 0. Step8. The final result of multiplication will be

stored in AC, QR, register pair in combination.


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Q. 19. Solve the multiply 4 x 9 by usingBooths Algorithm orMultiplication Algorithm.

Ans. Solution: The multiplier 9 (01001) isstored in register QR. Register AC isinitialized to zero i.e. 00000 (Ac is a 5-bitregister in this example). The flip-flop Q1 willbe initialised to 0. The multiplicand 4 (00100)

is stored in register BR. HereASHR standsarithmetic shift right Q0 flip-flop stores theright most bit of register QR in the previousstep. Substraction of BR register value is equalto adding BR+l according to 2s complementrules. This algorithm require the size of BR, QRand AC to be one bit more than the maximum

bits requires to represent multiplicand andmultiplier. In 4 x 9, 9 can be represented using4-bit. That is why QR, BR and AC are having 5-bit size


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register = 000100100. This value is binaryequivalence of 36.

Q. 20. Write short note on Fast Carry

adder.Ans. In fast carry adder, It devised faster wayto add two binary numbers by using carry look


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head adder. It work by creating two signals (Pand a) for each bit position The block basedadders include the carry to carry adder which

determining P and G values for each blockrather than each bit, the carry select adderwhich pregeneratessum and carry valve foreither possible carry input to block.

Q. 21. What are the different register usedin 8085 processor and what are the

various categories of instruction in 8085processor?

Or


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What are various issues for designing theinstruction set of a processor.

Ans. The 8085 is 8-bit general microprocessorcan address up to 64 K words of memory. Thisprocessor requires 5-volt power supply and canoperate at 3 MHz single- phase clock. Thisprocessor is having 8-bit data bus and 16-bitaddress bus data bus is multiplexed with

address bus. That means 8-bit data bus is usedas lower 8-bits of address but whenever theaddress have to be carried in address bus.

The arithmetic logic unit includes 8-bitaccumulator, 8-bit temporaryregister, arithmetic and logic circuits and fiveflags. These five flags are used to indicatecertain condition such as overflow or carry thatarises during arithmetic and logical operations.

This processor has six general purposeregisters named as B, C, D, E, H and L.These registers can be combined in pairs asBC, DE and HL in order to perform 16-bit

operations. The accumulated is named as Aand one of the operand may reside inaccumulator register in an instruction. Thestack pointer and program counter is 16-bitstack pointer (SP) is used by the programmer


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to maintain a stack in memory. Programcounter (PC) is used to keep track of theaddress of instruction in memory that has to

be executed next. The increment decrementlatch is also 16-bit.

The Instruction of processor can be classifiedin following categories.

1. Data Transfer

2. Arithmetic operations.

3. Logical operations.

4. Branching operations.


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5. Machine control operations

6. Assembler Directives

Each Instruction contains op-code and mayhave operands. The opcode is 8-bit andoperand can be stored in 8-bit or 16-bitregister pair.

Q. 22. What do you mean by errordetection and what are the differenttechniques used for error detection?

Ans. The data writing in memory should beaccurately written. That means the errorshould not be introduced while writing thedata. Similarly the error should not beintroduced during the transmission of data.Single bit error means that only one bit of thegiven data is changed from 0 to I or from I to

0. These types of errors are easy to detect andcorrect. Burst error mean that two or more bitsof data unit have changed from 0 to 1 or from1 to 0. These types of errors are difficult todetect and correct. The most common four


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methods used for error detection are : Verticalredundancy check (VRC), Longitudinalredundancy check (LRQ, cyclic redundancy

check (CRC) and check sum.

1. Vertical Redundancy check (VRC): Thismethod of error detection is also called paritycheck. In this method an extra bit called paritybit is appended at the end of data so that totalnumber of ls will become even. Suppose itwants to transmit 10100010. The paritygenerator counts the ls and appends. 1 asparity bit so that total number of ls in thatdata will be even. Hence data will become110100010.

At receiving end, even parities function checksthe number of ls to be even. If the numbers of

ls are not even, that mean data has beendamaged. This method is used for single biterror detection. The other system may be oddparity. That means to make total number of isto be old using odd parity generates.

2. Longitudinal Redundancy Check (LRC) :

To transmit four byte of date, each byte isstored at one line so that four bytes are storedin four lines one below the other as shownbelow:


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Now the fifth row called LRC is created bymaking. The parity of each column to be even.Then LRC is appended at the end of date and istransmitted to receiver. Similarly LRC of fourbyte date is checked at the receiving sides. Ifthere is difference in sending and receivingLRC, that means error has been introduced.LRC technique is used for detecting the bursterrors.

3. Cyclic Redundancy Check (CRC) : CRC isbased on the binary decision. In this technique,CRC remainder is appended at the end of data

so that resulting data is exactly divisible bybinary number. At the receiving end, the dateis divided by same binary number. If there isno remainder during division that means datahas correctly reached the destination. Whilethe remainder during division indicates thatdata have been, damaged during transmission.

CRC technique is used for detecting bursterrors.

4. Check Sum: Check sum generatorsubdivides the data unit into M segments


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such that each segments will have N-bits. Allthe segments using ls complement areadded together to get the sum. The sum is

complemented and is called checksum. Thechecksum is appended at the end of data. Thereceiver sub-divides the data unit includingchecksum field into M segments so that eachsegment will have N-bits exactly like thesender did all segments using is complementare added to get the sum. Then sum is

complemented If this value is zero, the data iscorrect. Else data requires the transmission.This techniques is also used for burst errordetection.

Q. 23. Write an algorithm of summation ofa set of numbers.

Ans. This sum is a sequential operation thatrequires a sequence of add and shift micro-operation. There is addition of n numbers can

be done with micro-operation by


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means of combinational circuit that performsthe sum all at once.

An array addition can implemented with a

combinational circuit. The argend and addendare i.e. a0, a1, a2, a3 ...a.

There are following steps of summation of aset of number.

Step 1. There is n-array, numbers which are

a1, a1, a2 .. .a so the result is in sum.Step 2. Input of a0, a2, a3,.. .a1 are given thecombinational logical circuit. It shows theresult.

Step 3. The output is takens in sum and sometime, a carry is produced.

Step 4. A carry is put in the carry flag. Thetotal result of sum is stored in SUM and carryis stored in CARRY.


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Q. 24. Write an algorithm of Addition.

Ans. Addition (A + B) in floating pointnumbers are performed according to followingalgorithm.

Step 1. If any of the two number A or B is 0,then non-zero number is the result. Normalice

the result to represent it in computer format.

Step 2. Align the mautissa of both numbers sothat exponent value of both the numbers willbe same.

Step 3. Same exponent part can be taken outcommon to do addition.

Step 4. The sum (MA + MB) x rP0t ordifference is (MA MB) .exponent

Step 5. Normalise the result.

Q. 25. Simplify the following Booleanfunctions using three variable map insum of product form.


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1.f(a,b,c)=(1,4,5,6,7)

2. f.(a, b, c) = E (0, 1, 5, 7)

3. f (a, b, c) = E (1, 2, 3, 6, 7)

4. f (a, Li, c) = (3, 5, 6, 7)

5.f(a, Li, c) Y(O, 2, 3,4,6)

Ans.


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Q. 25. Simplify the ( a, b, c, d) =(0,1,2,5,8,9,10) Boolean functions usingfour variable map in sum of product andproduct of sum form. Verify the results ofboth using truth table.

Ans. Sum of Product (SOP)

f(a,b,c,d) =E(O,1,2,5,8,9,1O)


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These are two 4-bit input A(A3, A2, A1, A0) B(B3, B2, B1, l3) and a 4-bit output D (D3,

D2,D, D0). The four inputs form A(A3, A2, A1,A0) are applied directly to X (X3 X2, X1, X0)

inputs of full adder. The four inputs from B (BB2 B1 B0) are connected to data input I of fourmultiplexer. The logic input 0 is connected todata input 12 oi four multiplexers.

The logic input I is connected to data input 13of four multiplexers. One of the four inputs ofmultiplexer as output is selected by twoselection lines S0 and S1. The outputs from allfour multiplexers are connected to the Y (Y3 Y2


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Y, Y0) inputs of full adder. The input carry Cmis applied to the carry input of the full adderFAI. The carry generated by adder is

connected to next adder and finally cout isgenerated. The output generated by full adderis represented by expression shown ahead.

Q. 26. Explain the De-Morgan's theorems.

De-Morgan theorem is applicable to n numberof variable. Where n can have value 2, 3, 4etc. De-Morgan theorem for three variables willbe shown ahead.

(AB+C) =A.B.C

(A.B.C) A+B+C

To prove the following identity

[(A + C). (B + D)] = A. C + B. D Let x =[(A + C). (B + D)]


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(A + C). (B + D) [De-Morgan theorem]

= (A. C) + (B. D) [De-Morgan theorem]

= A. C + B. D.

The truth table for the second expression isgiven ahead. The equivalent between theentries in column (A + B) and (A. B). Provethe 2nd theorem.

Q. 27. What is universality of NAND andNOR Gates?

Ans. It is possible implement any logicexpression using only NAND gates. Thisis because NAND gate can he used to perform

each of the Boolean operations INVERT, ANDand OR. NANI) is the same as the AND gatesymbol except that it has a small circle at theoutput. This small circle represents theinversion operation. Therefore the output


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expression of the input NAND gate is X =(A.B)

The INVERT, AND OR gates have beenconstructed using NAND gates.

NOR is the same as OR gate symbol exceptthat it has a small circle at the output Thesmall circle represents the inversion operation


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The Boolean expression and logic diagram oftwo input NOR gate is described ahead

NAND and NOR are universal gate. It canimplement any logic gate or circuit.


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Q. 28. Design a 4-bit binary incrementercircuit.

Ans. The 4-bit binary incrementer adds value1 to its previous value. This circuit can act asbinary counter. The four half address arecascaded serially. One input of least significantadder is connected to 1 and other input isconnected to least significant bit of A (A3, A2,

A1, A0) means A0. The sum bit appears as S0and carry C0 of this adder will be the one inputof next adder. The other input of next adderwill be A1. That will produce sum S1 and carryC1. The complete operation is as shown ahead.


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Q. 29. Register a is having S-bit number11011001. Determine the operand andlogic micro-operation to be performed in

order to change the value in A to.

(i) 01101101

(ii) 11111101

(iii) Starting from an initial value R =11011101, determine the sequence of

binary values in R after a logical shift left,followed by circular shift right, followedby a logical shift right and a circular shiftleft.

Ans. (1) 11011001 A Register

10110100 B Register

01101101 A register afteroperations.

The selective complement operationcomplements the bits in register A where thereis 1 in the corresponding bit of register B. Thisdoes not affect the bit value in A. Where thereare 0 in the corresponding bit of register B.

(ii) 11011001 A register

00100100 B register


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11111101 A register after operation.

The selective set operation sets the bit inregister A to 1. Where there is I incorresponding bit of register B. This does notaffect the bit value in. A where there are 0 incorresponding bit of register B.

(iii) 11011101 R register

10111010 R register after logical

shift left01011101 R register after circular

shift right

00101110 R register after logicalshift right

01011100 R register after circularshift left.

Q. 30. Design a 4-bit common bus totransfer the contents of one register to

other.

Solution. Common bus is a mean fortransferring the information from one register


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to other. The 4-bit common bus is constructedwith four multiplexers. The bus is not onlyused for transferring the information from

register to register but also used for transferinformation from register to memory, memoryto register and memory to memory.

The number of multiplexer are four becausethere are 4-bits in each register used in the

common bus. Moreover there are four registersnamed register A, register B, register C andregister D. The size of each multiplexer is 4 1because there are four register. There are twoselection lines S and S in the 4 x 1 multiplexer.


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These multiplexers select one of register andits contents are placed on the common bus.The register is selected as shown in function

table.

Suppose the selection line S1 =00 that meansthe selection line has selected register

A. A0 the least significant bit of register A isselected by MUX 1, A, the second least

significant bit of register A is selected byMUX2, A2 the third least significant bit ofregister A is selected by MUX3 and A3, themost significant bit of the register A. A isselected by MUX4. Because the value ofselection lines in each multiplexer is S1S0 =00. The A1, A2 and A.3 have not connected to

MUX2, MUX3 and MUX4 because that will makethe diagram to be visually complicated. InActual A1, A2 and A3 have been connected toMUX2, MUX3 and MUX4. Also C1, C2 and C3have been connected to MUX 2, MUX3 MUX4.


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That means ope bit data is selected by eachmultiplexer and is transferred to common bus.

Similarly whee selection S1 5o that meansthe register B is selected. The contents ofregister B will appear on common bus.

Similarly when selection S. S0 10, that meansthe register D is selected. The contents ofregister B will appear on common bus.

Similarly when selection S1 S0li, that meansthe register D is selected. The contents ofregister will appear on common bus.

Q. 31. Design 4-bit arithmetic circuit that

implements eight arithmetic operations.Ans. 4-bit arithmetic circuits constitute of fourmultiplexer of size 4 x and four full adders asshown in Figure 1.


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The required arithmetic micro-operation can beperformed by the combination of selection linesSo, S1 and C.

1. When S1 S0 = 00, 13input 0, How multiplexers are selected asoutput B(B3, B2, B1, B0) If Cm 0 the output D= A + B (Add). If Cm =1, the output D A + B+ C (Add with carry).

2 When S1 S = 01, I, input of

four multiplexers are selected as output B (B;B2 B1 B0). If cm =6the output D = A+ B(substract with Borrow). If C1n 1, the output D= A + B + 1 (Substract).


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These are two 4-bit input A(A3, A2, A1, A0) B

(B3, B2, B1, B0) and a 4-bit output D (D3,D21D, D0). The four inputs form A(A3, A2, A1,A0) are applied directly to X (X3 X2, X1, X0)inputs of full adder. The four inputs from B (B;B; B1 B) are connected to data input 13 of fourmultiplexer. The logic input 0 is connected todata input 2 of four multiplexers. The logic

input I is connected to data input 13 of fourmultiplexers. One of the four inputs ofmultiplexer as output is selected by twoselection lines S0 and S1. The outputs from allfour multiplexers are connected to the Y (Y3 Y2


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Y, Y0) inputs of full adder. The input carry Cmis applied to the carry input of the full adderFAI. The carry generated by adder is

connected to next adder and finally cout isgenerated. The output generated by full adderis represented by expression shown ahead.

D = X + y + C1

3. When S1 S0 = 10, 12 input of fourmultiplexer are selected as output (0000). If

Cm = 0, the output D = A (transfer A), If Cm=1, the output D = A +1 (increment).

4. When S1S0 =11, 13 input of fourmultiplexers are selected as output (1111) isequivalent to the 2s complement of 1. (2scomplement of binary 0001 is 1111). That

means adding 2s. Complement of I to A isequivalent to A - 1. If Cm =1, the output D A(transfer A). Transfer A micro operation hasgenerated twice.

Hence there are only seven distinct micro-operation

Q. 1. What do you mean by memoryhierarchy ? Briefly discuss.


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Ans. Memory is technically any form ofelectronic storage. Personal computer systemhave a hierarchical memory structure

consisting of auxiliary memory (disks), mainmemory (DRAM) and cache memory (SRAM). Adesign objective of computer system architectsis to have the memory hierarchy work asthrough it were entirely comprised of thefastest memory type in the system.

Q. 2. What is Cache memory?

Ans. Cache memory: Active portion ofprogram and data are stored in a fast small

memory, the average memory access time canbe reduced, thus reducing the execution timeof the program. Such a fast small memory isreferred to as cache memory. It is placed


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between the CPU and main memory as shownin figure.

Q. 3. What do you mean by interleavedmemory?

Ans. The memory is partitioned into a numberof modules connected to a common memory

address and data buses. A primary module is amemory array together with its own addresseddata registers. Figure shows a memory unitwith four modules.


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Q. 4. How many memory chips of4128x8)are needed to provide memory capacity of40 x 16.

Ans. Memory capacity is 4096 x 16

Each chip is 128 8

No. of chips which is 128 x 8 of 4096 x 16memory capacity

Q 5.Explain about main memory.


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Ans. RAM is used as main memory or primarymemory in the computer. This memory ismainly used by CPU so it is formed as primary

memory RAM is also referred as the primarymemory of computer. RAM is volatilememory because its contents erased up afterthe electrical power is switched off. ROM alsocome under category of primary memory. ROMis non volatile memory. Its contents will beretained even after electrical power is switched

off. ROM is read only memory and RAM isread-write memory.Primary memoryis the high speed memory. It can be accessedimmediately and randomly.

Q 6. What is meant by DMA?

Ans. DMA : The transfer of data between afast storage device such as magnetic disk andmemory is liputed by speed of CPU. Removingthe CPU from the path and letting theperipheral device manager the memory busesdirectly would improve speed of transfer. Thistransfer technique is called Direct my Access(DMA) During DMA transfer, the CPU i idle


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iiThhsno-eeRtmtofo buses. A DMAcontroller takes over the buses to manage thetransfer y nteI/O device and memory

Q. 7. Write about DMA transfer.

Ans. The DMA controller is among the othercomponents in a computer system. The CPUcommunicates with the DMA through theaddress and data buses with any interface unit.The DMA has its own address, which activateswith Data selection and One the DMA receivesthe start control command, it can start thetransfer between the peripheral device andCPU.

Q. 8. Explain about Inter leave memory.

Ans. The memory is to be partitioned into anumber of modules connected to a common


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memory address and data buses. A memorymodule is a memory array together with itsown address and data register. Each memory

array has its own address register and dataregister. The address registers receiveinformation from a common address bus anddata register communicate with a bidirectionaldata bus. The two least significant bits of theaddress can be used to distinguish betweenfour modules. The modular system permits one

module to initiate a memory access while withother modules are in the process of reading orwriting a word and each module is honor amemory requestind endent of the state of theother modules.

Q. 9 Differentiate among direct mappingand associate mapping.

Ans. Direct mapping : The direct mapped

cache is the simplest form of cache and easiestto check for a hit. There is only one possibleplace that any memory location can be cached,there is nothing to search. The line either


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contain the memory information it is lookingfor or it does not.

Associate mapping : Associate cache iscontent addressable memory. Thecache memory does not have its address.Instead this memory is being accessed usingits contents. Each line of cache memory willaccommodate the address and the contentsof the address from the main memory. Alwaysthe block of data is being transferred to cachememory instead of transferring the contents ofsingle memory location from main

Q 10. Define the terms: Seek time,Rotational Delay, Access time.

Ans .Seek time : Seek time is a time in whichthe drive can position its read/write ads overany particular data track. Seek time varies for

different accesses in tie disk. It is preferred tomeasure as an average seek time. Seek time isalways measured in milliseconds (ms).


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Rotational Delay: All drives 1bve rotationaldelay. The time that elapses between themoment when the read/we heal\settles over

the desired data track and the moment whenthe first byte of required data appearsunder the head.

Access time: Access time is simply the sumof the seek time and rotational latency time.

Q 11. What do you mean by DMA channel?

Ans. DMA channel: DMA channel is issued to

transfer data between main memory andperipheral device IrirdeTto perform thetransfer of data. The DMA controller accs rsaddress and data buses.

DMA with help of sthematic diagram ofcontroller ontile needs the sual circuits of

and e to communicate with - CPZJ and I/Odevice. In addition, it nee s an addressregister; aword count register, and a set of,esThe address register and address lines areused rec communication with memory to word


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count register specifies the no.of word that -must be trEia transfer may be done directlybetween the device and memory .

Figure 2 shows the block diagram of typicalDMA controlIer. The unit communicates withCPU via the data bus and control lines. Theregisters in the DMA are selected by


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-through the address bus by enablin DS DMARS (Register Select) mputse Icy iceaa) and riteinputs are bidirectional. When the G (Bus

Grant) fo CPU can communicate with DMAregister through the data bus to read from orwrite to the DMA registers. When BC = 1, theCPU has buses and DMA can communicatedirectly with memory by specifying an addressin address bus and activating orWR.ctrLil. TheDMA communicate with ex1Tipheral through

request and acknowledge lines by using handshaking procedure.

1.The DMA controller has three registers :an address register, a word count register, anda control register. The address register cnfi

in address The address bits go through busbuffer into address bus The address register isincremented after word that transferredto memory. The word- co1fltTegister o14sthe number of words to be transferred.Thisregister is decremented by one after each wordtransfer and internally tested for zero. The

control register specifies the mode of Allregisters m the DMA appears to the (PtJ asI/O interfZ?egisters Thus this CPU canread from or write into DMA registerundefjrggrai1contrpI Via the data bus.


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Q. 13. RAM chip 4096 x 8 bits has tioenable lines. How many pins areneeded for the iegrated circuits package?Draw a block diagram and label all inputand outputs of the RAM. What is mainfeature of random access memory?

Ans.


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(a) Total RAM capacity of 4096. Moreover thesize of each RAM chip in 1024 x 8, that meanstotal number of RAM chips required.

4O96

1024

That means total 4RAM chips are required of1024 x 8 RAM.

No. of address lines required to map each RAMchip of size 1024 x 8 is calculated as specifiedahead.

2 = 1024; 2 = n = 10 that means 10 bitaddress is required to map each RAM chip of

size 1024 x 8.8-bit data bus is required for RAM becausenumber after multiplication is 8 in RAM chip ofsize 1024 x 8.

10 bit address bus is required to map 1024 x8RAM. The 11th and bit is used to select one of

four RAM chips. Here we will take 12 bit ofaddress bus because of 11th and 12th bit willselect one of the four RAM chip as shown inmemory address in Diagram. N0Q. The RAM1C as described above is used in a


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microprocessor system, having 16b addressline and 8 bit data line. Its enable 1 input isactive when A15 and A14 bjjre 0 and 1 and

enable -2 input is active when A13, A12 bitsare X and 0.

Q 14. What shall be the range ofaddresses that is being used by the RAM.

Ans. The RAM chip is better suited forcommunication with the CPU if it has one ormore control inputs that selects the chip onlywhen needed. Another there is bidirectionaldata bus that allows the transfer of data eitherfrom memory to CPU during a read operation,or from CPU to memory during a writeoperation. A bidirectional bus can be three-state buffer. A three-stats buffer output can beplaced in one of three possible states a signalequivalent to logic , a signal equivalent to logic0, or a high impedance state. The logic 1 and0) are normal digital signals. The highimpedance state behaves like an open circuitwhich means that the output does-not carry asignal and has no logic significance.


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The block diagram of a RAM chip is shows in

figure. The capacity of memory is 216 work of16 bit per word. This requires a 16-bit addressand 8-bit bidirectional data bus.

It has A13 and A12 bits which 1 and 0, 0 and 0then it is active to accept two input throughchip select CSI and CS2.

If A15, A14 bits are 0 and I then one input isacceptable it is active i.e. it is from CS1 or CS2(Chip selections).

General Functional table


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Q 15.Design a CPU that meets thefollowing specifications.

Ans .can access 64 words of memory, each

word being 8-bit long. The CPU doesthis outputting a 6-bit address on its outputpins A [5 0] and reading in the 8-bit valuefrom memory on inputs D [7,...O]. It has one8-bit accumulator, s-bit address register, 6-bitprogram counter, 2-bit instruction register, 8bit data register.

The CPU must realise the following instructionset:


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AC is Accumulator


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MUX is Multiplexer

Here instruction register has two bitscombination i.e.

Instruction Code Instruction Operation

00 ADD AC - AC + M[A]

01 AND AC - AC A M[A]

10 JMP AC - M[A]

11 INC AC - AC + I

Q. 16. What are the advantages you gotwith virtual memory?

Ans permit the user to construct program asthough a large memory space were available,equal to totality auxiliary memory. Eachaddress that is referenced by CPU goes

through an address mapping from so calledvirtual address to physical address mainmemory.


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There are following advantages we got withvirtual memory:

1. Virtual memory helps in improving theprocessor utilization.

2. Memory allocation is also an importantconsideration in computer programming due tohigh cost of main memory.

3. The function of the memory management

unit is therefore to translate virtual address tothe physical address.

4. Virtual memory enables a program toexecute on a computer with less main memorywhen it needs.

5.Virtual memory is generally implemented by

demand paging concept In demand paging,pages are only loaded to main memory whenthey are required

6.Virtual memory that gives illusion to userthat they have main memory equal to capacityof secondary stages media.

The virtual memory is concept of implementation which is transferring the datafrom secondary stage media to main memoryas and when necessary. The data replacedfrom main memory is written back to


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secondary storage according to predeterminedreplacement algorithm. If the data swajd isdesignated a fixed size. This concept is called

paging. If the data is in the main viiI1zesubroutines or matrices, it is calledsegmentation. Some operating systemscombine segmentation and paging.

Q 17. Write about DMA transfer.

Ans .the CPU communicates with DMA throughthe address and data buses as with a interfaceunit. The DMA has its own address, whichactivates the DS and RS lin&jt\he CPUinitializes the DMA through the data bus. Oncethe DMA receives the start control command, itcan start the transfer between peripheraldevice and the memory. When the peripheraldevice sends a DMA request, the DMAcontroller activates the BR line, informing theCPU to relinquish the buses. The CPU respondswith its BC line, informing the DMA that itsbuses are disabled. The DMA then puts thecurrent value of its address register withaddress bqs, initiates the RD WR signal, and


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sends a DMA acknowledge to the peripheraldevice. RD and WR lines in DMA controller arebidirectional. The direction of transfer depends

on the status of BC line.

When BG = 0, the RD and WR are input linesallowing CPU to communicate with the internalDMA register when BC =1, the RD and WR areoutput lines from the DMA controller torandom-access memory to specify the read orwrite operation for the data.

When the peripheral device receives a DMAacknowledge, it puts a word in the data bus(for write) or receives a word from the data


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bus (for read). Thus the DMA controls the reador write operations and supplies. The addressfor the memory through the data bus for direct

transfer between two units while CPU ismomentarily disabled.

DMA transfer is very useful in manyapplications . It is used for fast transferof information between magnetic disks andmemory. It is also useful for updating thedisplay in an interactive terminal. The contentsof memory is transferred to the screenperiodically by means of DMA transfer.

Q 18.What is memory organization ?Explain various memories ?

Ans .The memory unit is an essentialcomponent in any digital computer since itis needed for storing programs and data A very

small computer with a limited application maybe able to fulfill its intended task without theneed of additional storage capacity, Mostgeneral purpose computer is run moreefficiently if it is equipped with additional


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storage beyond the capacity of main memory.There is just not enough in one memory unit toaccommodate all the programs used in typical

compui Mbst computei- users accumulateand continue to accumulate large amounts ofdata processing software.

There, it is more economical to use low coststorage devices to serve as a backupfor storing. The information that is notcurrently used by CPU. The unit thatcommunicates directly with CPU is called themam memory Devices that provide backupIore d&ild auary memory The most commonauxj1aii memory device used auxilor systemare magnetic disks and tapes. They are usedfor storing system programs, large data files,and other backup information. Only proapisnddata currently needed by the processor residein mam memory All other information is storedin auxiliary memory and transferred to mainmemory when needed.

There are following types of Memories:

1. Main memory

* RAM (Random - Access Memory)

* ROM (Read only Memory)


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2. Auxiliary Memory

* Magnetic Disks -

* Magnetic tapes etc.

1. Main Memory : The main memory iscentral storage unit in computer system. It isused to store programs and data duringcomputer operation. The technology for

main memory is based on semi conductorintegrated circuit.

RAM (Random Access Memory) : Integratedcircuit RAM chips are available in two possibleoperating modes, static and dynamic. Thestatic RAM consists of internal flip flops that

store the binary information. The dynamic RAMstores binary information in form of electriccharges that are applied to capacitors.

ROM: Most of the main memory in generalpurpose computer is made up of RAM integrated chips, but a portion of thememory may be constructed with ROM chips.Rom is also random access. It is used for stringprograms that are permanently incomputer and for tables of constants that donot change in value once the production ofcomputer is completed.


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2. Auxiliary Memory : The most commonauxiliary memory devices used in computer

systems are magnetic disks and magnetictapes. Other components used, but not asfrequently, are magnetic drums, magneticbubble memory, and optical disks. Auxiliarymemory devices must have a knowledge ofmagnetic, jctranics and electro mechanicalsystems There are followmg auxiliary

memories.

Magnetic Disk: A magnetic .Disk is a circularplate constructed of metal or plastic coatedwith magnetized material. Both sides of thedisk are used and several disks may bestacked on one spindle with read/write heads

available on each surface. Bits are stored inmagnetised surface in spots along concentriccircles called tracks. Tracks are commonlydivided into sections called sectors. Disk thatare permanently attached and cannot removedby occasional user are called Hard disk. A diskdrive with removable disks are called a floppy

disks.

Magnetic tapes: A magnetic tape transportconsists of electric, mechanical and electroniccomponents to provide the parts and controlmechanism for a magnetic tape unit. The tape


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itself is a strip of plastic coated with amagnetic recording medium. Bits are recordedas magnetic spots on tape along several

tracks. Seven or Nine bits are recorded to forma character together with a parity bit R/Wheads are mounted onein each track so thatdata can be recorded and read as a sequenceof characters.

Q. 19. Compare interrupt I/O with DMAT/O?

Ans. There is following given comparisonbetween interrupt I/O with DMA I/O.


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Q 20. What is memory interleaving ? Howis it different from cache memory?

Ans. Memory is to be partitioned into anumber of modules connected to acommon memory address and data buses Amemory modules is memory array togetherwith its own address and data registers. Figureshow a memory unit with four modules. Eachmemory array has its own address register ARand data register DR. The ssreisters receiveinformation from a common address bus andthe data registers communicate with abidirectional data bus The two least significantbits of the address can be usedto distinguish between four iodiii The fidteinjtsiEidu1e to initiate a memoryaccesswle cLmQdlls are in process of readingor writing awo and each module is honor amemory request independent of the state ofother modules.


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The advantage of a modular memory is that itallows the use of a techniquecalled interleaving. In an inter created memory,different sets of addresses are assignedto different memory modules. For example, ina two-module memory system theeven addresses may be one module and theodd addresses in other. When the numberof modules is a power of 2, the least significantbits of the address select a memorymodule and remaining hIs designale thespecific lncptitebaccss within the

selected module,A modular memory is useful in systems withpipeline and vector processing. A vectorprocessor that uses an n- y interleavedmemory caric oerandsom n different


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modules. By staggering the memory access, ?ifective memory cycle time can he reduced bya factor close to the number of modulus. A CPU

with instruction pipeline can take advantage ofmultiple memory modules so that eachsegment in the pipeline can access memoryindependent of memory access from othersegments. Cache memory is different frommemory interleavmg.

Processor accesses the main memory for thedata. That speed of central processes areabout 50 times faster than main memory.Hence processor cannot be utilized toits efficiency. The solution to this problem is touse a cache memory between thecentral processor and the main memory. Cachememory can provide the data to the CPU atthe faster rate as compared to main memory.It is pronounced cashes, a special high-speed storage mechanism. It can he either areserved section of main memory or anindependent high speed memory.

A cache memory is totally different from

interleave memory because its talks about itsdata and address bus but in cache memory, itsits between central processor and the mainmemory. During any particular memory cycle,the cache is being checked for memory


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address being issued by the processor. If therequested data is available in cache, this iscalled a cache bit. If the requested data is not

available in cache, this is called a cache miss.Cache replacement policy will determine thedata that will go out of cache to accommodatethe new coming data.

Hit ratio is defined as number of hits in cacheto total number of attempt made by CPU. A hitratio has the value range from 0 to 1. Higher isthe hit ratio, better is the performance ofsystem.

Suppose access time in cache is easy to findout as compared to memory inter leave accesstime. There is simple i.e. access time of mainmemory 100 ns, access time of cache memory

is I Ons and hit ratio is 0.8. The averageaccess time of CPU (8 x 10 + 2 x (100 +10)/lO) = 30 ns. Since hit ratio is 0.8 thatmeans CPU will get the data 8 times in cachememory out of 10 attempts and in remaining 2attempts CPU have to access the data from themain memory.

The size of cache memory is up to 512 MB andsize of main memory is up to 512 MB incurrent generator computers. So why not wechoose the size of cache equal to the main


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memory. Is that case no main memory isrequired. That would work but it would hnincredibly expensive. The idea behind caching

is to use a small amount of expensive peed upa large arnou. J siowei, xpensve mey.

Q.21.What do you mean by initializationof DMA controller ? HowDMA Controller works? Explain withsuitable block diagram ?

Ans. The DMA controller needs the usualcircuits of an interface to communicate WithCPU and I/O device. In addition, it needs anaddress register, a word count register, and aset of address line. The address register andaddress line are used for direct communicationwith the memory. The word count registerspecifies the number of words that must betransferred. The data transfer may be donedirectly between the device an memory undercontrol of DMA,


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Figure 2 shows the block diagram of a typicalDIA controller. The unit communicate with CPUvia datet,bus and control lines. The registers inDMA are selected by CPU through address busby enabling PS (DMA select) and RS (registerselect) inputs. The RD (read) and WR (write)inputs are bidirectional When the BG (Busgrant) Input is 0, The CPU is in communicatewith DMA registers through the data bus toread from or write to DMA registers. When BC1, the CPU has the buses and DMA cancommunicate directly with the memory byspecifying a address in the address bus andthe activating the RD or WR control. The DMAcommunicate with the external peripheralthrough the request and acknowledge lines byusing handshaking procedure.

The DMA controller has three register : anaddress register, a word count register, andcontrol register. The address register containsan address to specify the desired location inmemory. The address bits go through bus


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buffers into the address bus. The addressregister is incremented after each word that istransferred to memory. The word count

register holds the number of words to betransferred. The register is decremented byone after each word transfer and internallytested for zero. The control register specifiesthe mode of transfer. All register in DMAappear to CPU as I/O interface register. Thusthe CPU can read from or write into DMA

register under program control via the databus. transfer data be memory a per unittransferred

Block diagram of DMA controller.


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The initialization process is essentially aprogram consisting pf I/O instructionsthat include the address for selecting particular

DMA registers. The CPU initializes the DMA bysending the following information through databus:

1. The starting address of the memory lockhere data liable (for read) or when the dataare stored (for write).

2. The word cont, which is the number ofwords in memory block.

3. Control to specifically the modes of transfersuch as reader Write.

4. A control to start the DMA transfer.

the starting address is stored in the addressregister. the word count is stored in theword Triste hd the control information in thecontrol register. When DMA is initialized, theCPU stops communicating with DMA unless itreceives an interrupt signal or if it wants tocheck how many words have been transferred.


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Q. 22. When a DMA module takes controlof bus and while it retain control of bus,what does the processor do.

Ans. The CPU communicates with the DMAthrough the address and data buses as withany interface unit. The DMA has its ownaddress, which activates the 1)5 and RS lines.The CPU initializes the DMA through the databus. Once the DMA receives the start controlcommand, it can start the transfer betweenperipheral device and the memory. When theperipheral device sends a DMA request, theDMA controller activates the BR line, informingthe CPU responds with its HG line, informingthe DMA that its buses are disabled. The DMAthen puts the current value of its addressregister into the address bus, initiate the RD orWR signal and sends a DMA acknowledge tothe peripheral device. Note that RD and WRlines in DMA controller are bidirectional. Thedirection of transfer depends on the status ofBG line. When BG 0, the RD and WR are inputlines allowing the CPU to communicate with

internal DMA registers. When BC = 1, the RDand WR are output lines from DMA controller tothe random access memory to specify the reador write operation for the data. When theperipheral device receives a DMA acknowledge,


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it puts a word in the data bus (for write) orreceives a word from the data bus (for read).Thus the DMA controls the read or write

operations and supplies the address for thememory. The peripheral unit can thencommunicate with memory through the databus for direct transfer between the two unitswhile the CPU is momentarily disabled.

For each word that is transferred, the DMAincrements its address register anddecrements its word count register. If the word


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count does not reach zero, the DMA checks therequest line coming from peripheral. For a highspeed device, the line will be active as soon as

the previous transfer is completed. A secondtransfer is then initiated, and the processcontinues until the entire block is transferred.If the peripheral speed is slower, the DMArequest line may come somewhat late. In thiscase the DMA disables the bus request line sothat the CPU can continue.to execute its

program, when the peripheral requests atransfer, DMA requests the buses again.

If the word count register reaches zero, theDMA stops any further transfer and removesits bus request. It also informs the CPU of thetermination by means of interrupts when theCPU responds to interrupts, it reads thecontent of word count register. The zero valueof this register indicates that all the wordswere transferred successfully. The CPU canread this register at any time to check thenumber of words already transferred.

A DMA controller may have more than one

channel. In this case, each channel hasa request and acknowledge pair of controlsignals which are connected toseparate peripheral devices. Each channel alsohas its own address register and word count


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register within the DMA controller. A priorityamong the channels may be established sothat channels with high priority are serviced

before channels with lower priority.

DMA transfer is very useful in manyapplication. It is used for fast transfer ofinformation between magnetic disks andmemory. It is also useful for updating thedisplay in an interactive terminal. The contentsof memory can be transferred to the screen bymeans of DMA transfer.

Q. 23. (a) How many 128 x 8 RAM chips

are needed to provide a memory capacityof 2048 bytes?

(b) How many lines of the address busmust be used to access 2048 bytes ofmemory ? How many these lines will becommon to all chips?

(c) How many lines must be decoded forchip select ? Specify the size ofrecorder. 2048


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Q. 24. A computer uses RAM chips of 1024x 1 capacity.

(a) How many chips are needed, and howshould there address lines be connectedto provide a memory capacity of 1024bytes?

(b) How many chips are needed toprovide a memory capacity of 16K bytes?Explain in words how the chips are to beconnected to the address bus ? Specifythe size of the decoders. 1024

.


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Q. 26. An 8-bit computer has a 16-bitaddress bus. The first 15 lines of addressare used to select a bank of 32K bytes ofmemory. The higher order bit of address

is used to select a register which receivesthe contents of the data bus ?

Explain how this configuration can beused to extend the memory capacity


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of system to eight banks of 32 K byteseach, for a total of 256 bytes of memory.

Ans. The processor selects the externalregister with an address 8000 hexadecimal.

Each bank of 32K bytes are selected byaddress 00007 FFF. The processor loads an8-bit number into the register with a single Iand seven 0s. Each output of register selectsone of the 8 banks of 32 bytes through 2-chipselect input. A memory bank can be changedby changing in number in the register.

Q. 27. A Hard disk with 5 platters has2048 tracks/ platter, 1024 sector/track(fixed number of sector per track) and512 byte sectors. What is its totalcapacity?

Ans. 512 bytes x 1024 sectors 0.5 MB/track.Multiplying by 2048tracks/platter gives 1GB/plat platter, or 5GBcapacity in the driver. (in the problem, we use)


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the standard computer architecture definitionof MB 220 bytes and GB 230 bytes, many harddisk manufactures use MB = 1,000,000 bytes

and GB = 1,000,000,000 bytes. Thesedefinitions are close, but not equivalent.

Q. 28. A manufactures wishes to design ahard disk with a capacity of 30 GB or more(using the standard definition of 1GB =230 bytes). If the technology usedto manufacture the disks allows 1024-bytes sectors,.. 2048 sector/track, and40% tracks/ platter, how many platterare required?

Ans. Multiplying bytes per sector times sectorsper tracks per platter gives a capacity of 8 GB(8 x 230) per platter. Therefore, 4 platter willhe required to give a total capacity of 30GB.


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Q. 29. If a disk spins at 10,000 rpm vhatis the average rational latency time of arequest? If a given track on the disk has

1024 sectors, what is the transfer time fora sector?

Ans. At 10,000 r/min, it takes 6ms for acomplete rotation of the disk. On average, theread/write head will have to wait for half

rotation before the needed sector reaches it,SC) the average rotational latency will be 3ms.Since there are 1024 sectors on the track, thetransfer time will he equal to the rotation timeof the disk divided by 1024, or approximately 6microseconds.

Q. 30. In a cache with 64-byte cache lineshow may bits are used to determine whichbyte within a cache line an address pointsto ?

Ans. The 26 = 64, so the low 6 hits of addressdetermine an addresss byte within a cacheline.


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Q. 31. In a cache with 64 byte lines, whatis the address of the first word in thecache line containing the addressBEF.3DEi40 H ?

Ans. Cache lines are aligned on a multiple oftheir size, so the address of first word in a linecan found by setting all of the hits thatdetermine the byte within the line to 0. In thiscase, 6 bits are used to select a byte within theline, SO We can find the starting addressaddress of line by setting the low b b,ts of the

address to 0. giving 13FF 3DE 40 H as theaddress of the first word in the line,

Q. 32. In a cache with 128-byte cachelines, what is the address of the first wordin the cache line containing the addresses.

(a) A23847FF4 (b) 724Ti824H (c)IFFABCIJ24.


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Ans, For 1 28-byte catie lines, the low 7 hits ofaddress indicate which byte within the line an

address refers to. Since lines, are aligned, theaddress of first word in line can be found bysetting the bits of the address that determinethe byte within the line to 0. Therefore, theaddresses of the first byte in lines containingthe above addresses are as follows

(a) A2384780F1 (b) 7245E800H (c)EEFABC8OH.

Q. 33 For a cache with a capacity of 32KB, How many lines does the cache holdfor line lengths of 32, 64 or 128 bytes?

Ans. The number of lines in cache is simplythe capacity divided by the line length, so thecache has 1024 lines with 32-byte lines, 512lines with 64-byte lines, and 256 lines with 128byte lines.


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Q. 34. If a cache has a capacity of 16KBand a line length of 128 bytes, how manysets does the cache have if it is 2-way, 4-way, or 8-way set associative?

Ans. With 128-byte lines, the cache contains atotal of 128 lines. The number of sets in thecache is the number of lines divided by theassociativity so cache has 64 sets if it is 2-wayset association, 32 sets if 4-way setassociative, and 16 set if 8-way set-associative.

Q. 35. If a cache memory has a hit rate of75 percent, memory request take l2ns tocomplete if they hit in the cache andmemory request that miss in the cachetake 100 ns to complete, what is the

average access time of cache?

Ans. Using the formula, the average accesstime = (THjt X H1t) + (TmissX miss)


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The average access time is (12 ns x 0.75) +(100 ns x 0.25) = 34 ns.

Q. 36. In a two-level memory hierarchy, ifthe cache has an access time of ns and

main memory has an access time of 60ns,what is the hit rate in cache required togive an average access time of 10ns?

Ans. Using the formula, the average accesstime = (THjt X 1Hit) + (T5x miss)

The average access time 10ns = (8ns x hitrate) + 60 ns x (hit rate), (The hit and missrates at a given level should sum to 100percent). Solving for hit rate, we get requiredhit rate of 96.2%.

Q. 37. A two-level memory system has anaverage access time of l2ns. The top level


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(cache memory) of memory system has ahit rate of 90 percent and an access timeof 5ns. What is the access time of lower

level (main memory) of the memorysystem.

Ans. Using the formula, the average accesstime = (Flit x PEIIt) + miss)

The average access time = l2ris (5 x 0.9) +(Tmjss x 0.1).

Solving for Tmiss, we get Tmiss 75 ns,

Which is the access time of main memory.

Q. 38. If a cache has 64-byte cache lines,how long does it take to fetch a cache lineif the main memory takes 20 cycles torespond to each memory request andreturn 2 bytes of data in response to eachrequest?

Ans. Since the main memory returns 2 bytesof data in response to each request,


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32 memory requests are required to fetch theline. At 20 cycles per request, fetching a cacheline will take 640 cycles.

Q. 39. In direct-mapped cache with acapacity of 16KB and a line length of 32bytes, how many bits are used todetermine the byte that a memoryoperation references within a cache line,and how many bits are used to select theline in the cache that may contain thedata?

Ans. 2 = 32, so 5 bits are required todetermine which byte within a cache line isbeing referenced with 32-byte lines, there are512 lines in 16KB cache, so, 9 bits are requiredto select the line that may contains theaddress (2 = 512).


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Q. 40. The logical address space in acomputer system consists of 128segments. 'Each segment can have up to

32 pages of 4K words in each physicalmemory consists of 4K blocks of 4K wordsin each. Formulate the logical andphysical address formats.

Ans. Logical address:


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Q. 43. A memory system contains a cache,a main memory and a virtual memory. The


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access time of the cache is 5ns, and it hasan 80 percent hit rate. The access time ofthe main memory is 100 ns, and it has a

99.5 percent hit rate. The access time ofthe virtual memory is 10 ms. What isaverage access time of the hierarchy.

Ans. To solve this sort of problem, we start atthe bottom of the hierarchy and work up. Since

the hit rate of virtual memory is 100 percent,we can compute the average access time forrequests that reach the main memory as (l00ns x 0.995) + (10 ns x 0.005)

= 50,099.5 ns. Give this, the average access

time for requests that reach the cache (whichis all request) is (5ns x 0.80) + (50,099.5 ns x0.20) = 10,024 ns.

Q. 44. Why does increasing the capacity ofcache tend to increase its hit rate?


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Ans. Increasing the capacity Of cache allowsmore data to be stored in cache. If a programreferences more data than the capacity of a

cache, increasing the caches capacity willincrease the function of a programs data thatcan be kept in the cache. This will usuallyincrease the bit rate of the cache. If theprogram references less data than capacity ofa cache, increasing the capacity of the cachegenerally does not affect the hit rate unless

this change causes two or more lines thatconflicted for space in the cache to not conflictsince the program does not need the extraspace.

Q. 45. Extend the memory system of 4096bytes to 128 x 8 bytes of RAM and 512 x 8bytes of ROM. List the memory addressmap and indicate what size decoderare needed if CPU address bus lines are

16 4096Ans. Number RAM chips = 32


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Therefore, 5 x 32 decoder are needed to selecteach of 32 chips. Also 128 = 2, First 7 lines areused as a address lines for a selected

RAM 4096Number of ROM chips = 8.

Therefore, 3 x 8 decoders are needed to selecteach of 8 ROM chips. Also 512 = 2,

First 9 lines are used as a address line for aselected ROM. Since, 4096 = 212,therefore, There are 12 common address linesand I line to select between RAM and ROM.The memory address map is tabulated below

Q. 46. A computer employ RAM chips f 256x 8 and ROM chips of 1024 x 8. The


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computer system needs 2k byte of RAM,4K. bytes of RO

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