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AltiumLive 2017:
Component selection
for EMC
Martin O’HaraVictory Lighting Ltd
Munich,24-25 October 2017
▪Passives▪ resistors, capacitors and inductors
▪Discrete▪ diodes, bipolar transistors, FETs
▪Integrated Circuits▪ logic, microprocessors, i/o interface
▪Others▪ crystals, heatsinks
Component Selection
▪Surface Mount Preference▪ lower parasitic inductance and capacitance
▪Smaller Parts Usually Better▪ same reason as above
▪Be Aware of Mechanical Effects
▪Avoid Sockets in Production▪ add more parasitics
Component Packaging
▪Surface Mount Preference▪ lower parasitic inductance and capacitance
▪Carbon and Film Preferred▪ have more high frequency losses than metal
▪ no intrinsic resonances of significance
▪Wirewound Highly Inductive▪ can be reduced by winding style
▪ Noise Voltage Not Critical to EMC
Resistors
Chip Resistors
100R, 0805
1GHz100kHz
Impedance
(Ω
)
10
10,000
100
1000
▪Surface Mount Preference▪ parasitic inductance limits frequency response
▪Low Equivalent Series Resistance▪ higher rejection at specific frequencies
▪Low Equivalent Series Inductance▪ limits frequency response
▪Cure many EMC problems at circuit level▪ filtering, decoupling, slew limiting
Capacitors
▪ 4-Element Model Simulates Impedance Characteristics
▪ Rs - series resistance
(resistance of lead/electrodes)
▪ ESL – equivalent series inductance (inductance of lead/electrodes)
▪ Rp - dissipative resistance (leakage/hysteresis losses)
▪ Cp - primary capacitance
(design value)
Capacitor Model
DC 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz 100MHz 1GHz
Mica, Glass, Low-Loss Ceramic
Polystyrene
Ceramic (High-K)
Aluminium Electrolytic
Tantalum Electrolytic
Paper
Mylar
Capacitor Dielectric
Ceramic Dielectrics
Dielectric Self Resonant Frequency (MHz)
Y5V 46
X7R 44
COG 40
Capacitor Lead Length
0.1
1
Imp
edan
ce (O
hm
s)
Frequency
15mm
10mm
0mm
10kHz 10MHz1MHz100kHz
10uF Ceramic Disc Capacitor
ESR Limited Capacitor
1
10
100
Imp
edan
ce (O
hm
s)
frequency
ESR
1kHz 10kHz 100kHz 1MHz 10MHz
0.1
1
10
100
1000
10000
100000
1000000
Imp
edan
ce (O
hm
s)
frequency
2.2nF
100nF
1uF
10uF
Impedance MLCC Capacitors
10Hz 100Hz 10kHz 1MHz 10MHz1kHz 100kHz
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30
Applied DC Bias (Volts)
Cap
acita
nce
as a
Per
cent
age
of N
omin
al (%
) COG
X7R
Y5V
DC Bias of MLCC Capacitors
-70
-60
-50
-40
-30
-20
-10
0
10
-40 -20 0 20 40 60 80 100 120 140
Temperature (C)
Cha
nge
in N
omin
al C
apac
itanc
e (%
)
Y5V
X7R
C0G
Temperature Bias of MLCC
Parallel Capacitors
Parallel Resonance of 1uF and 1nF Capacitors
0.01
0.1
1
10
100
1000
10000
10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz 100MHz 1GHz
frequency
Imp
ed
ance
(Oh
ms)
▪Surface Mount Not Important!
▪Parasitic Capacitance ▪ effected by winding style (unquoted)
▪ form factor (closed loop or air cored)
▪Few Useful for Higher Frequency Filtering
▪Self Resonance Potential EMC Problem▪ often within radiated emissions band
Inductors
▪4-Element Model Simulates Impedance Characteristics
▪ Rs - series resistance
(resistance of wire)
▪ Cw - winding capacitance
(varies with winding style)
▪ Rp - dissipative resistance
(limits resonance peak)
▪ Lp - primary inductance
(design value)
Inductor Model
0.01
0.1
1
10
100
1000
10000
100000
1000000
10 100 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 1,000,000,000
Impe
danc
e (O
hms)
frequency (Hz)
10mH
1mH
100uH
10uHW
oLC
f2
1
Inductor Impedance Curves
0.1
1
10
100
1000
10000
100000
10 100 1,000 10,000 100,000 1,000,000 10,000,000
Impe
nanc
e (O
hms)
Frequency (Hz)
Bobbin
Toroid
Rod
Ideal
Lf
RQ
o
p
2
δ
Inductor Form Factor
50
60
70
80
90
100
0 1 2 3 4 5 6 7 8 9
Per
cent
age
of N
omin
al I
nduc
tanc
e (%
)
DC Bias Current (A)
BobbinToroid
Rod
Current Limited Inductance
0
5
10
15
20
1 10 100 1000 frequency (MHz)
Ferrite BeadA
tte
nu
atio
n(d
B)
Ferrite Beads: 1T Inductors
▪Surface Mount Preference▪ lower parasitic inductance and capacitance
▪Diodes▪ unusually fast is often good for EMC
▪Transistors▪ opposite of above!
Discrete Components
Discrete Component Packaging
Package Type Lead and BondWire Inductance
(nH)
Inter-LeadCapacitance
(pF)E-Line 5 0.15
SOT-23 2.5 0.08
▪Terminate Base/Gate Drive from Logic▪ high R for BJT, low R for FET
▪Bipolar Higher ESD Tolerance▪ back-to-back diode structure beneficial
▪Slew Limit Drive with Capacitor▪ BJT can switch very quickly
▪ BJT/FET can demodulate RF as EXP/SQ law
Transistors: Generalisations
Soft recovery best for
lower ripple
Reverse Recovery Time
▪Surface Mount Preference▪ lower parasitic inductance and capacitance
▪Digital Components▪ use lowest speed you can functionally
▪Analogue Components▪ look for bandwidth limited parts
▪ slew rate limiting now popular (for good reason)
▪Avoid Using Sockets in Production
Integrated Circuits
Dual-in-Line (DIL)
Small Outline (SOIC)
Plastic Leaded Chip Carrier
(PLCC)
Lead Count
L (nH) C (pF) L (nH) C (pF) L (nH) C (pF)
8 6.3 0.68 3.1 0.35
14 6.7 0.74 3.2 0.36
16 6.9 0.77 3.4 0.38
20 8.6 1.01 6.7 0.65 4.6 0.62
24 9.1 1.06 7.2 1.14
28 9.6 1.14 5.8 0.72
40/44 11.0 1.25 5.9 0.77
64/68 17.6 1.51 6.1 0.80
IC Packages
www.aseglobal.com
R (mOhms) C (pF) L (nH) Cm (pF) Lm (nH)
MQFP 1.6 16
PQFP 1.7 13
TSOP 90 0.8 5.5
BGA 70 0.5 2.3
uBGA 50 0.25 1.8 0.04 0.2
CWLP 20 0.00531 0.1 0.035
Compliant Wafer Level Packaging
Lead inductance inc at 0.8nH/mm
Lead capacitance inc at 0.1-0.15pF/mm
Bond wire inductance inc. at 1nH/mm
Newer Packages
Ultra-Low Parasitics
Pitch 0.65 0.4 mm
Lm 0.6 1.5 nH
Cm 0.05 1.42 pF
▪ Fine Pitch Packages
▪ increases mutual inductance/capacitance (increases cross talk)
▪ reduced parasitic pin inductance/capacitance (due to shorter leads)
Pin Pitch
Special Package Configuration
Logic Family
Rise/Fall Time (ns)
Bandwidth (MHz)
Noise Margin (V)
Decoupling Capacitor
(nF)
CMOS 100 6.3 1.0 0.47
LTTTL 20/10 20 0.4 0.33
TTL 10 32 0.4 2.20
HC CMOS 10 32 1.0 0.33
LS 10/6 40 0.3 3.30
ALS 4 100 0.4 2.20
S 3/2.5 120 0.3 1.50
F 1.75 180 0.3 1.50
ECL-10K 2 160 0.125 0.22
ECL-100K 1 320 0.125 0.22
Logic Family Parameters
0.0
0.5
1.0
1.5
2.0
2.5
1 10 100
Clock Frequency (MHz)
Pow
er D
isip
atio
n (W
)
100pF
50pF
10pF
0pF
Loaded CMOS Drivers
High Data Rate Drive
1 10 100 1000
Pow
er D
issi
patio
n pe
r Por
t (P
d)
Frequency (MHz)
60MHz-70MHzPECL
CMOS
▪Decouple Every IC▪ can share for low speed, slew limited circuits
▪Calculate C If Possible▪ can use “Rule of Thumb”
▪Multiple Decoupling for Microprocessors▪ every supply pin
▪ parallel capacitors of 1:100
▪Lower Cost than Large Bypass Capacitor
Decoupling Capacitors
Spread Spectrum Clocks
-4 -3 -2 -1 0 1 2 3 4
Am
plit
ud
e (d
Bu
V)
Modulation (%)
Spread Spectrum Clock
Standard Clock
▪Trend for Low Operating Voltage
▪Reduces Current Surges
▪ hence decoupling requirement reduced
▪Reduced Emissions
▪ for same rise/time and frequency 3.3V has 3.6dB lower emissions than 5V part
▪Increased Susceptibility
▪ Avoid or buffer at interfaces
▪ differential signalling improves susceptibility
Low Operating Voltage
▪IC Manufacturer May Change Process▪ improve their yield, increases rise/fall time
▪ won’t advise if no parametric change
▪Not All IC’s Made The Same▪ different manufacturers, different EMI performance
▪ EMC is not a usual datasheet parameter
▪Emission Problem with Digital ICs▪ datasheets specify maximum time parameters only
▪Susceptibility Usually with Analogue ICs
Buyer Beware
▪Transformers▪ similar to inductors for EMC parameters
▪Thyristors, TRIACs, SCR’s etc
▪DC-DC Converters and SMPS▪ often bought as component
▪Electromechanical▪ relays, switches, heatsinks, cabling
▪ use snubber circuits on relays and switches
Other Components
tw
tp
tr
Ideal Square Wave
r
w
p
o
tf
tf
tf
1
1
1
2
1
fo f1 f2
Frequency Domain
Switched Mode Power Supply
0
10
20
30
40
50
60
70
80
90
100
100000 1000000 10000000 100000000
Frequency (Hz)
Co
nd
uct
ed
Em
issi
on
(d
Bu
V)
20dB/decade
40dB/decade
▪Component Selection for EMC is Secondary to Functional Selection
▪Preference for SMD over PTH
▪Generally Slower is Better▪ “fit for purpose”, no need for 100MHz controller on a washing machine
▪ except diodes
▪Use Where Other Criteria are Exhausted▪ note: slower is usually lower cost!
Summary
Thanks for your Attention!
Questions?