Compiling Network Descriptions (LOGLVS)

December 1999 5-1

Dracula Reference

5Compiling Network Descriptions(LOGLVS)

The main focus of Chapter 5 will be on LOGLVS in Dracula. It will cover thefollowing:

■ “Overview” on page 5-2

■ “Preparing Netlists” on page 5-8

■ “LOGLVS Command Sequence” on page 5-9

■ “CDL Control Commands” on page 5-15

■ “SPICE and HSPICE Commands” on page 5-62

■ “Preparing Data Files” on page 5-92

■ “Specifying Transistor Parameters in Data Files” on page 5-126

■ “Running LOGLVS” on page 5-133

■ “Using Hierarchical LOGLVS” on page 5-182

■ “LOGLVS Examples” on page 5-192

December 1999 5-2

Dracula ReferenceCompiling Network Descriptions (LOGLVS)

OverviewTo run an LVS comparison, you must convert a schematic netlist into atransistor-level network data file. You can use LOGLVS to convert many differentdatabase formats, as shown in the LVS flow diagram on the following page.

LOGLVS compiles the logic network data, expands the macros, and integratesthe circuit definition with the logic network data.

A logic schematic is concerned only with an element’s logical function–NAND,NOR, AND, OR, and so forth—not with how this function is implemented intransistors. Therefore, the schematic does not provide enough information toperform a consistency check on gates that have the same logic function butdifferent implementations. To solve this problem, Dracula reads a subcircuitdescription data file you create with the Circuit Description Language (CDL)described in the “Preparing Netlists” section in this chapter. Use CDL to modifyan existing circuit simulator input data file, such as a SPICE™ file.

When LOGLVS integrates a circuit definition with logic network data, it producestransistor-level network data. Each type of primitive logic element must have acorresponding subcircuit description definition. Logic elements with the samename and the same number of inputs and outputs, but with differentimplementations, require different CDL definitions. CDL uses the nameextension to accomplish this. If a logic element does not have a CDL description,it is treated as a box with a logic meaning.

Dracula compares the elements in the logic schematic with the elements in thecircuit library. If both name extensions and I/O counts match, Dracula expandsthe logic element into transistors. After checking and expanding all logicelements in the schematic, Dracula creates an LVS logic file. This file is also

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known as the transistor-level network file, although it can contain a nontransistorbox.

Dracula also expands SPICE data files into transistor-level network files for LVScomparison. The line length is limited to 128 characters, and the module/signal/instance name length is limited to 80 characters.

Note: To turn on MULTIPLE-DISK mode, you only need to specifyMDISKIO.TAB in the LOGLVS run directory.

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LVS Flow Diagram

LVSlogic file

Layout

CadenceEDIF

Error outputPRINT.OUT

SPICEdata file

TEGAS5database

LOGLVS

Form nodes,elements,devices, andcircuits

LVScomparison

Schematic-entryworkstation

Form expanded,sorted Draculadatabase

Draculadatabase

(Transistor-levelnetwork file)

CadenceEDIF

OR

Filter/Reduce

EDIFdatabase

Verilogdatabase

OROR

Subcircuitdescription file (CDL)

Error output*.lvs

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Initial Correspondence Nodes

LVS requires some initial correspondence node pairs for comparison. Draculachecks the names from the layout and the network to find the initialcorrespondence pairs. Each network description language has its own way ofspecifying initial correspondence nodes. The following table summarizes thenode names for each data description format.

Note: Internal correspondence pairs are not required when you use theAUTOMATCH command in the Description block.

Node names Definitions

SPICE GLOBAL

I/O list in .SUBCKTor .MACRO

VCC and VDD are keywords for powerVSS and GND are keywords for groundNode names defined as the highestlevel .SUBCKT or .MACRO are I/O forthe entire chip

TEGAS5

PWRGRNDCLOCKPI or nodes in INPUTcommandPO or nodes in OUTPUTcommand

Element defined as powerElement defined as groundClock inputInputOutput

EDIF VCC or VDDVSS, GND, or GRNDPORT

PowerGroundInput and output

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Node Names

After macro expansion, each node has a new name inside the macro. LOGLVSuses the following format for a node name or cell designator in a logic-level orcircuit-level network:

name1-name2-name3...-namen

name1 Highest level module designator

namen Lowest level node name or designator

LOGLVS uses the following format for the expansion of a SPICE element name:

Mnum1Xnum2...Xnumn

Mnum1 Lowest level element name

Xnum2...Xnumn Subcircuit element names of the subcircuit call listed in thereverse order of the hierarchy

Verilog supply1supply0inputoutput

POWERGROUNDINPUTOUTPUT

Node names Definitions

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For example, the logic network has an element A1-1 as follows:

Dracula expands the node name P1 in BOX3 as follows:

A1-1-Q1-P1

If the preceding figure is a SPICE subcircuit, Dracula expands the name of theelement MP1 as follows:

MP1X02X01

The LVS error report uses the schematic node name. LOGLVS creates theIMAGE.LIS file, which stores the node name directory.

B3S1

B3S2

P1or MP1

Q1 or X02

B2S2

B2S1

B1S2

B1S1

A1-1 (cell designator) or X01

Box 2

Box 1 (cell name)

Logic Network C1001

Box 3

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Preparing NetlistsLVS can use a variety of netlists. However, a logic simulator netlist describesonly an element’s logical function (NAND, NOR, and so forth) and not thetransistors that make up the logic symbol. Therefore, you must also provide aSPICE or CDL file that describes, at the transistor level, what comprises thelogical elements (primitives). LOGLVS uses both of these files to create atransistor-level netlist for LVS.

Every type of primitive logic element called by the schematic netlist must havea corresponding subcircuit definition in SPICE or CDL format. Logic elementswith the same name and the same number of inputs and outputs, but withdifferent implementations, must have different subcircuit definitions. You caneither use a different name or use the name extension feature available in CDL.

LOGLVS accepts CDL netlist files in random .SUBCKT order.

The CDL format is a subset of the SPICE format but differs from it in thefollowing ways:

■ You can use both node names and node numbers.

■ When defining MOS devices, you must give all four terminals (source, gate,drain, and substrate).

To run LVS successfully, you must make minor additions to the basic SPICE orCDL subcircuit netlist.

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LOGLVS Command SequenceThis section describes the LOGLVS commands and shows examples for usingthem in different types of netlists.

LOGLVS commands can be grouped into the following categories:

■ Control commands

■ Parse commands

■ Expand or flatten commands

For some commands, the order is important. If you specify commands in thewrong order, Dracula issues a warning message.

Control Commands

Control commands are optional and must appear at the beginning of the netlist.

CASE Turns on case sensitivity. You must specify this command toinvoke case sensitivity.

TRANSISTOR Allocates virtual memory

RESISTOR Allocates virtual memory for resistor shortages

FPIN Turns on explicit pin assignment and implicit floating pinhandling. For Verilog only.

DATAFORMAT Turns on 4.2 data compression

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DXF Generates EXPELE.LIS/EXPELE.CEL

HTV/DRE Generates Dracula Interactive files

NO_WARNING Turns off connection checking

NO_WARNING TEGAS_PIN

Suppresses warning messages about explicit pinconnection checks

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Parse Commands

To parse the netlist, you must specify parse commands.

EDIF/NET Compiles EDIF netlist file

TEG Compiles TEGAS-V netlist file

VER Compiles VERILOG netlist file

CIRCUIT Compiles SPICE or CDL netlist

CELL/BOX Drops netlist statements from all Hcells. Works only incomposite mode for SPICE files.

Expand or Flatten Commands

Expand or flatten commands are required and let you expand or flatten thenetlist from the parsed result for the primary cell.

GENPAD Generates a 6GPADS.DATA file and must precede theCONV command

LINK Expands the logic network. For TEGAS and VERILOGnetlists only.

CONVERT Converts logic network into a LVSLOGIC.DAT file.

SUMMARY Prints the ELEMENT summary by types and must follow theCONV command

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EXIT Exits the program

LOGLVS Examples

CDL example:

LOGLVS !<<TRANS 200000RESI 30000DXFCELL cell.tab ;necessary if running cell mode. Use the

;CELL/box command if running composite;mode.

CIR cdl ;parse CDL netlist firstCON topX!

Verilog example with the FPIN command:

LOGLVS !<<TRANS 200000FPINHTVCASECELL cell.tab ;necessary if running cell mode. Use the


CIR cdl ;parse CDL netlist firstVER verilog ;parse Verilog netlistLINKCONX!

Verilog example without the FPIN command:

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LOGLVS !<<CASECELL cell.tab ;necessary if running cell mode. Use the


VER verilog ;parse Verilog netlist;can swap with the CDL command

CIR cdl ;parse CDL netlist and can swap with;the VER command

LINKCONSUMX!

EDIF example:

LOGLVS !<<UNLIMITCELL cell.tab ;necessary if running cell mode. Use the


EDIF edif ;parse the EDIF netlistCON top ;convert the top cellx!

EDIF and CDL example:

LOGLVS !<<DATAFORMAT 4.2NO_WARNINGCELL cell.tab ;necessary if running cell mode. Use the


CIR cdl ;parse CDL netlist firstEDIF edif ;parse the EDIF netlistLINKCON top ;convert the top cell

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x!

TEGAS example:

LOGLVS !<<CELL cell.tab ;necessary if running cell mode. Use the


CIR cdl ;parse CDL netlist;can swap with the TEG command

TEG tegas ;parse TEGAS netlist;can swap with the CDL command

LINKCONSUMx!

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CDL Control CommandsYou can add commands to the CDL netlist that can be read by Dracula softwarebut not by the simulator.

■ Use an asterisk (*) preceding a command to specify a line to be read byDracula but not by the circuit simulator. If the first two characters of the linedo not constitute a Dracula control statement, Dracula ignores the line.

■ Use a dollar sign ($) preceding a field to specify a field to be read byDracula but not by the circuit simulator.

■ Use a dollar sign ($) preceding a command to indicate that the line is acomment, and Dracula ignores the line.

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*.BIPOLAR

*.BIPOLAR

Description

Preserves and compares any analog elements coded in the netlist (capacitors,diodes, and resistors). If you do not use the *.BIPOLAR command, LOGLVSignores all resistors, capacitors, and diodes.

When you use *.BIPOLAR, use the *.CAPA command to tell Dracula to ignorecapacitors. Use *.DIODE to tell Dracula to ignore diodes.

To cause Dracula to ignore resistors, use the *.RESI command and specify athreshold resistance below the resistors you want Dracula to ignore. Thiseffectively “shorts” the resistor nodes.

When you use the *.BIPOLAR command, Dracula checks only the connectivityof capacitors, diodes, and resistors. Dracula does not check their sizeparameters unless you specify in the netlist, respectively,

*.RESVAL or *.RESSIZE*.CAPVAL or *.CAPAREA*.DIOAREA*.DIOPERI

If you use the RESVAL command in the netlist file, you cannot also use theRESSIZE command in the netlist. Likewise, if you use the CAPVAL command,you cannot also use the CAPAREA command.

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Be sure your rules file checks for parameter mismatches for each device.Dracula either checks for all resistance mismatches or for width/lengthmismatches. However, Dracula cannot check for both of these simultaneously.

Note: Make sure that every element in the CDL file corresponds to an elementin the layout.

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*.BUSDELIMITER

*.BUSDELIMITER delimiterChar

Description

Specifies delimiter characters for pins in a bus in CDL or EDIF. Pins in a busmust be grouped together in ascending or descending order in CDL. The orderof the net connection to its corresponding pin is determined by its position inthe .SUBCKT statement. For example, a RAM cell is defined in CDL as follows:

.SUBCKT RAM A[0] A[1] B C[8] C[7]

The reference for the RAM cell in Verilog is as follows:

MODULE TOP (CLK,IN,...INPUT [1:2] CLK;INPUT [1:0] IN;...RAM XR1 (.B(net78), .C(CLK), .A(IN));

The pin C[8] of instance XR1 is connected to CLK[1].The pin C[7] of instance XR1 is connected to CLK[2].The pin A[0] of instance XR1 is connected to IN[1].The pin A[1] of instance XR1 is connected to IN[0].

The *.BUSDELIMITER command tells LOGLVS what bus delimiter to look for inCDL files so that LOGLVS correctly matches the CDL definition and itscorresponding Verilog reference. To have LOGLVS replace the bus delimiters itfinds with some other character (or a blank space), use the *.EDIFDELIMITERcommand.

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Arguments

delimiterChar The delimiter can be one of the following: a bracket ([), a lessthan sign (<), or a curly bracket ({). Specify only the leftmostcharacter with the *.BUSDELIMITER command.

Example

The following example specifies a bracket ( [ ) as the delimiter character.

*.BUSDELIMITER [

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*.CAPA

*.CAPA

or

*.CAPA model-name1 model-name2 ...

Description

Use the *.CAPA command only when you specify *.BIPOLAR but do not wantthe capacitors from the SPICE file to be included in the LVS check.

If you specify model names, LOGLVS drops capacitors with the specified modelnames. LOGLVS also drops capacitors that do not specify model names. Youcan specify wildcards with the following exceptions:

■ You must specify “*” with another character. It cannot be specified alonebecause “*” is treated as a comment in CDL/SPICE.

■ You cannot specify wildcards on the cap statement. For example, youcannot specify the following statement:

C3 il vss 3.53898E-02 $.MODEL = P*

Arguments

model-name1 ... LOGLVS drops capacitors with the model names youspecify.

Example

In the following example, LOGLVS drops C1 and C2.

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*.global vdd vss*.BIPOLAR*.RESI=150 [ry] [rx]*.CAPA PA.param.subckt tlow in outC1 in out 3 $.MODEL = PA.ends tlow.SUBCKT inv Z / A WN=1 LN=1 WP=4 LP=2* INVERTERMP1 Z A vdd vdd P WP LPMN1 vss A Z vss N WN LN.ends inv.subckt top out1 in1 V=1Kx1 o1 i1 /inv WN=13 LN=3x2 i1 in1 /inv WN=13 LN=3x3 out1 o1 /inv WN=13 LN=3x4 o1 vss /tlowC2 i1 vss 3.53898E-02C3 i1 vss 3.53898E-02 $.MODEL = PB.ends

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*.CAPAREA

*.CAPAREA

Description

Use this command to specify the area of the capacitor.

Example

C0 NET2 GND 4.5 $[MP]

indicates that the area of the capacitor body is 4.5 squares.

To have LVS compare the area of the capacitors between the schematic andlayout, specify the CAPAREA option in the LVSCHK command.

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*.CAPVAL

*.CAPVAL

Description

Use this command to specify the capacitance value of the capacitor.

Example

C0 NET2 GND 4.5p $[MP]

indicates that the capacitance value of the capacitor is 4.5 picofarads.

To have LVS compare the area of the capacitors between the schematic andlayout, specify the CAPVAL option in the LVSCHK command.

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*.DEFAULT

*.DEFAULT {W=width L=length} {QW=qwidth QL=qlength}{RW=rwidth RL=rlength}

Description

Assigns a default width and length to all transistors and resistors in the netlistthat have no width and length specification.

Arguments

width Width of transistors.

length Length of transistors.

qwidth Width of BJTs.

qlength Length of BJTs.

rwidth Width of resistors.

rlength Length of resistors.

Specify both width and length. If you specify only one, the other defaults to zero.

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*.DIOAREA

*.DIOAREA

Description

Use this command to specify the area of the diode.

Example

D10 NET2 NET7 DP 21 20

indicates that the area of the diode body is 21 squares.

To have LVS compare the area of the diodes between the schematic and layout,specify the DIOAREA option in the LVSCHK command.

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*.DIOPERI

*.DIOPERI

Use this command to specify the perimeter of the diode.

Example

D10 NET2 NET7 DP 21 20

indicates that the perimeter of the diode body is 20 squares.

To have LVS compare the perimeter of the diodes between the schematic andlayout, specify the DIOPERI option in the LVSCHK command.

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*.DIODE

*.DIODE

Description

Use the *.DIODE command only when you specify *.BIPOLAR but do not wantthe diodes from the SPICE file to be included in the LVS check.

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*.EDIFDELIMITER

*.EDIFDELIMITER delimiterChar

Description

Specifies that LOGLVS replaces the port array delimiter in EDIF. The expandedarray port name has the ’_’ delimiter by default. You can change the delimiter byspecifying the *.EDIFDELIMITER control statement in a dummy CDL file. Youcan change the delimiter to any character or a blank space.

Arguments

delimiterChar Any single character you specify. You can also specify ablank space.

Example 1

In the following example, dollar($) is specified as the delimiter for the expandedport array name in EDIF.

The dummy CDL file contains

*.EDIFDELIMTER $

The EDIF netlist file contains

(cell ram(view symboly (viewtype schematic))(interface

(portBundle PB(listOfPorts (port I1) (port I2))

(port (array PA 2)))...

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The expanded port names for ram are as follows

PB_I1PB_I2PA$0PA$1

Example 2

You can specify both *.BUSDELIMITER and *.EDIFDELIMITER in order torecognize the bus notation in the EDIF rename construct and redefine theexpanded bus delimiter as shown in the following example.

The dummy CDL file contains

*.BUSDELIMITER <

*.EDIFDELIMITER #

The EDIF netlist contains

(view symbol (viewType NETLIST)

(interface

(port (array (rename XRB_60_0T03_62_ "XRB[0:3]") 4)(direction INPUT))

(port XDGB (direction INPUT))

(port WPH (direction INPUT))

(port (array (rename RWD_60_0T03_62_ "RWD<1:3>") 3) (directionOUTPUT))

....

The expanded port name is as follows:

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XRB[0:3]#0 ; replace the bus delimiter by #XRB[0:3]#1XRB[0:3]#2XRB[0:3]#3XDGBWPHRWD#1 ; see the effect hereRWD#2

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*.EQUATION

*.EQUATION

Description

Specifies that LOGLVS evaluates and passes parameter expressions downthrough the netlist hierarchy. You must also specify the .PARAM command.

Note: If case-sensitivity is on, all function names, for example, SORT and LOG,must be in uppercase to be recognized by LOGLVS.

Example

*.BIPOLAR*.GLOBAL GND gnd vdd*.PIN GND gnd vdd*.EQUATION*.RESI*.RESVAL.PARAM.subckt zinv zoutp zinp pl=2.0 pp=5.2MQ1 zoutp zinp vdd vdd P w=pl*2+(pp-1) P=LOG(pp)MQ0 zoutp zinp gnd gnd N w=l l=SQRT(pp+10)R2 zoutp zinp 2000+pp $W=MAX(pl,pp) $L=MIN(pl,pp).ends zinv.subckt ztest ztout ztin S1=10 S2=90XI1 ztout net2 zinv pl=4*2 pp=(S1*10)XI0 net2 ztin zinv pl=EXP(S1-9)/2 pp=(S1+S2).ends ztest

After expansion, for the devices of instance XI1:

MQ1 width=115 and length=4.61MQ0 width=10.49 and length=10.49R2 resistance value=2100, width=100, and length=8

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For the devices of instance XI0:

MQ1 width=101.72 and length=4.61MQ0 width=10.49 and length=10.49R2 has resistance value=2100, width=100, and length=1.35

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*.EQUIV

*.EQUIV new-name = old-name

*. EQUIV new-model = old-model

Description

The *.EQUIV command works in one of three ways:

■ Equates node names in a layout database to the corresponding nodenumber in the netlist

■ Equates element subtypes in a Dracula rules file to model names in a CDLfile

■ Equates power and ground nodes. For example,

*. EQUIV VDD=vdd1 VDD=vdd2

In an LVS comparison, all layout text names must start with an alphabeticcharacter and must match the netlist I/O names. The *.EQUIV command canassign a new name to a number in the SPICE netlist. The order in which youenter these parameters is important.

You can also use the *.EQUIV command to equate an element subtype to amodel name. Dracula reads the first two characters of the model name, and ifthey are not the same as the subtype of the element defined, it looks for an*.EQUIV command.

If your *.EQUIV command extends more than one line, use an asterisk-plus sign(*+) at the beginning of each additional line to indicate continuation of theprevious line.

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Note: *.EQUIV cannot be used in the following ways:

■ To double-translate node names

For example, ABC = XYZ and XYZ = DEF does not equate ABC and DEF.

■ To rename a SPICE node number

For example, CBS=99 where CBS is assigned text in the layout databaseor in EDTEXT.

Arguments

new-name Layout text.

old-name Schematic node name or SPICE or CDL node number.

new-model Element subtype.

old-model SPICE/CDL model name.

Example: Equating Node Names with Node Numbers

The following example equates node numbers in a SPICE file (99, 0, 43) to textnames in a layout (VSS, VCC, AIN).

Layout text:

VCC VSS AIN

SPICE:

*.EQUIV VCC=99 VSS=0 AIN=43M1 99 43 8 0 NC W=20 L=5

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Example: Equating Subtype Elements with Model Names

In the following example, for each model name N15L in the netlist, the layoutdatabase must contain a MOS[N] subtype element. Also, for each MOS[N]element in the layout, a corresponding model name N15L must be coded in thenetlist.

Dracula:

ELEMENT MOS[N]

SPICE:

*.EQUIV N=N15LM1 D G S B N15L W=10 L=1.5

Example: Using Node Numbers in a SPICE File

The following is a correct SPICE file:

*.SPICE*.GLOBAL 99:P 0:G*.EQUIV VCC=99 VSS=0 A=8 B=7 C=98.SUBCKT TOP 8 7 98M1 99 8 7 99 P 20 5M2 0 8 7 0 N 10 5M3 7 98 9 99 P 10 5M4 7 98 9 0 N 5 5.ENDS

Here is an example of an incorrect SPICE file:

*.SPICE*.EQUIV A=8 B=7 C=98 VCC=99 VSS=0

.SUBCKT TOP A B CM1 99 8 7 99 P 20 5M2 0 8 7 0 N 10 5

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M3 7 98 9 99 P 10 5M4 7 98 9 0 N 5 5.ENDS

The SPICE file is incorrect because the I/Os (A, B, and C in the .SUBCKTcommand) should be 8, 7, and 98. The *.EQUIV command does not equatenames and numbers within the SPICE file.

The incorrect SPICE file can also be changed to a correct CDL file as follows:

*.GLOBAL VCC VSS.SUBCKT TOP A B CM1 VCC A B VCC P 20 5M2 VSS A B VSS N 10 5M3 B C 9 VCC P 10 5M4 B C 9 VSS N 5 5.ENDS

No *.EQUIV command is needed because this is a CDL file. The .SUBCKT I/Onames assign node names to the layout text I/O names for initialcorrespondence in LVS.

Note: When you use your SPICE or CDL data to run LVS, the *.EQUIVcommand assigns a name to a node number. It cannot connect two nodes. Forexample, node 1 and 2 are two nodes in the SPICE data file. If you specify*.EQUIV VCC=1, VCC=2, Dracula assigns the name VCC to both node 1 andnode 2. These nodes are still two different nodes. For an example of anexception to this global node handling, see the following example.

Example: Equating Different Power Nodes in a SPICE File

*.GLOBAL VDD, VSS, VDD1:P, VDD2:P, VSS1:G, VSS2:G*.PIN VDD VSS*.EQUIV VDD=VDD1 VDD=VDD2 VSS=VSS1 VSS=VSS2

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.SUBCKT NA2 Z A B* 2 INPUT NANDMP1 Z A VDD1 VDD P WP=21.0 LP=21.0MP2 Z B VDD VDD P W=1.0 L=1.0MN1 Z A 5 VSS2 N W=1.0 L=1.0MN2 5 B VSS VSS N W=1.0 L=1.0.ENDS NA2

.SUBCKT NA3 Z C B A* 3 INPUT NAND*.SWAP A B CMP1 Z A VDD2 VDD P W=21.0 L=21.0MP2 Z B VDD VDD P W=1.0 L=1.0MP3 Z C VDD VDD P W=1.0 L=1.0MN1 Z A 6 VSS1 N W=1.0 L=1.0MN2 6 B 7 VSS N W=50.62 L=4.53MN3 7 C VSS VSS N W=1.0 L=1.0.ENDS NA3

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*.GNONSWAP*.GNONSWAP mname

Description

Declares all MOS devices with a specific model name as *.NONSWAP devices.

Argument

mname The model name reference. Must be one or two characters.

Example

Mxxx*.GLOBAL VDD VSS**.GNONSWAP P*.SUBCKT NA2 Z / A BMP1 Z A VDD VDDP WP=12 LP=14MN1 Z B VDD VDDN WN=12 LN=14MP2 Z 5 VSS VSS P WP=12 LP=14MN2 5 B VSS VSS N WN=12 LN=14.ENDS

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*.LDD

*.LDD

Description

Checks LDD devices. You must place this command at the beginning of yourCDL file. For more information, refer to the MOSFETS description in the “CDLElement Definition” section of this chapter.

Example

*.GLOBAL VDD VSS*.LDD..SUBCKT TOP A B.M1 A B VSS NLDD L=2.0 W=10.0 $LDD[N]...ENDS

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*.MEGA

*.MEGA

Description

You specify *.MEGA to invoke case sensitivity for m (milli) and M (mega). If youdo not specify *.MEGA, both m and M mean “milli.” The *.MEGA commandworks only if you the specify the *.SCALE command.

If you specify the *.MEGA command, 53m means 53*10e-3, and 53M means53*10e6. If you do not specify *.MEGA, 53m and 53M both mean 53*10e-3.

Example

*.BIPOLAR*.RESI = 0*.RESVAL*.CAPVAL*.DIODE*.EQUATION*.SCALE METER*.mega.PARAM

*.GLOBAL vdd!

*.PIN vdd

.SUBCKT px A ZMM0 Z A vdd! vdd! PM W=Wx L=1.5u M=1.ENDS px

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.SUBCKT TOP IN OUT VM VPRR9 OUT VP 53K $[RP]RR11 IN VM 53M $[RP]XI0 IN OUT / px Wx=12u.ENDS TOP

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*.NONSWAP

*.NONSWAP mname

or

Mxxx drain gate source bulk mname {W=width L=length} {m=multiplier}{$LDD[type]} $NONSWAP

Description

Specifies all logic gate, series, and parallel structures are swappable by default.The *.NONSWAP command lets you control the swappability in differentapplications.

This command applies to MOS devices only.

Arguments


Mxxx The MOSFET element name. The name must begin with M.

drain The drain terminal node number/name.

gate The gate terminal node number/name.

source The source terminal node number/name.

bulk The bulk terminal node number or name.

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width The width. If you specify W=, it indicates a widthspecification. Dracula does not check the width if you do notinclude this argument.

length The length. If you specify L=, it indicates a lengthspecification.

multiplier Specifies multiple device.

type The LDD designator, specified as a comment. Declares thatthe source and drain terminals have different characteristicsand cannot be swapped.

Examples

Specify nonswappable devices in device statements for a SPICE or CDL file asfollows:

.SUBCKT TOP N1 N2

.....

.....MD1 out N1 10 VSS MN L=10 W=20 $NONSWAPMD2 10 N2 20 VSS MN L=10 W=20 $NONSWAPMD3 20 N3 VSS VSS MP L=10 W=20...........ENDS

Specify nonswappable devices by subtype in a SPICE or CDL file as follows:

.SUBCKT TOP N1 N2*.NONSWAP MN..........MD1 out N1 10 VSS MN L=10 W=20

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MD2 10 N2 20 VSS MN L=10 W=20MD3 20 N3 VSS VSS MP L=10 W=20...........ENDS

You must specify the *.NONSWAP command after the .SUBCKT command.

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*.NOPIN

*.NOPIN signalName ...

Description

Specifies the exclusion of pins inside an Hcell instance. The *.NOPIN commandmust be inside the .SUBCKT statement, immediately following the header ofthe .SUBCKT statement.

Arguments

signalName The name of the net for the pin.*.NOSUB_M*.NOSUB_M

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*.NOSUB

*.NOSUB_M

Description

Ignores substrate terminal for MOS in the LOGLVS schematic side.

Arguments

M Stands for MOS.

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*.PIN

*.PIN signalName ...

Description

Specifies the insertion of pins that are not in the I/O list to the primary cell orHcell instances. The *.PIN command specifies global pins if you specify itoutside the .SUBCKT statement. If you specify the *.PIN command insidea .SUBCKT statement, *.PIN specifies local pins.

Arguments

signalName The name of the net for the pin.

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*.PININFO

*.PININFO signalName:pinType ...

Description

Specifies which pins act as drivers (outputs) and which pins act as loads(inputs). This command adds pin types to pins listed in the .SUBCKT statementonly. Global nodes are ignored if they are listed in the *.PININFO statement.

By default, if a “/” appears in the .SUBCKT header:

■ The pins preceding the “/” are considered output nodes.

■ The pins following the “/” are input nodes.

If no “/” exists or you specify an unknown pin type, the first pin is an output nodeand the others are input nodes.

Note: When running LVS, pin types are ignored, except for power or groundpads. Pin type is very important in DSPF (an output of HPRE). Refer toChapter 9, “Overview of Parasitic Resistance Extraction.” for more details.

Arguments

signalName The name of the net for the pin.

pinType Specifies one of the following pin types:

B Input/Output (bi-directional)CClockEEnable

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GGroundIInputJJumperOOutputPPowerSSwitchUUnused

Example 1

In the following example, Y is an output signal. A is bi-directional. Pins B and Care input signals.

*.PININFO Y:O A:B B:I C:I

Example 2

In the following example, if you do not specify power and ground, they aretreated as input.

.SUBCKT TOP A1 A2 A3 A4 T1 T2 T3 T4 ANA_VDD ANA_VSS DIG_VDD+ DIG_VSS*.PININFO ANA_VDD:P ANA_VSS:G DIG_VDD:P DIG_VSS:GXNA2 A1 A2 A3 ANA_VDD ANA_VSS NA2XNA4 A1 A2 A4 DIG_VDD DIG_VSS NA2XNA3 T1 T2 T3 T4 DIG_VDD DIG_VSS NA3.ENDS

Example 3

For a .SUBCKT with long list of signals, the syntax is:

*.PININFO O14:O O13:O O12:O O11:O O10:O O9:O O8:O O7:O*.PININFO O6:O O5:O O4:O O3:O O2:O O1:O B10:B B9:B B8:B B7:B

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*.PININFO B6:B B5:B B4:B B3:B B2:B B1:B I10:I I9:I I8:I I7:I*.PININFO I6:I I5:I I4:I I3:I I2:I I1:I

or

*.PININFO O14:O O13:O . . . O O7:O*.PININFO O6:O O5:O . . . B7:B*.PININFO B6:B B5:B . . . I7:I*.PININFO I6:I . . . I1:I

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*.RESI

*.RESI = {value} {[modelName]}

*.RESI = {value} {$.model = modelName}

Description

Specifies the threshold value of the shorted resistors. If the resistance betweenany two nodes in the resistor statement is less than or equal to the thresholdvalue, Dracula connects the two nodes.

You can also short a resistor by specifying its model name. Dracula treats allresistors with the same model name as shorts.

You cannot short two global nodes together.

You can use resistors in SPICE format for simulating both intentional andparasitic resistors. For LVS purposes, you must short the parasitic resistors.

You must include a *.BIPOLAR command. Otherwise, Dracula ignores *.RESIand all resistors. You must include *.RESI before any SPICE element statement.

Arguments

value The threshold value of the resistors to be shorted. You canindicate the units with a K or an M, or you can type the fullnumber. You can use the SPICE scale factor for value. Thedefault is 2K.

modelName The model name of the resistors you want to short. ThemodelName can be a maximum of four characters. If you

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specify a name longer than four characters, Draculatruncates it. Do not put spaces between the square bracketand the model name.

Example 1

In the following example, Dracula shorts both R1and R2.

*.Global VDD VSS*.Bipolar*.RESI=3K [abc]

.SUBCKT TOP A B CM1 A B VDD VDD PR1 C A $[abc]R2 A B 2.5K.ENDS

Example 2

In the following example, the X4 placement of SHI1 shorts the internal net 01 toVSS. The X5 placement of SHI2 shorts its two input terminals, OUT1 and IN1,together. The short effect propagates through the network.

*.GLOBAL VDD VSS*.BIPOLAR*.RESI.PARAM

.SUBCKT INV Z / A WN=1 LN=1 WP=4 LP=2

* INVERTERMP1 Z A VDD VDD P WP LPMN1 VSS A Z VSS N WN LN.ENDS INV

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* SHORT INPUT TO VSS.SUBCKT SHI1 PORTAR1 PORTA VSS 1.5K.ENDS

* SHORT TWO I/Os.SUBCKT SHI2 A BR1 A B 1K.ENDS

.SUBCKT TEST OUT1 IN1X1 I1 IN1 /INV WN=13 LN=3X2 O1 I2 /INV WN=13 LN=3X3 OUT1 O1 /INV WN=13 LN=3X4 O1 VSS /SHI1X5 OUT1 IN1 /SHI2.ends

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*.RESSIZE

*.RESSIZE

Description

Use this command to specify the body size of a resistor as the number ofsquares in the resistor, or to specify the width and length of the resistor body.

Example 1

*.RESSIZE

R3 NET2 OUT 2.4 $[S]

indicates the body size is 2.4 squares.

To have LVS compare the resistor’s body size between the schematic andlayout, specify the RESSIZE option in the LVSCHK command.

Example 2

*.RESSIZE

R3 NET2 OUT $[S] $W=5 $L=12

indicates the width of the resistor is 5 microns and the length is 12 microns.

To have LVS compare the width and length of a resistor body between theschematic and layout, you need to specify the RESWPERCENT andRESLPERCENT options respectively in the LVSCHK command.

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*.RESVAL

*RESVAL

Description

Use this command when specifying the resistance value of the resistor.

Example

*.RESVAL

R3 NET2 OUT 2.4 $[S]

indicates the resistance value is 2.4 ohms.

To have LVS compare the resistance value between the schematic and layout,specify the RESVAL option in the LVSCHK command.

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*.REVERSE

*.REVERSE

Description

Swaps MOS width and length in the SPICE netlist. The standard SPICE MOSstatement specifies width in the first field and length in the second field. If thesetwo fields are swapped, you must use *.REVERSE to ensure correct device sizechecking.

Example

In the following example, the width and length are swapped in the MOSstatements, and *.REVERSE alerts LOGLVS of this. If you specify W= and L=in the MOS statements, *.REVERSE has no effect.

***TRUE SPICE FILE****.SPICE*.REVERSE*.GLOBAL 99 0*.EQUIV IN=1 OUT=2 VCC=99 VSS=0.SUBCKT INV 1 2M1 99 1 2 99 P 2 20M2 0 1 2 0 N 2 10.ENDS

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*.SCALE

*.SCALE [meter]

Description

Specifies that Dracula reads scales in the CDL netlist including for allparameters. If you do not specify this command, scales in the CDL netlist areread only for parameters on resistor and capacitor instances.

Note: Dracula ignores all units in the subcircuit headers and instanceinvocations. For the expression w=2.4um, u is the scale and m is the unit.

The following table lists the scaling factors.

Character(case-insensitive)

Name Multiplier

T Tera 1012

G Giga 109

MEG Mega 106

K Kilo 103

M Milli 1e-3

U Micro 1e-6

N Nano 1e-9

P Pico 1e-12

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Arguments

meter Changes the default database unit from microns to meters.Parameters that represent distance, such as those for diode,MOSFET, BJT, and function MOSFET instances, aremultiplied by E+6 internally to change the unit back tomicron. Parameters for resistor and capacitor instances arenot adjusted if they do not represent distance.

Example 1

This example represents default behavior.

*.BIPOLAR*.CAPVAL.PARAM*.GLOBAL GND:G VDD:P

.SUBCKT INV IN OUT

C1 IN GND 59K * 59000M1 OUT IN VDD VDD P w=.5u l=.25u * .5 .25M2 OUT IN GND GND N w=.5u l=.25u * .5 .25.ENDS

Example 2

In the following example, *.SCALE is specified.

F Femto 1e-15

Character(case-insensitive)

Name Multiplier

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*.BIPOLAR*.CAPVAL*.SCALE.PARAM*.GLOBAL GND:G VDD:P

.SUBCKT INV IN OUTC1 IN GND 59K * 59000M1 OUT IN VDD VDD P w=500000u l=.25 * .5 .25M2 OUT IN GND GND N w=500000u l=.25 * .5 .25.ENDS

Example 3

In the following example, *.SCALE [meter] is specified.

*.BIPOLAR*.CAPVAL*.SCALE meter.PARAM*.GLOBAL GND:G VDD:P

.SUBCKT INV IN OUTC1 IN GND 59K * 59000M1 OUT IN VDD VDD P w=.5e-6 l=.25u * .5 .25M2 OUT IN GND GND N w=.5e-6 l=.25u * .5 .25.ENDS

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*.SPICE

*.SPICE

Description

Indicates a standard SPICE file. This command lets you use an unmodifiedSPICE file that contains only node numbers instead of node names. When youuse a *.SPICE command, Dracula assumes all node names in the CDL orSPICE commands use numbers instead of names. Dracula issues a warningwhen it encounters a node name instead of a number.

You must use this command before using a SPICE element statement. If youomit the *.SPICE command, you must place a backslash before the name of thesubcircuit being called. Without the backslash, Dracula assumes that thesubcircuit is defined in CDL format.

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*.UNSPEC

*.UNSPEC

Description

When you use the *.UNSPEC command in your SPICE or CDL netlist, LOGLVSdetects devices that do not have a width or length definition. Dracula issues awarning in the PRINT.OUT file.

Use this command to check RES, BJT, JFET, and MOS devices.

Examples

*.GLOBAL VDD, VSS*.PARAM WP=2 WN=2*.UNSPEC

.SUBCKT NA2 Z / A B* 2 INPUT NANDMP1 Z A VDD VDD PMP2 Z B VDD VDD P WP=12 LP=14MN1 Z A 5 VSS NMN2 5 B VSS VSS N WN=12 LN=14.ENDS NA2

When you place the *.UNSPEC command in the SPICE or CDL file beforethe .SUBCKT command, you get warning messages for the devices MP1 andMN1 as follows:

***WARNING: MOS HAVE WIDTH OR LENGTH WITH 0LINE 7 : MP1 Z A VDD VDD P

***WARNING: MOS HAVE WIDTH OR LENGTH WITH 0LINE 9 : MN1 Z A 5 VSS N

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SPICE and HSPICE CommandsThis section describes the HSPICE™ and SPICE commands you can use in anetlist file.

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.ENDS or .EOM

.ENDS / .EOM

Description

Terminates a subcircuit definition.

The .SUBCKT or .MACRO commands begin a subcircuit definition. A subcircuitdefinition that begins with .SUBCKT must end with .ENDS. A subcircuitdefinition that begins with .MACRO must end with .EOM.

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.GLOBAL

.GLOBAL name... {:P/G}

Description

Defines global node names such as power, ground, clock, or any node notpassed in and out of subcircuits through the subcircuit I/O. If your version of theSPICE format does not have a .GLOBAL command, you can use *.GLOBAL.However, even with *.GLOBAL, any continuation lines must begin with a plussign (+), not an asterisk-plus sign (*+).

Arguments

name Specifies a list of global node names. The names thatappear here must be the node names in the logic network.

:P/G You can assign a pad type to a global name by adding :Por :G to the name. P stands for power, and G stands forground.

The pad type must always attach to a global name or number even though thisglobal name or number is later replaced by a new name with an *.EQUIVcommand.

Examples

In this example, VBB is a power pad.

.Global VSS, VDD, VBB:P

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Two ground and power pads have unique names. In this application, VBB is aground pad.

*.GLOBAL 1:P 0:G 99:G 2:P*.EQUIV VSS1=0, VDD1=1, VDD2=2, VBB=99

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.INCLUDE

.INCLUDE filename

Description

Includes a file in the SPICE or CDL netlist. This is a standard SPICE statement.

Argument

filename The name of a file to be included in the netlist.

Examples

**CDL/SPICE FILE.INCLUDE MODEL.SPI.INCLUDE QUAD1.SPI.INCLUDE QUAD2.SPI.INCLUDE QUAD3.SPI.INCLUDE QUAD4.SPI

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.PARAM

.PARAM parameter = value...

Description

LOGLVS supports HSPICE parameter usage. You must use this command withparameters in the HSPICE file even if you do not declare any global parameters.

LVS compares the following parameters only:

■ Width and length of MOS and BJT devices

■ Values and areas of capacitors

■ Values and size of resistors

■ Area and perimeter of diodes

Do not place an asterisk (*) in front of the .PARAM command. If you use anasterisk, Dracula ignores this command. To use the .PARAM command, setlocal parameters in the .SUBCKT command as shown below:

.SUBCKT AND 3 1 2 PA1=10, PA2=5

PA1 and PA2 assign a default value to the parameters inside the subcircuit incase a global assignment is not made. You can use only numbers in the I/Olisting. You can also set the parameters in the subcircuit call as follows:

X1 3 1 2 AND PA1=20 PA2=10

The value of PA1 and PA2 overrides a value assigned in the .SUBCKTcommand but does not override a globally set value.

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You can use the parameters to replace the width and length specification in anMOS statement as follows:

.MAC NAND 1 2 3 WP=10 LPn=5M1 3 1 99 0 P WP LPn....EOM

If a parameter value is missing, LOGLVS issues an error message. Theparameter values are missing in the following example:

.SUBCKTINVZ A PW2=PL2=MP1 Z AVDDVDDP W=PW2L=PL2MN1 Z AVSSVSSN W=PW2L=PL2.ENDS INV

When you run LOGLVS in this example, the PRINT.OUT file contains thesemessages:

***ERROR: LINE 2 AT COLUMN 21 PARAMETER PW2 HAS NO VALUE; IGNORE

***ERROR: LINE 2 AT COLUMN 27 PARAMETER PW2 HAS NO VALUE; IGNORE

Arguments

parameter Parameter names. Names must begin with an alphabeticcharacter. There is no limit to the length of parameternames, but only the first four characters in a parametername determine its uniqueness. For example, ABCDE isconsidered the same as ABCDF because the first fourcharacters in both names are identical. If a parameter name

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over four characters appears more than once in the netlist,it is still counted only once.

Note: When the parameter name begins with a W or L character, it has specialmeaning as shown in the following example:

.PARAM

.SUBCKT A X Y Z WL=1 LW=2M1 X Y X Y P WL LWM2 Z Y Y Z N WL LW.ENDS

In this case, both MOS M1 and M2 get Width=1 and Length=2.

value Real numbers. The units of these numbers are ignored. Tohave the scale taken into consideration, specify the*.SCALE command.

Example

The following example shows a CDL netlist with parameter passing:

*TWO-SOME THREE-SOME INVERTER CHAIN.PARAM*.GLOBAL VDD VSS.SUBCKT INV OUT IN pw=10 pl=2 nw=5 nl=2M1 VDD IN OUT VDD P pw pl $ or w=pw l=plM2 OUT IN VSS VSS N nw nl $ or w=nw l=nl.ENDS.SUBCKT CHAIN OUT IN pw1=l0 nw1=5 pw2=30+ nw2=15 pw3=90 nw3=45 nl1=2X1 OUT SIG2 INV pw=pw3 nw=nw3 nl=nl1X2 SIG2 SIG1 INV pw=pw2 nw=nw2 nl=nl1X3 SIG1 IN INV pw=pw1 nw=nw1 nl=nl1.END

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.SUBCKT TOP OUTA OUTB INA INBXA OUTA INA CHAINXB OUTB INB CHAIN pw1=15 nw1=7.5 pw2=15+ nw2=7.5 pw3=15 nw3=7.5 nl1=2.5.ENDS

In the previous example, OUTA, OUTB, INA, INB, VDD, and VSS are the namesfor initial correspondence in LVS.

In inverter chain A, the output instance P device is 90/2 (W/L) and the N deviceis 45/2. The middle instance P device is 30/2 and the N device is 15/2. The inputinstance P device is 10/2 and the N device is 5/2.

In the inverter instance B, the three instances of P device and N device are 15/2 and 7.5/2.5, respectively. The parameter passing feature lets you specify thedevice size without many unique subcircuit definitions.

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.SUBCKT or .MACRO

.SUBCKT/.MACRO subname[#ext] output-node... {/}input-node...

Description

Begins a subcircuit definition. The two commands are equivalent.

The .ENDS or .EOM command ends a subcircuit definition. A subcircuitdefinition that begins with .SUBCKT must end with .ENDS. A subcircuitdefinition that begins with .MACRO must end with .EOM.

Note: Any subcircuit that does not contain a device is considered an elementbox and must have a corresponding element box definition in your Dracula rulesfile.

If you want to use your original SPICE data to run LVS, note the following:

■ If you use an *.EQUIV command and the circuit file is a standard SPICE file(only node numbers and no node names), the .SUBCKTI/O must be numbers and not names.

■ LVS does not allow nested .SUBCKT definitions. Dracula allows subcircuitcalls inside .SUBCKT definitions, but not .SUBCKT definitionsinside .SUBCKT definitions.

■ Node numbers defined in the global statement cannot be included inthe .SUBCKT I/O listing, except for a ground node, which is 0.

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Arguments

subname The element name. You can use an element name definedin TEGAS5 or a user-defined element name. Any name notdefined by TEGAS5 is considered a user-defined name.

#ext The extension associated with this element. The pound sign(#) indicates that an extension follows. The extension isalphanumeric and can be up to eight characters long. Itdistinguishes elements that have the same name and I/Ocount but different implementations. The output node nameof a device must have the same #ext string appended at theend.

output-node The output node names of the element. For single outputdevices, only the first name is considered output. The rest isconsidered input.

/ Separates output names from input names.

Note: When parsing .SUBCKT names, LOGLVS treats “/” as a normalcharacter instead of as a separator.

input-node Input node names.

.Example

.SUBCKT NAND#1 OUT / IN1 IN2

To specify a node as input or output, use the backslash (/) delimiter. LVS doesnot use of this information, but LPE does.

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.SWAP and Special Elements

.SWAP pin-name...

.SWAP (f/p {(f/p pin-name...)} pin-name... )...

Description

LOGLVS lets you specify a special element as a box. The .SWAP commandspecifies which I/O pins can be swapped.

In composite mode, the netlist for LVS, whether compiled from your schematicnetlist or extracted from the layout database, contains a list of interconnectedHcell placements and a list of composite-level pins. The .SWAP commanddetermines whether pins can be swapped on the Hcell placements.

Use the first syntax shown above for a one level swap. Use the second syntaxline for a multiple level swap.

In a one-level swap, a group of pins can be interchanged among themselves,meaning that LVS processes all pins in the group the same way.

In a two-level swap, two groups of pins are interchangeable. The pins withineach group can be interchangeable.

In a multiple level swap, two subtrees of pins are interchangeable. A subtree isa branch of a tree that represents how pins are grouped. Subtrees within eachsubtree can be interchangeable.

The following limitations apply to multiple level swappability:

■ All limitations of one level swappability apply.

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■ Swappable trees must have the same structure.

■ Multiple level swappability applies only to pins in an Hcell.

Argument

pin-name I/O names of the subcircuit. You must enclose the .SWAPspecification by the .SUBCKT and .ENDS or .MACROand .EOM commands.

You must designate whether the pin order is fixed (f) or permutable (p). If you donot want the pin order to change in processing, specify f before the list of pinnames. If the pin order can change during processing, specify p before the listof pin names.

Note: There can be no element specification other than another .SWAP. A plussign (+) indicates continuation to the next line. If you use a .NOPIN statement,it must precede the .SWAP statement.

Examples: One-Level Swap

More than one .SWAP:

.SUBCKT AX1 1 2 3 4*.NOPIN pin1 pin2.SWAP 1 2.SWAP 3 4.ENDS

Nodes 1 and 2 are class 1 terminals. Nodes 3 and 4 are class 2 terminals.

The following specification is illegal. The MOS element specification M1 is notrecognized when you use .SWAP.

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.SUBCKT A1 OUT I1 I2 I3 M1 OUT1 I1 I2 O N*.NOPIN pin1 pin2.SWAP I1 I2 I3.ENDS

Examples: Multi-Level Swap

The circuits in the following examples use this .SUBCKT definition:

.SUBCKT SAMPLE A B C D E F G H I J K L

In the following example, pins A and B are not swappable. Pins C and D are notswappable. However, groups (A B) and (C D) are swappable. Pin A is at thesame position as pin C, so they are swappable. Pins B and D are swappable.

CIR1:.SWAP (p (f A B) (f C D))

In the following example, pins A and B are swappable, pins C and D areswappable, and groups (f (p A B) E) and (f (p C D) F) are swappable.

CIR2:.SWAP (p (f (p A B) E) (f (p C D) F))

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Subcircuit Calls

Xyyy name... {/} subname

Description

A description of the input and output pins of a circuit followed by the subcircuitname.

The .SUBCKT or .MACRO command begins a subcircuit call. The .ENDSor .EOM command ends a subcircuit call.

If the netlist file does not define the subcircuit, Dracula generates a warningmessage in the PRINT.OUT file that includes the cell name and itscorresponding line number.

Arguments

Xyyy The subcircuit call reference beginning with an X.

name Lists the external reference node names. Dracula does notdistinguish between input and output node names. Dracularefers to the names in the order you define in the subcircuitdefinition.

/ Indicates the end of the external node name specification.

subname The subcircuit element name. If the original definition usesan extension, subname must include that extension. You donot need to define the subcircuit before listing it. LOGLVSaccepts randomly ordered netlists.

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Examples

The following example shows subcircuit definitions in a SPICE netlist file.

*.SPICE...SUBCKT GRAYCODE 3 4 5 6 7..X1 14 8 INVX2 16 9 INV...ENDS

The following netlist file has missing subcircuit definitions:

*.GLOBAL VDD.SUBCKT sub0 o iM1 I O VDD VDD P L=5 W=10.ENDS.SUBCKT sub1 ao1 ai1M1 VDD Ao1 1 VDD P L=5 W=10M2 VDD Ai1 1 VDD P L=5 W=10.ENDS.SUBCKT sub2 bo1 bi1M3 1 bo1 PP VDD P L=5 W=10M4 1 bi1 2 VDD P L=5 W=10Xsub12 PP 2 /subxxxxx.ENDS.SUBCKT TOP t1 t2Xsub1 T1 ii /sub1Xsub98790 t2 ii /sub9999999.ENDS

The PRINT.OUT file contains the following error messages:

*** ERROR: SUBCIRCUIT :SUBXXXXX NOT DEFINED at LINE: 12

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*** ERROR: SUBCIRCUIT :SUB9999999 NOT DEFINED at LINE: 16

1) *** UNDEFINED ELEMENT SUB9 : XSUB98790

Pin Count Discrepancies

If the pin count in the .SUBCKT call is different than the number of pins in thesubcircuit, LOGLVS outputs the following error in the PRINT.OUT file:

*** ERROR : DEVICE TYPE JKFF1/GA ISDEFINED WITH 7 PINS, NOT 8 PINS

** ERROR ** DEVICE TYPE : JKFF1 OFELEMENT N1A IS NOT DEFINED

If you ignore this error message, LVS might fail in LVSCHM.

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CDL Element Definition

The CDL defines the following elements:

■ Capacitors

■ Diodes

■ Resistors

■ Three types of transistors

❑ Bipolar junction transistors (BJTs)

❑ Junction field effect transistors (JFETs)

❑ Metal oxide semiconductor field effect transistors (MOSFETs)

To define these elements, CDL uses the formats described in this section.Dracula ignores other elements.

Capacitor Syntax

Cxxx npositive nminus {cap} {M=multiplier} {$[mname] / $.MODEL=mname}{$SUB=substrate}

Arguments

Cxxx The capacitor element. Must begin with the letter C.

npositive The positive terminal node number/name.

multiplier The multiplier device.

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nminus The negative terminal node number/name.

cap The capacitance value. Dracula does not check the value ifthis specification is missing.

mname Specifies the model name reference. The name must beone or two characters. If you want model/subtype checking,you must specify the mname in the CDL netlist and specifythe ELEMENT CAP subtype option in your rules file.

substrate Specifies substrate terminal or node name.

Note: If you require a polarity check, you cannot swap the npositive and nminusterminals with the ELEMENT CAP layer-b and layer-c. You must specify theLVSCHK[P] command in your rules file. If the CDL netlist contains capacitors tobe checked by LVS, you might want to use the *.BIPOLAR command. From the4.7 release, Dracula will support multiplier for Capacity. If you specifymultiplier Capacity in the CDL netlist and do not want to check M-Factorin LVSCHK, the parameters of these devices will be recalculated so that theeffective values will be processed in the LVS flow.

Example

C23 neta netb 3.5p M=2 $.MODEL=CX

Diode Syntax

Dxxx npositive nminus mname {area} {M=multiplier} {periphery}{$SUB=substrate}

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Arguments

Dxxx The diode element name. Must begin with the letter D.

npositive The positive terminal node number/name.

nminus The negative terminal node number/name.

mname The model name reference. The name must be one or twocharacters. For model/subtype checking, you must specifythe mname in the CDL netlist and specify the ELEMENTDIO subtype option in your rules file. You cannot swapnpositive and nminus terminals.

area The diode area specification.

periphery The periphery of junction.

substrate The substrate terminal or node name.

Note: If the CDL file contains diodes to be checked by LVS, you might want touse the *.BIPOLAR command. In the 4.7 release, Dracula will supportmultiplier for Diode. If you specify multiplier Diode in the CDL netlistand do not want to check M-Factor in LVSCHK, the parameters of thesedevices will be recalculated so that the effective values will be processed in theLVS flow.

Example

D100 net_plus net_minus DD

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Resistor Syntax

Rxxx term1 term2 {res} {$SUB=substrate} {M=multiplier} {$[mname] /$.MODEL=mname} {$W=width} {$L=length}

Arguments

Rxxx The resistor element name. Must begin with the letter R.

term1 The first terminal node number/name.

term2 The second terminal node number/mname.

res The resistance value. Dracula does not check the value ifthis specification is missing.


multiplier The multiplier device.

mname The model name reference. The name must be one or twocharacters. For model/subtype checking, you must specifythe mname in the CDL netlist and specify the ELEMENTRES command with a subtype option in your rules file.

width The width of the resistor.

length The length of the resistor.

Note: If the CDL file contains resistors to be checked by LVS, you can use the*.BIPOLAR command. From the 4.7 release, Dracula will support multiplierfor Resistor. If you specify multiplier Resistor in the CDL netlist and do not

December 1999 5-83


want to check M-Factor in LVSCHK, the parameters of these devices will berecalculated so that the effective values will be processed in the LVS flow.

Example

R11 net3 net7 5.9 M=3 $[RX]

Transistor (BJT) Syntax

Qxxx coll base emitter [nsub] mname {M=multiplier} {$EA=value}{$L=length} {$W=width} {$SUB=substrate}

Arguments

Qxxx The BJT element name. Must begin with the letter Q.

coll The collector terminal node name.

base The base terminal node number/name.

emitter The emitter terminal node number/name.

nsub Substrate terminal node name or number.

mname The model name reference. The name can be one or twocharacters.

multiplier Specifies an integer. You must place multiplier in thedescription before you specify any value.

value Specifies an emitter size, coded as a comment.

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length The length of the BJT.

width The width of the BJT.


M-factor commands define multipliers globally. The information here lets youspecifically define multipliers for different circuit elements. See Chapter 11,“ABORT-P-G-SHORT,” for information about M-factor commands.

Example

.PARAM*.GLOBAL VCC VSS*.BIPOLAR.SUBCKT TOP A B AB....Q1 2 5 1 LP M=4 $EA=30 $W=10 $L=3.........ENDS

Transistor (JFET) Syntax

Jxxx drain gate source mname {W=width L=length}

Arguments

Jxxx The JFET element name. Must begin with the letter J.



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mname The model name reference. The name can be one or twocharacters.

width The width. Width is a real number. Dracula does not checkthe width if it is not specified. W= is optional.

length The length. Length is a real number. Dracula does not checkthe length if it is not specified. L= is optional.

Note: You can specify the width and length with two real numbers following themodel name. The first real number is width, the second number is length.

Note: To use parameters as discussed in HSPICE format, use the .PARAMcommand.

Example

J01 net0 net1 net JP W=11 L=2

Transistor (MOSFET) Syntax

Mxxx drain gate source bulk mname {W=width L=length} {M=multiplier}{$LDD[type]} {$NONSWAP}

Arguments

Mxxx The MOSFET element name. It must begin with the letter M.


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bulk The bulk terminal node number/name.


width The optional width. If L= is used, it indicates a lengthspecification. Dracula does not check the width if thisspecification is missing.

length The length. If W= is used, it indicates a width specification.

multiplier The multiple device.

type The LDD designator, specified as a comment. Declares thatthe source and drain terminals have different characteristicsand cannot be swapped.

M-factor commands define multipliers globally, while the information here letsyou specifically define multipliers for different circuit elements. For moreinformation about M-factor commands, refer to Chapter 11, “ABORT-P-G-SHORT.”

Example 1

*.GLOBAL VCC VSS*.BIPOLAR.SUBCKT TOP A B AB.....M1 A B AB LP N M=4 W=10 L=3

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Example 2

M1 A B VSS N LDD L=2.0 W=10.0 $LDD[N]

You can stop generating pseudo gates when running an LVS check by usingmodel name type X-. Dracula prevents any model name (mname) with an X asits first character from forming pseudo gates. This lets LVS locally stop theformation of pseudo gates in the schematic and allows LVS checking of mixedanalog and digital circuits. This special model type works with the ELEMENTMOS[X-] command.

CDL Macro Expansion

CDL has its own macro expansion capability. Although LOGLVS allows morethan 30 levels of macro expansion, it stores element names up to 125characters and truncates characters over the limit.

Dracula expands macros as follows. A .SUBCKT command defines elementX00l as Box1. In Box1 there is another subcircuit called Box2 with the elementname X002. In Box2 there is a third subcircuit called Box3 with the elementname X003. The name of the transistor in Box3 is given in reverse order, fromthe lowest to the highest level:

J001X003X002X001

In addition to the element name JXXX, MXXX, QXXX, or XYYY, every node inthe subcircuit definition has a node name or a node number. Dracula expandsthe node name differently. If the subcircuit is called A1 in the logic network, thename of node 1 inside Box 3 is given from the highest to the lowest level:

A1-X001-X002-X003-1

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This node name expansion is consistent with the name expansion in the logicnetwork.

Macro Expansion

X001 (Element name)

Box 2

Box 1 (SUBCKT name reference)

X002

Box 3

X003

J001

1

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CDL File Example

Here is a partial example of a CDL file. Remember that in CDL you must list allfour terminals (drain, gate, source, and body) when you define MOS devices.

*.GLOBAL VDD,VSS** NA2.SUBCKT NA2 Z / A B* 2 INPUT NAND*TRANSNAME DRAIN GATE SOURCE BODY MODELMP1 Z A VDD VDD P WP=12 LP=14MP2 Z B VDD VDD P WP=12 LP=14MN1 Z A 5 VSS N WN=12 LN=14MN2 5 B VSS VSS N WN=12 LN=14.ENDS NA2*** NA3.SUBCKT NA3 Z / A B C* 3 INPUT NANDMP1 Z A VDD VDD PMP2 Z B VDD VDD PMP3 Z C VDD VDD PMN1 Z A 6 VSS NMN2 6 B 7 VSS NMN3 7 C VSS VSS N.ENDS NA3*** NA4.SUBCKT NA4 Z / A B C D* 4 INPUT NANDMP1 Z A VDD VDD PMP2 Z B VDD VDD PMP3 Z C VDD VDD PMP4 Z D VDD VDD P

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MN1 Z A 7 VSS NMN2 7 B 8 VSS NMN3 8 C 9 VSS NMN4 9 D VSS VSS N.ENDS NA4* NOR.SUBCKT NOR Z / A B* 2 INPUT NORMP1 5 B VDD VDD P WP=22 LP=24MP2 Z A 5 VDD P WP=22 LP=24MN1 Z A VSS VSS N WN=12 LN=14MN2 Z B VSS VSS N WN=12 LN=14.ENDS NOR** IV.SUBCKT INV Z / A* INVERTERMP1 Z A VDD VDD P WP=12 LP=14MN1 Z A VSS VSS N WN=12 LN=14.ENDS INV*.SUBCKT JKFF1 Q QN / CL J K S RMP1 6 CL VDD VDD P WP=12 LP=14MN2 6 CL VSS VSS N WN=12 LN=14MP3 5 6 VDD VDD P WP=12 LP=14MN4 5 6 VSS VSS N WN=12 LN=14MP5 9 6 7 VDD P WP=12 LP=14MN6 9 5 7 VSS N WN=12 LN=14MP7 44 5 7 VDD P WP=12 LP=14MN8 44 6 7 VSS N WN=12 LN=14MP9 8 7 VDD VDD P WP=12 LP=14MP27 8 R VDD VDD P WP=12 LP=14MN10 8 7 17 VSS N WN=12 LN=14MN28 17 R VSS VSS N WN=12 LN=14MP11 9 8 VDD VDD P WP=12 LP=14MN12 9 8 10 VSS N WN=12 LN=14MP13 9 S VDD VDD P WP=12 LP=14MN14 10 S VSS VSS N WN=12 LN=14

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MP15 QN 5 11 VDD P WP=12 LP=14MN16 QN 6 11 VSS N WN=12 LN=14MP17 8 6 11 VDD P WP=12 LP=14MN18 8 5 11 VSS N WN=12 LN=14MP19 Q 11 VDD VDD P WP=12 LP=14MN20 Q 11 13 VSS N WN=12 LN=14MP21 Q S VDD VDD P WP=12 LP=14MN22 13 S VSS VSS N WN=12 LN=14MP23 QN Q VDD VDD P WP=12 LP=14MP25 QN R VDD VDD P WP=12 LP=14MN24 QN Q 18 VSS N WN=12 LN=14MN26 18 R VSS VSS N WN=12 LN=14MP37 39 J VDD VDD P WP=12 LP=14MP38 39 QN VDD VDD P WP=12 LP=14MP39 44 39 VDD VDD P WP=12 LP=14MP40 43 QN VDD VDD P WP=12 LP=14MP41 44 K 43 VDD P WP=12 LP=14MN42 39 QN 42 VSS N WN=12 LN=14MN43 42 J VSS VSS N WN=12 LN=14MN44 44 39 45 VSS N WN=12 LN=14MN45 45 QN VSS VSS N WN=12 LN=14MN46 45 K VSS VSS N WN=12 LN=14.ENDS JKFF1*

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Preparing Data FilesThis section explains how to use the following data formats to describe yournetwork:

■ SPICE

■ TEGAS5

■ EDIF

■ VERILOG

Preparing SPICE Files

To use the original SPICE data (no logic-level description) to run LVS, followthese guidelines:

■ Enclose all element statements in a set of .SUBCKT and .ENDSor .MACRO and .EOM commands. You must also include all of the highestlevel SPICE data statements in a set of .SUBCKT and .ENDS or .MACROand .EOM commands. The I/O names of this macro are candidates forinitial correspondence node pairs.

■ Dracula does not allow nested .SUBCKT definitions. You cannest .SUBCKT calls inside a .SUBCKT definition but not a .SUBCKTdefinition inside another .SUBCKT definition.

■ Except for a ground node, which is assumed to be 0, node numbers definedin the global statement cannot be included in the .SUBCKTI/O listing.

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■ The power name must be VCC or VDD. The ground node name must beVSS or GND. Dracula does not recognize any other name in the *.EQUIVcommand as power or ground.

■ *.EQUIV assigns a name to a node number; it cannot connect two nodes.For example, nodes one and two are two nodes in the SPICE data file. Ifyou specify *.EQUIV VCC=1, VCC=2, Dracula assigns the name VCC toboth node one and node two, but they are still two different nodes.

■ To connect two nodes in the SPICE file, specify the voltage between themas zero. For example,

V1 10,0,0

Dracula connects node 10 and node 0.

You can connect any independent node to a global node or an I/O node.You cannot connect global nodes to global nodes.

■ Do not use the following characters in node names:

, ; : = / tab space

You can use a slash (/) when defining device names in the CDL netlist file.

■ The dollar sign ($) and asterisk (*) are comment indicators.

SPICE File Example

The .GLOBAL command declares power and ground nodes.

The .SPICE command indicates that this is a pure SPICE file and nodes canonly be represented by a number. Use the .EQUIV command to assign a nameto a node number.

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The power node must be VCC or VDD. A ground node can be either VSS orGND. Nodes on the I/O listing of a .SUBCKT command are used as initialcorrespondence nodes.

NETLIST FOR GRAYCODE IN SPICE*FILE NAME = GRAYCODE.SPI*.SPICE.GLOBAL 1 0*.EQUIV Q1B=3 Q2B=4 Q3B=5 Q4B=6 CO=7*+CA=8 MC1=9 SCT1=10 SCT2=11 SCT3=12 *+SCT4=13.SUBCKT GRAYCODE 3 4 5 6 7+8 9 10 11 12 13X1 14 8 INVX2 16 9 INVXN1A 17 3 14 1 1 17 16 JKFF1X3 17 10 INVX4 18 11 INVXN1B 19 4 14 17 17 18 16 JKFF1X5 20 17 19 NA2X6 21 20 INVXR1A 22 5 14 21 21 23 16 JKFF1X7 23 12 INVX8 24 17 19 22 NA3X9 25 24 INVXR1B 26 6 14 25 25 27 16 JKFF1XGH3D 27 13 INVXTU2 28 17 19 22 26 NA4X10 29 28 8 NORXRS2C 7 29 INV.ENDS

Preparing TEGAS5 Files

This section gives details about using the TEGAS5 logic simulator to verify yourdesign and using the TEGAS5 data format to describe your network.

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LOGLVS requires that every element in the network description data be definedby the circuit description language. This section discusses precautions youshould take when preparing a TEGAS5 data file.

Using the TEGAS5 Description Language

This section lists the limitations that apply when using the TEGAS5 DescriptionLanguage (TDL) with LOGLVS.

■ LOGLVS accepts a 132-column text file.

■ LOGLVS accepts TEGAS files in random order.

■ LOGLVS accepts as a valid instance name any string of up to 12alphanumeric characters. If an instance name is more than 12 characters,Dracula turns unlimited text on. The first character must be alphanumeric,but the rest of the string can include any of the following:

_ . # + ( ) - &

■ You can use the dollar sign ($) and semicolon (;) at the end of eachcommand. The dollar sign marks the end of the command.

■ Blanks, commas, colons, and tabs are delimiters.

■ LOGLVS ignores text between double quotation marks (" "), slash-asterisk(/*), and asterisk-slash (*/).

■ Module description commands should appear in the following order:

MODULEINPUTSOUTPUTSLEVEL

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USEDEFINEEND MODULE

■ LOGLVS requires the MODULE, DEFINE, and END MODULE commandsbut does not require both INPUT and OUTPUT commands; however, oneor the other must be present. The USE command is optional. Any of thesecommands may encompass several lines.

■ LOGLVS ignores the LEVEL command except when the level of a moduleis CELL and its I/O pin names are used when compiling higher levelmodules. You must define the details of the module in CDL.

Preparing TEGAS5 Netlists

To prepare a TEGAS5 netlist for LVS, do the following:

■ Encode the network using TEGAS5 data format. Remove dummy elementBoolean equations. Assign a node name to any unconnected NC nodes.Except for the highest level module, bidirectional signals can appear on aninput listing and/or an output listing. If you have a TEGAS5 databasealready built, modify the database as necessary.

■ Define the I/O pads of the highest level module as one of the following:

❑ Power nodes as element PWR

❑ Ground nodes as element GRND

❑ Any clock nodes

❑ Node names in the INPUT or OUTPUT commands

❑ Nodes used as element PI or PPO

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■ Describe any module or element not defined by a TEGAS5 descriptionlanguage using CDL or SPICE format.

Compile the TEGAS5 file as follows:

1. Run LOGLVS.

2. To compile TEGAS5 data files, use the LIB command.

3. To compile a circuit description data file, use the CIR command.

4. To perform a macro expansion on the logic network, use the LINKcommand.

5. To convert the logic network into a transistor-level data file, use the CONcommand.

6. To exit LOGLVS, use the EXIT or X command.

Describing TEGAS5 Data

You must define every gate type in a TEGAS5 netlist with the circuit descriptionlanguage; otherwise, the netlist cannot be expanded into transistors. Thefollowing are exceptions to this requirement:

■ FDETECT, SHDALL, SHD01, SHD10 - Dummy elements are deleted.

■ Boolean equations not allowed.

■ FLTDUMMY - Input and output nodes are connected.Element is deleted.

■ DELAYT, DELAY - Input and output nodes are connected.Element is deleted.

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You can use TDL data directly after doing the following:

■ Convert Boolean equations into their gate implementations.

■ Give every pin a unique node name. Do not try to skip an input or outputpin by using additional commas.

■ Add input protection devices to the network data file, even though they arenot used by the logic simulator.

■ Use CDL to define a circuit box that does not have a logic meaning as amodule.

■ Make modules out of composite gates that should not be separated intoseveral primitives. Use CDL to describe them.

■ Place each node name on a single line. Do not split a name between twolines.

■ Add VSS=GRND$ if there is NC/O/ at any of the input commands. If thereis a NC/1/ command, add VDD=PWR$.

Example: Boolean Equations

Although in logic simulation a Boolean equation can accurately model thebehavior of a logic function, it cannot describe how this function is implemented.To use it to check against the layout, convert any Boolean equation to its gateimplementation. For example, here is a Boolean equation:

RMO = A2’*A1’*A0’

Here is the gate implementation of this equation:

RMO = NOR(A2,A1,A0)

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Example: Skipped I/O Pins

The TEGAS5 logic simulator lets you skip an input or output pin if you specifytwo consecutive commas (, ,) in the input or output pin specification. BecauseLVS needs a node name to report the connection or consistency error, every pinmust have a unique name. You cannot skip an input or output pin. For example:

OUT = NAND(A1,A2, ,A4);

Convert this specification as follows:

OUT = NAND(A1,A2,OUT-3,A4);

Example: Terminators

All TEGAS5 commands require a terminator at the end of the line. You can usea semicolon (;) or dollar sign ($). The only exception is the DEFINE command,which does not need a terminator.

MODULE TEST;INPUT IN1 , IN2;OUTPUT OUT;DESCRIPTION "Description of the module"LEVEL NONE;DEFINEOUT = INV(IN1);END;

Example: Input Protection Devices

Input protection devices, although never used in the logic simulator, must beadded to the network data file. Make the protection device into a module with asingle output/no input or with one output and one input. Then use CDL todescribe the input protection devices.

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For example, an input protection device can be added as a single outputmodule.

A1 = IP( );

Here is the corresponding subcircuit description:

.SUBCKT IP A1

.

.ENDS

This input protection device can also be encoded as follows:

A1 = IP(A1);

The following example is the corresponding subcircuit description:

.SUBCKT IP A1 DUMMY

.

.ENDS

DUMMY is the dummy input port that is not used in the subcircuit.

Example: Circuits that TDL Cannot Describe

If your circuit cannot be described by the TEGAS5 data description language,make the circuit into a module. Then describe this module using CDL.

For example, suppose there is a circuit module A1 that cannot be described byTEGAS5 primitives. You can describe it as a module, EX1 for example, and treatit as a black box.

A1 = EX1(IN1,IN2);

Define it in the circuit file using CDL:

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.SUBCKT EX1 OUT IN1,IN2

.

.ENDS

Note: If a switchlist view is present for a blackbox, you must specify thecomplete library search path of that view. Otherwise, an error occurs.

Example: Splitting Node Names

Any node name must reside on one line.

OUT=NAND(IN1, IN2,...INn)$

The preceding node name cannot be expressed as follows.

OUT=NAND(IN1, IN2, IN3,...INn)$

The name IN3 is interpreted as two words, “IN” and “3.”

Example: NC/0/ and NC/1/

LOGLVS converts NC/1/ to VDD and NC/0/ to GND. If a TEGAS5 netlist filecontains the following commands, LOGLVS converts NC/1/ andNC/0/ as specified in the PWD and GRND statements.

■ NC/0/

■ NC/1/

■ VDD=PWD$

■ GND=GRND$

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Preparing Circuit Data

When preparing circuit data, take these precautions:

■ Similar types of primitive gates that have different I/O counts must havetheir own CDL definitions.

■ You must not separate a composite gate (for example, AND-OR-Inverter)into several primitive gates. Although the functionality of the twopresentations is the same, the implementations are different. Make thecomposite gate a module. Define it in the circuit file using CDL.

■ LVS treats both the wired AND and the wired OR as wire connections.There is no difference in functionality.

■ Except for TDL primitives with a pin name, the order of output pins andinput pins in the subcircuit definition must match the order used in theTEGAS5 data statement.

For example, here is a TEGAS5 data statement:

A1 (O1,O2) = FF2(I1,I2,I3);

Here is the corresponding subcircuit definition:

.SUBCKT FF2 Q, QB, R, S, C

.

.ENDS

You have the following connections:

O1 to QO2 to QBI1 to RI2 to SI3 to C

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If you use pin name specification, LOGLVS checks pin name matching betweenthe TEGAS5 description and CDL description. For example, here is a sampleTEGAS5 statement and a CDL subcircuit definition.

I-10 (N-10=Q, N-3=QB) = FF1 (N-8=CK, N-4=D);I-11 (N-4=QB, N-11=Q) = FF1 (N-9=CK, N-4=D);

.SUBCKT FF1 Q QB CK D

.

.ENDS

LOGLVS checks the pin name in the TEGAS5 statement, compares it with theI/O names in the .SUBCKT command, and makes the correct connection.

Defining Initial Correspondence Nodes

TEGAS5 uses the following nodes as initial correspondence nodes:

■ Nodes defined as PWR, GRND, CLOCK, PI, and PPO

■ Nodes defined in an INPUT command

■ Nodes defined in an OUTPUT command

The name in the TEGAS5 file must match the name in the layout.

Interpreting TEGAS5 Commands

Some of the commands in TEGAS5 have slightly different interpretations inLOGLVS. Here is a list of these variations:

DEFINE

DEFINE:

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Signals the beginning of the logical data description of the module network.Following the DEFINE specification, you can have as many network descriptioncommands as the network has.

designator {output-node...}=module-name {input-node...}$

designator The designator of the module. For a single output device,you can use the designator as the output node name of thegiven device. For a single output device, duplicatedesignators imply that a wired OR connection must be madebetween two output nodes.

output-node The output nodes listing. Lists all output nodes and theirconnections to the given device. You can omit output-nodefor a single output device. Some TDL primitives reverse theorder of output nodes by specifying pin names. LOGLVSrecognizes this condition. However, this method is notrecommended for non-TEGAS5 users.

module-name A TDL primitive element name or a user-defined modulename. A missing module name indicates a wired ORconnection between the output nodes listing and the inputnodes listing. You do not have to include the module namein the USE command or define it as a module. You can usethis name as a subcircuit name in CDL. When the logicnetwork is compiled and converted to an LVS transistor file,LOGLVS uses this name to match with the subcircuit and toperform the expansion.

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input-node Inputs listed in the same order as defined in a moduledefinition or in a subcircuit definition. The names alsoindicate their corresponding connection. The order in whichyou list inputs is significant because it is used at the time ofmacro expansion. TEGAS5 lets you to specify a no-connectby using two commas +(, ,). Although LOGLVS can use thisfeature, it is not recommended because in LVS every pin ofthe element is checked. A floating input must be consideredan error.

Note: LOGLVS lets you arbitrarily select the module name. This means that youcan use the existing cell names. You do not need to rename the cells to matchthe LOGLVS format.

END

END {module} $

Signals the end of the module network description.

module Optional module name specification.

INPUTS

INPUTS: pin-name... $

Lists the external inputs to the module and establishes their relative order.

pin-name List of pin names. You can list up to (2**17)-1 pin names.Continuation is allowed.

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MODULE

MODULE: module-name $

Indicates the beginning of a definition that specifies a module name.

module-name Can have more than 32 characters. TDL has extensions ofdescription class, version number, and directory. Do not usein LOGLVS.

OUTPUT

OUTPUT: pin-name... $

Lists external outputs from the module and establishes their relative order.

pin-name The list of pin names. You can list up to (2**14)-1 pin names.Continuation is allowed.

USE

USE: new-name=type-name{outputs,inputs}$

Assigns a unique type name to a TEGAS5 element or to a user-defined modulename. In the original TDL, the USE command has other purposes. BecauseLOGLVS gives you more freedom in encoding the network, those purposes arenot relevant in LOGLVS.

You can include as many specifications as you want in each USE command.

new-name The user-defined name. When only one new-name ispresent, this module is referenced.

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type-name Specifies either a TDL primitive element name or a user-defined module name.

outputs, inputs The optional output count and input count. If you don’tspecify this option, Dracula uses the I/O counts in theDEFINE command as the module I/O count. If thespecification is present, LOGLVS checks for consistencybetween the I/O counts in the module definition and theactual reference.

Note: In the CDL subcircuit definition, you can use both the new name and typename as a subcircuit name. This lets you distinguish between different elementsthat have the same logic meaning and I/O counts.

Other Module Description Commands

In TEGAS5 TDL, the following module description commands are available:

BIDIRECTDESCRIPTIONLEVELDELAYSWIRED

LOGLVS recognizes a LEVEL command. The other commands are treated asDESCRIPTION commands. Do not use the LEVEL command in LVS.

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Interpreting TDL Primitive Elements

LOGLVS recognizes primitive elements of TDL. Because some primitives arenot useful for LVS, LOGLVS has its own interpretations. Dracula divides TDLprimitives into the following categories.

■ Dummy gates

LOGLVS deletes FDETECT, SHDALL, SHD01, and SHD10 dummy gates.Dracula converts FLTDUMMY into connections, first input to first output.You do not have to define the following dummy gates in CDL:

FDETECTSHDALLSHD01SHD10FLTDUMMY

■ Primary I/O, Power, and Ground

LOGLVS uses these elements as the starting points for LVS comparison.

PIPPOCLOCKPWRGRND

■ Single output devices

Define these gates in CDL using the element name as the subcircuit name.

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AND NOR OR TRIANDONESHOT NOT PUSHPULL TRIORNAND NXOR RESONESHT XOR

■ Wired OR gate type

LOGLVS interprets these gates as connections only.

WANDWORDELAYDELAYT

■ Special gates

Although the gates listed below (except BOOLEAN) represent transistors,you must still define them as a subcircuit using CDL.

BDSWITCH TRANSPBOOLEAN TRIEC1TRANENE TRIRECXTRANEPE TRIREC0

LOGLVS recognizes Boolean equations and assumes that the order ofinputs is the same in the equation. The subcircuit name for the equationmust be BOOLEAN. Name extensions can be used to distinguish Booleanfunctions. Do not use Boolean equations for LVS purposes.

■ Multiple output devices

You must define these multiple output devices in CDL. The I/O listing ofsubcircuits must conform to the I/O listings in the logic data description.LOGLVS does not allow a wired OR configuration of multiple outputdevices.

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ADDER ALU ANDNAND BCDBCDIN COMPARTR COUNTER DECODERDECODERE DENE DEPE DMNEJKENE JKEPE JKMNE MULTIPLMUX NANDMOUT ORNOR PARITYPLA REFILE ROM SERSHIFTSRENE SRNPE SRMNE SRNANDLSRNORL SUBTRACT TMNE

Expanding Macros on a Logic Network

LOGLVS can also perform macro expansion on a logic network. Although theprogram allows more than 30 levels of macro expansion, the hierarchical nodename is limited to 125 characters. Dracula truncates characters over the limit.

The LINK command initiates the macro expansion of a logic network. Beforeperforming the expansion, LOGLVS checks that every element in the module tobe expanded is defined in the library. Dracula prints a warning message if the I/O count of the module does not match the library definition.

Macro expansion of the logic network uses the same format as macroexpansion of the subcircuit defined by CDL. See the CDL Macro Expansionsection in this chapter for more information. The hierarchical name of everynode name in the module is composed of the module designator and its originalnode name with a dash (-) to separate levels of hierarchy instead of a slash (/).

For example, the logic network description language defines Module P1 asBOX1. In BOX1, there is another module called BOX2 with the designator Q1.In BOX2, there is another module called BOX3 with the designator A1. There isa node named OUTPUT inside BOX3. After macro expansion, this node nameis:

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P1-Q1-A1-OUTPUT

The name in the highest level of hierarchy appears first. The designator at eachlevel appears in the same order as its hierarchical order. This format isconsistent with the node name inside a subcircuit definition. The hierarchicalnode name lets you trace a node down to the subcircuit level.

TEGAS File Example

The following is an example of a TEGAS5 TDL file. The first module, FLIPFLOP,defines a JK flip-flop. The occurrence name is used as the output node name ofthe device. If the type name is not a TEGAS name and is not defined in a USEcommand, it is interpreted as a module name.

The second module, JKFLFP, defines the logic network to be compared. TheFLIPFLOP module is expanded twice to form a logic network.

DIRECTORY : SYSTEM $MODULE: FLIPFLOP ;INPUTS : CLOCK, J, K, SET, RESET ;OUTPUT : Q, QBAR ;DESCRIPTION: THE MODULE IS A JK FLIP-FLOP WITH SET AND RESETLINES ;/* THE FOLLOWING LINES DESCRIBE ELEMENTS USED BY THE NETWORK */

USE:NO2 = NOR (2, 1) ;I1 = INV ;AN1 ;

DEFINE:Q1 = NO2 (J,Q5) ;Q2 = AN1(K,Q5,Q1) ;S1 = CXFR(Q10,Q9,Q2) ;Q9 = INV (CLOCK) ;Q10 = I1(Q9) ;

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Q3 = NO2(SET,S1) ;S2 = CXFR(Q9,Q10,Q4) ;S2 = (S1) ;Q4 = NO2(Q3,RESET) ;S3 = CXFR(Q9,Q10,Q3) ;Q5(Q5)= NO2(S3,RESET) ;Q6 = NO2(SET,Q5) ;S4 = CXFR(Q10,Q9,Q6) ;S3 = (S4);(QBAR)= I1(Q5) ;Q8(Q)= I1(Q6) ;

END ;

MODULE : JKFLFP ;INPUTS : CLOCK,J,K,SET,RESET,CLOCK1,J1,K1,SET1,RESET1;OUTPUT : Q,, QBAR, Q1, QBAR1 ;DESCRIPTION : THE MODULE IS A DUAL JK FLIPFLOP ;

USE : FLIPFLOP / / / ;DEFINE :

M(Q,QBAR)=FLIPFLOP(CLOCK,J,K,SET,RESET) ;M1(Q1,QBAR1)=FLIPFLOP(CLOCK1,J1,K1,SET1,RESET1) ;

END ;

Preparing EDIF Files

LOGLVS accepts EDIF netlist files in two ways. You can use EDIF format todefine the logic-level circuit design and CDL or SPICE format to define thecircuit-level detail, or you can use EDIF format to describe the network down tothe transistor level. The commands you use for running EDIF are similar to thoseyou use for CDL or SPICE. The EDIF command parses an EDIF netlist.

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Using EDIF With LOGLVS

If you specify the circuit by mixing EDIF and CDL/SPICE formats, use thefollowing command script:

:cir sub.cdl /* CDL/SPICE netlist files imported first */:EDIF edif.netlist /* EDIF netlist files */:con topCell:x

For composite mode, use the following command script:

:cell/box cell.tab /* Use the box option when running composite mode jobs */

:cir sub.cdl /* CDL/SPICE netlist files imported first */:EDIF edif.netlist /* EDIF netlist files */:con topCell:x

If you specify a circuit using EDIF only, your script might look like this:


:EDIF edif.netlist /* EDIF netlist files */:con topCell:x

Before parsing any work, use the CASE command in LOGLVS to preserve thecharacter case of your input netlist. If you do not use CASE, Dracula changesthe file to uppercase.

The primary cell name specified in the CONVERT command is optional if theEDIF netlist contains a DESIGN construct.

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Using EDIF Primitive Devices

Like CDL/SPICE format, LOGLVS supports primitive devices supplied in theCadence schematic library. LOGLVS also supports primitive devices defined inthe Cadence netlist translator, NINO. The following is a list of the primitivedevices:

Device name model name terminal name

"DIODE" " " "PLUS","MINUS","","", "CAPACITOR" " " "PLUS","MINUS","","", "NDEPL" "ND" "G","D","S","B", "NFET" "NF" "G","D","S","B", "NJFET" "NJ" "G","D","S","", "NMOS" "NM" "G","D","S","", "NMOSD" "NM" "G","D","S","", "NMOSE" "NM" "G","D","S","", "NPN" "NP" "C","B","E","", "NPNS" "NP" "C","B","E","SUB", "NSFTN" "NS" "G","D","S","B", "NXFR" "NX" "G","D","S","", "PCAPACITOR", "P" "PLUS","MINUS","","", "PDEPL" "PD" "G","D","S","B", "PDIODE" "PD" "PLUS","MINUS","","", "PFET" "PF" "G","D","S","B", "PJFET" "PJ" "G","D","S","", "PMOS" "PM" "G","D","S","", "PMOSD" "PM" "G","D","S","", "PMOSE" "PM" "G","D","S","", "PNP" "PN" "C","B","E", "", "PNPS" "PN" "C","B","E","SUB", "PSFTN" "PS" "G","D","S","B", "PXFR" "PX" "G","D","S","", "RES" " " "A","Y","","", "RESISTOR" " " "PLUS","MINUS","","",

Cadence NINO supports the following syntax:

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/* support NINO */ Device name model name terminal name "MOS" " " "G","D","S","B", "BJT" " " "COL","BASE","EMIT","", "RES" " " "TERM1","TERM2","","", "CAP" " " "TERM1","TERM2","","", "DIO" " " "P","N","",""

Primitive device parameters are implemented through the EDIF propertyconstruct.

The following table shows the corresponding property names.

When you use NINO, a property subtype is added to every primitive device.

EDIF files with unrecognized primitive devices are supplemented by aCDL .SUBCKT description, for example:

(cell mentorMos (port A (direction INPUT)) (port B (direction INPUT)) (port C (direction INPUT)) (port D (direction INPUT)))

Primitive typePropertyname

mos W, L

bjt AREA, W, L

res R

dio AREA

cap C

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This primitive mentorMos device can be implemented with CDL in the followingway:

.subckt mentorMOS A B C D m1 B C D A.ends

Parameters are passed in one of two ways, as shown below under Form 1 andForm 2. The corresponding CDL or SPICE form is shown here for reference.

Form 1: Using parameter passing:

. EDIF part (cell nor ... (contents (instance mp1 (viewRef netlist (cellRef pfet (libraryRef sample))) (property l (string "[@PL:%37%:2.00u]")) (property w (string "[@PW:%37%:1.00u]")))

The format [@PW:%37%:1.00u] comes from the output of the Cadence NINOtranslator, edifout. %37% is not used for LOGLVS. The CDL synonym is

.subckt nor ... PL=2.00u PW=1.00ump1 ... l=PL w=PW

Form 2: Setting parameters by value:

. EDIF part (cell adder .. (contents (instance nor2 (viewRef netlist (cellRef nor (libraryRef myLib))) (property PL (string "3.00u")) (property PW (string "4.00u"))

The CDL synonym is

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.subckt adder ... xnor1 ...PL=3.00u PW=4.00u

Preparing Netlist Data

Remember the following restrictions when preparing netlist data:

■ Dracula does not read any file after EDIF. If you use a CDL/SPICE file, putit first and put the EDIF file last.

■ cellType supports GENERIC only (not RIPPER, TIE).

■ Dracula expands the names of ports defined using the EDIF keywordportBundle.

(portBundle data (listOfPorts (port A (direction INPUT))

data_A is the designator. The underscore (_) is the delimiter.

■ Dracula expands nets you define using the EDIF keyword netBundle.

(netBundle local (listOfNets (net A (joined ...))

local_A is the designator. The underscore (_) is the delimiter.

■ Name an array element as follows:

arrayName'_'dimension1'_'dimension2...

You can change the delimiter by specifying the *.EDIFDELIMITER controlstatement in a dummy CDL file

■ viewType supports NETLIST and SCHEMATIC only.

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■ Dracula supports one dimension arrays.

■ Dracula does not support Rename for property names.

■ Dracula requires that you describe primitive devices in uppercase.

■ If you do not define primdev.tab or prop.alias files to map user-definedprimitive devices and properties, Dracula uses the default.

Preparing a primdev.tab File

The primdev.tab file uses a free format and contains two sections. The firstsection tells how many primitive devices are defined in the file. The secondsection defines every primitive device attribute. The eight fields in each linespecify a primitive name, primitive type, terminal count, model name, and fourterminal names.

Primitive name is a string.

Primitive type is one of the following integers:

1 MOS2BJT3RES5DIO6CAP11POWER12GROUND

Terminal count is an integer.

Model name is a string or an asterisk (*).

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Terminal name is a string or an asterisk (*).

Example:

9DIODE 5 2 * PLUS MINUS * *CAPACITOR 6 2 * PLUS MINUS * *NFET 1 4 N G D S BNPN 2 3 N C B E *PFET 1 4 P G D S BPNP 2 3 P C B E *RESISTOR 3 2 * PLUS MINUS * *PWER1 11 1 * U22POW_ U22POW! * *GND1 12 1 * GND1 GND1 * *

The two special primitive types, 11 and 12, are for the power and ground cellsgenerated from the P&R output. U22POW_ is the port name used in theconnection. U22POW! is an alias and is used as the output name in theLVSLOGIC.DAT file. The following are the cell definitions for the power andground cells:

(cell PWER1 (cellType GENERIC)(view symbol (viewType NETLIST)

(interface(port (rename U22POW_ "U22POW!")(direction

INOUT))))))(cell GND1 (cellType GENERIC)

(view symbol (viewType NETLIST)(interface

(port GND1 (direction INOUT))))))

Preparing a prop.alias File

The prop.alias file renames the default primitive property names to the user-defined names. The prop.alais file is free format. The total line number is six.Each line contains four properties.

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line 1:widthlength‘*’‘*’for MOS/LDD devicesline 2: areawidthlength‘*’for BJT devicesline 3: res_val‘*’‘*’‘*’for RES devicesline 4:‘*’‘*’‘*’‘*’unusedline 5:area‘*’‘*’‘*’for DIO devicesline 6:cap_val‘*’‘*’‘*’for CAP devices

‘*’ represents a blank value. The properties and sequence for each device arefixed.

Each line defines four properties, for example:

WW LL * *AREA0 WID LEN *R1 * * ** * * *AREA1 * * *C2 * * *

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Preparing Verilog Files

The commands for running Verilog are similar to those you use for TEGASexcept that you add the VER command to parse the Verilog netlist files. Thefollowing is an example of the command script:

:ver verilog.netlist /* Verilog netlist files:cir sub.cdl /* CDL/SPICE netlist files imported first */:link:con:x

For composite mode, the command script is as follows:


:ver verilog.netlist /* Verilog netlist files */:cir sub.cdl /* CDL/SPICE netlist files imported first */:link:con:x

Note: You can use the CASE command to preserve the case of an input netlist.When you do not use CASE, uppercase is the default. Specify the CASEcommand prior to lines that affect parsing.

If your netlist uses the explicit port assignment in the instance and has missingfloating pins, you must specify the FPIN command. When you specify the FPINcommand, you must specify the CIR command before the VER command so themaster cells are defined before they are accessed. When you do not use theFPIN command, the order of the CIR and VER commands does not matter.

The command script using the FPIN command is as follows:

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:FPIN:cell cell.tab:cir sub.cdl /* CDL/SPICE netlist files imported first */:ver verilog.netlist /* Verilog netlist files */:link:con:x

When running a Verilog file in LOGLVS, you must supply a SPICE or CDL netlistwith the Verilog file even if the Verilog netlist has transistor-level definitions. TheSPICE or CDL netlist supplies the p-transistor and n-transistor level definitions.When preparing your Verilog files, take the following precautions:

■ Check that the maximum line length of the Verilog netlist file is 128characters or fewer, and that module or signal instance names have 80characters or fewer.

■ Match the input and output pin order from the CDL or SPICE definition tothe Verilog file.

For example, if the Verilog file is

FF2 A1 (Q1,Q2,I1,I2,I3)

the subcircuit definition is

.SUBCKT FF2 Q QB R S C

.....

.ENDS

The results include the following connections:

Q1 to QQ2 to QBI1 to RI2 to SI3 to C

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If you specify pin names, LOGLVS checks that the pin names match betweenthe Verilog description and the CDL or SPICE description. For example,

FF2 A1 (.Q(Q1),.QB(Q2),.C(I3),.R(I1),.S(I2));

Regardless of the sequence you define in the subcircuit, the connections are thesame as in the Verilog file.

Tips for Running Verilog FIles in LOGLVS

There are some constructs that are legal in Verilog, but that cause problems forLOGLVS. The following list describes some tips you can use when preparingVerilog files.

■ Group wire [n:m] statements at the beginning of module definitions ratherthan scattered throughout the module. These statements must comebefore any module references.

■ Eliminate multi-line comments in “C” format. For example, change thefollowing comments

/* commentscommentscomments */

to this format:

// comments// comments// comments

or to this format

/* comments comments comments */

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■ Leave spaces both before and after constructs such as [n:m]. For example,change this construct

wire[n:m]name

to

wire [n:m] name

Check for spaces before and after [n:m] constructs in other arguments aswell:

input [n:m] name

output [n:m] name

inout [n:m] name

■ Tell LOGLVS what to LINK. Refer to description of LINK command for whyit is necessary.

■ Use supply1 VCC and supply0 GND instead of input VCC and input GNDso they are recognized as POWER and GROUND for reduction and LVSpurposes. You must also remove VCC and GND from the top-level I/O listor you will get a warning message stating that there is “No power/ground inschematic.”

■ Check the case of primary I/Os. Usually they are lower-case in Verilog, butthe layout pin and text is upper-case. You want to make sure the case isconsistent.

■ Make sure the first signal in an I/O list is not a group, which is defined bybraces({ }). You use braces to group signals together in a bus. Normally,LOGLVS ignores the braces. However, if your first signal in an I/O list is agroup, it will cause problems for LOGLVS because of how I/O lists arecompiled.

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For example, a module definition has the form

module mux(abuss, bbuss, c, d);output [15:0] abuss;input [15:0] bbuss;input c, d;

A module “call” has the form

input [2:0] 3bit;input [12:0] 13bit;[...other stuff...]mux mux({3bit, 13bit}, 16bit, c, d);

LOGLVS selects the first signal in each I/O list to be an output, and all theother signals are inputs. This works fine when the first signal is a single bitsignal, or if the number of bits in the calling bus is the same as the numberof bits in the called bus.

However, if you use a group ({ }), the calling bus can be made up of multiplesmaller busses. When LOGLVS ignores the group, only part of the overallbuss is recognized, and a mismatch occurs in the I/Os between calling andcalled I/O lists.

In the example above, LOGLVS assigns all the 16-bit abuss in the mux tobe the output in the module definition. However, in the call, the firstargument is the 3-bit 3bit signal, so only those three bits get put in theoutput statement, and only those three bits of the 16-bit buss get matchedand used as outputs. The other 13 bits are completely ignored, and everyother signal in the I/O list is shifted by 13. This causes a bad I/O match-upand considerable LVS problems. You need to make sure the first signal inevery I/O list is scalar (single-bit), or at least make sure the calling bus doesnot use groups ({ }).

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Specifying Transistor Parameters in DataFilesThis section discusses how to specify transistor parameters for LVS in TEGAS5logic data file. You can assign the following parameters in the logic data filesinside a comment statement:

■ Width and length information

■ Special gate types

■ Cell names

Use the specifications discussed in this section for parameters of NAND, NOR,INV, AND, and OR standard logic cells. For other types of cells, use CDLwhenever possible.

Parameter Specification Syntax

Parameter specifications must appear in the first nonblank comment statementafter the data statement, on the same line or on the next line. All formats use adollar sign ($) at the beginning of a line as a comment symbol. In addition,TEGAS5 uses the following comment symbols:

■ A semicolon (;) starts a line. To continue on the next line, use anothersemicolon.

■ Quotes (" ") enclose the statement. Both quotes must appear on the sameline.

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■ Slash-asterisk (/*) and asterisk-slash (*/) enclose the statement. Allsymbols must appear on the same line.

A plus sign (+) after the comment symbol indicates a continuation line.

The following example shows the different comment symbols.

TEGAS5 /*.W/L I1=6/8*/

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Width and Length

The .W/L statement assigns width and length to the transistor whose gate isconnected to the input or output pins.

.W/L pin-specification=width/length,...

pin-specification One of the following:

■ MOS element name. The MOS element name must begin with an Mfollowed by up to seven alphanumeric characters.

■ Transistor model name from the CDL or SPICE file. The model name mustbegin with a P or N followed by one optional alphanumeric character.

No blanks are allowed between the equal sign (=) and the pin specification.

width/length Width and length of MOS in microns. Width and length arereal numbers. Only the first two decimal numbers aresignificant.

A slash (/) is required to separate width and length. No blanks are allowedbetween width or length and the slash.

TEGAS example:

Q3 = NO2(A,B)$/*.W/L M2=5/6, M3=4/6, *N=7/8*/

The following lines appear in the CDL file:

.SUBCKT NO2 O A BM1 VCC A 1 VCC PM2 1 B O VCC PM3 O A GND GND N

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M4 O B GND GND N.ENDS

The gate of the pull-up transistor connected to node B has a width of five and alength of six microns, and both pulldown transistors have the assigned widthseven and length eight. The effect of M3=4/6 is overridden by *N=7/8.

ILOS example:

A1 .NAND A3, I3, I4, B2 $ .W/L I1=4/6$ + I3=5/7

In this example, I1=4/6 specifies that MOS, which has a gate connected to nodeA3, has a width of four and a length of six microns. If it is CMOS, both thepulldown transistor and pull-up transistor have the assigned width and length.I3=5/7 indicates that the MOS whose gate is connected to node I4 (instead ofnode name I3) has a width of five and a length of seven.

Gate Type

The .TYPE specification assigns a new gate type to a transistor. Use it to updatea gate type in NMOS only. For CMOS, use CDL to specify the gate type.

.TYPE pin-number=type, ...

pin-number The I/O pin to which the parameter is passed. Draculaupdates only the parameters of transistors that have a gateconnected to this node.

I before the number indicates an input pin; O before the number indicates anoutput pin. Do not put a blank between I or O and the number. The number must

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be less than the number of input or output pins of the gate. An asterisk (*) or nopin-number specifies all pins.

type Gate type.

Cell Name

The .CELL command replaces a logic gate with a new cell name. Use it toassign a different name to gates with the same logic function, but with differentimplementation.

.CELL = cell-name

cell-name The new cell name. The cell name used in CDL must matchthis new cell name. It can be a maximum of eight characters.

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Cautions

Specify as much in CDL as possible. Use CDL or SPICE formats wheneverpossible to define width/length and to assign gate type. The features discussedin this section are designed to handle special cases, mainly in NMOS. Becauseof this, be aware of the following.

In TEGAS5, the pair of comment symbols must always appear on the same lineand follow the end-of-statement symbol ($ or ;). For example

$/* .W/L I1=32/42,...........................*/

Slash-asterisk (/*) and asterisk-slash (*/) must appear on the same line followingthe end-of-statement character ($).

To continue to a new line, you must enter a new end-of-statement character andnew comment symbols in addition to a plus sign (+). For example

$".W/L I1=10/5,..............................W/L I1=

$"+ 5/7,..................................... "

The features discussed in this section specify a transistor that has a gateconnected to the input or output pin of a cell only. If the gate of a transistorcannot be reached by either input pins or output pins, Dracula cannot update itsparameters. These features are best suited for conventional logic gates likeNAND and NOR. For other cell types, use CDL to specify the transistorparameter.

Once you assign a new cell name to a logic gate, you must use it as thesubcircuit name in CDL. The old cell name is overridden.

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You cannot use a .TYPE specification for CMOS. An input pin of a CMOS gateconnects to the gates of both pull-up and pulldown transistors. Any gate typeassignment results in the gate types of both transistors being updated. Thesame situation applies to the width and length specification, unless the widthand length of both pull-up and pulldown transistors are the same. Do not usethe .W/L specification.

Dracula expects either a period (.) or a plus sign (+) after the comment symbols.If other characters are encountered, Dracula treats the whole line as acomment. LOGLVS does not generate any syntax error message.

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Running LOGLVSThe Network Compiler, LOGLVS, runs interactively to compile schematic netlistdata and combine it with circuit description data to create a transistor-levelnetwork description that Dracula can use for LVS comparison.

After loading both the schematic netlist and the circuit description files on thesystem, you are ready to run LOGLVS. To start running LOGLVS, type

LOGLVS

During a LOGLVS run, you can use the commands described in this section tocontrol the run. You need to type only the first three characters of the command.You can type a maximum of 128 characters on each command line.

When LOGLVS finishes, it returns one of the following three status codes in thePRINT.OUT file:

0 no errors or warnings1 warnings, but no errors2 errors

If you want the status code to appear on the screen, use the following script:

LOGLVS <<!lib ecad.tegcir ecad.cirlinkconexit!

set $status2 = $statusif ($status2 = 1) then

echo "LOGLVS WARNING ****** exit $status2 ******"elseif ($status2 = 2) then

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echo "LOGLVS ERROR ****** exit $status2 ******"exit

endif

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CASE

CASE

Description

Turns on case sensitivity for the netlist processing.

By default, Dracula converts all input files to uppercase before processing.

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CELL

CELL{/option} filename... {1}

Description

Identifies the file that specifies Hcells. This file must contain the Hcell subcircuitnames as well as the Hcell layout cell names. See the HCELL-FILE commanddescription in Chapter 11, “ABORT-P-G-SHORT” for information on this file.

The CELL command works only in the hierarchical modes; it does not work inflat mode.

Arguments

option Directs the command output. Type one of the following:

/print Directs output to the PRINT.OUT file.

/type Directs output to the terminal, assuming that the terminaldefaults to file unit 6.

/store Directs output to the IMAGE.LIS file.

/auto Automatically updates Hcell table files. If Hcells do not havea placement number and are not found in the logic-level orcircuit files, the Hcell table files are added with a semicolon(;) comment character in column 1.

/ box Ignores netlist statements for all Hcells when compiling theLOGLVS netlist. Use this option for composite mode only.

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filename Names of files containing Hcell table files. Each file namecan have up to 80 characters, including the full path name.

1 Indicates that the first cell is to be considered a schematiccell name. You must include the “1” to compile a netlist thatwill be treated as the layout netlist in a Schematic VersusSchematic (SVS) check in either cell or composite mode.

Examples

In the following example, LOGLVS reads in Hcells from three files: file-1, file-2,and file-3.

CELL/type file-1 file-2 file-3

CELL hcell.tab 1

Dracula treats the first cell listed in HCELL.TAB as a schematic cell andperforms an SVS check.

cell/box hcell.tabcir filescon cell-namex

Dracula drops the netlist statements from all Hcells.

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CIRCUIT

CIRCUIT{/option} filename...

Description

Reads the circuit library file. The CIRCUIT command also compiles SPICE datafiles.

LOGLVS accepts circuit files in random .SUBCKT order.

Arguments





/nodrop Does not drop any devices that do not have I/O pins. Thisoption applies to all netlists compiled with the CIRCUITcommand from the point you specify nodrop.

filename Names of files containing the circuit library. If a subcircuit isdefined twice, the second subcircuit definition overrides thefirst. Each file name can have up to 32 characters.

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CONVERT

CONVERT{/option}/notop {cellname}

Description

Converts the logic network data into LVS format and saves it to disk. LOGLVScompares the elements in the logic schematic with the elements defined in thecircuit library. If the names, extensions, and I/O counts match, LOGLVS expandsthe logic elements into transistors. After it checks and expands all logicelements in the schematic, it creates the LVSLOGIC.DAT file.

Arguments




The default is one output file, LVSLOGIC.DAT.

notop Specify this option in Cell mode to specify there is no top-level .SUBCKT.

You use this option when verifying a standard library of cells that you have

not yet placed in a design hierarchy.

cellname The name of the top level subcircuit or macro to beconverted. Use this option only when you use a SPICE datafile with no logic network or when parsing an EDIF file. Whenthe cell name is absent, the logic network is converted.

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DATAFORMAT

DATAFORMAT 4.2

Description

Turns on the database compression algorithm introduced in Dracula 4.2.Dracula can take both D3 and 4.2 input files for the same module.

Note: You must also specify this command in the Description block for LVS andnon-LVS jobs.

If you do not set the data format in the rule file, LOGLVS run, or both, thecombination of the data format for the input and output files is shown in thefollowing table.

Example

DATAFORMAT 4.2

jxrun.com input

LOGLVSoutput

jxrun.com output

D3 D3 D3

D3 42 D3

42 D3 42

42 42 42

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DELCKT

DELCKT filename

Description

Specifies that LOGLVS drops the .SUBCKT names you specify, whetherthe .SUBCKT is empty or not. LOGLVS does not create box elements for anempty .SUBCKT.

Argument

filename Specifies the .SUBCKT names to delete.

Example

delckt delcel.tabcir cdlcon topx

The delcel.tab file looks like this.

tlow23 ---> subckt name to be dropped.

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DELECEL

DELECEL filename

Description

Removes logic gates in logic netlists such as TEGAS and Verilog. The fileformat is as follows:

■ The line starting with the string DELET is skipped.

■ The string after the first “=” character is read in as the top-down hierarchicalcell instance name and represents the gates and/or cells to delete.

■ “/” is the hierarchical name delimiter. The string after the instance name isignored.

■ Blank is the delimiter.

■ The maximum length of any line is 256 characters.

Argument

filename Specifies the gates and/or cells to delete in the file hierarchy.

Example

N = ANITA/TPC/DC_10 T = AN4N = ANITA/TPC/FD_10 T = FDN2PN = ANITA/INR/IPO_1 T = IVN = XX3939 T = BUF8AN = XX3945 T = BUF8AN = XX3943 T = BUF8AN = XX3941 T = BUF8A

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DXF

DXF

Description

Generates a cross reference file, EXPELE.LIS, which contains device numbersfollowed by the full path name for that device.

Caution

You must use this command before inputting logic or circuit-level files.

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EDIF

EDIF filename...

Description

Reads in EDIF netlist files. You can also use the NET command to read in EDIFnetlist files.

Argument

filename Names of the files containing the EDIF data files. If youdefine a macro twice, the second macro definition overridesthe first. Unlike the logic simulator, a macro has to bedefined before you reference it. If you use a CDL or SPICEfile, you must import it before parsing the EDIF netlist file.

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ENV

ENV new_number

Description

Increases the user-defined module name from the default of 1847 to a newvalue greater than or equal to the new number. The maximum number you canset is 10,000.

Arguments

new_number Number of modules you can set.

Example

ENV 10000

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EXIT

EXIT/X

Description

Stops the LOGLVS program. LOGLVS recognizes both EXIT and X.

When LOGLVS finishes, it returns one of the following three status codes in thePRINT.OUT file:

0 No errors or warnings1 Warnings, but no errors2 Errors

Example

The following is a C-shell example:

LOGLVS <<!lib ecad.tegcir ecad.cirlinkconx!If ($status ! = 0 ) exit 1

December 1999 5-147


FDELIMITER

*.FDELIMITER string

Description

Specifies delimiter characters for feedthrough pin names on the layout text. Thisfunction lets you specify separate feedthrough pin names on the layout andprevents Dracula from shorting all feedthrough pins. You can use*.FDELIMITER only in flat mode. You must specify all feedthrough pin names inthe CDL netlist file at the .SUBCKT statement. Specify the *.FDELIMITERcommand before the input netlist. LOGLVS generates a SCHFPIN.DAT filecontaining the feedthrough pin information.

When running PRE, the feedthrough pin text must be on the pad layer.

Argument

string One to four characters. The string cannot contain a space,a colon (:), a semicolon (;), or a question mark (?). If youspecify a string longer than four characters, Dracula reportsan error.

Example

In the following example, all pins with prefix Z@@10 are shorted together. Theresultant pin name is Z@@10.

LOGLVS !<<FDELIMITER &&CIR CDL.netlistCON TOP

December 1999 5-148


X!

.SUBCKT TOP OUT Z@@10&&86 Z@@10&&87 Z@@13&&88 Z@@13&&89 IP

...

December 1999 5-149


FPIN

FPIN

Description

Turns on the insertion of missing floating pins in instances. Apply to Verilognetlist when automatic floating node insertion is necessary. The FPIN commandis recomended whenever connection by explicit pin name is used in Verilog.Specify the FPIN command prior to the CONVERT command when you compilea netlist.

When using connections by explicit pin name in Verilog, an instance pin can bemissing if it is floating. For example, in the following module, BUF has pins I1,I2, and 0. When placed in another module, the I1 pin is floating. The Verilogstatement looks like this:

BUF X1 ( .I2(NET1), .O(NET2) ); /* instance pin I1 isfloating */

BUF X2 ( .I2(NET2), .O(SET), .I1(TET) )

To ensure the correct connection, use the FPIN command to enable theautomatic floating node insertion function.

Use the following command sequence when you use the FPIN command:

1. Issue the FPIN command.

2. Compile the CDL or SPICE netlist.

3. Compile the Verilog netlist.

December 1999 5-150


Example

The following command sequence is strongly recommended to make sure themodule is defined before using it.

LOGLVS <<!FPIN ;Turns on the insertion of missing floating CIRLIB.CDL ;pins in Verilog instances.VER TOP.TDLLINKCONVX!

December 1999 5-151


GENPAD

GENPAD

Description

Generates a special internal schematic initial correspondence file,6GPADS.DAT, which forces the LVS REDUCE module to use only names thatare in both 6PADL.DAT and 6GPADS.DAT. This eliminates additional layout textthat would cause REDUCE to form devices differently than the schematic side.

Use GENPAD before using the CONVERT command.

December 1999 5-152


GET

GET data

Description

Retrieves circuit library data or logic network data from disk files created by theSAVE command.

Arguments

data One of the following three values:

all Restores both circuit library and logic network data.

circuit Restores only circuit library data.

logic Restores only logic network data.

December 1999 5-153


GLOBAL

GLOBAL name1[:[P|G]] name2[:[P|G]] ... nameN[:[P|G]]

GLOBAL pfx1*[:[P|G]] pfx2*[:[P|G]] ... pfxN*[:[P|G]]

Description

Lets you specify power and ground nodes in LOGLVS.

Note: The GLOBAL command accepts multiple usage. All GLOBAL commandsare merged into a big *.GLOBAL command internally. The big internal*.GLOBAL command cannot be longer than 1280 characters.

Arguments

name Specifies a list of global node names. The names thatappear here must be the node names in the logic network.

:P/G You can assign a pad type to a global name by adding :Por :G to the name. P stands for power, and G stands forground.

The pad type must always attach to a global name or number even though thisglobal name or number is later replaced by a new name with an *.EQUIVcommand.

Example

POWER-NODE=Vdd* Vcc*

GROUND-NODE=Gnd* Vss*

December 1999 5-154


HELP

HELP command

Description

Displays information on your screen about a specified command.

Note: The HELP command might not display the most recent information aboutcommands.

Arguments

command The name of a LOGLVS command. You can abbreviate thecommand name to its first three letters. The commands forwhich you can get help are

CIRCUITCONVERTCOMMAND-FORMEXITGETINPUTLIBRARYLINKNETPRINTRESETSAVESTORETYPE

December 1999 5-155


Note: You must set the DRACHELP4 environment variable to the directorywhere the LOGLVS.HLP file is located (path/etc/drac_help/).

December 1999 5-156


HTV/DRE

HTV or DRE

Description

Generates files Dracula Interactive LVS needs for cross-probing.

Note: You must use this command before you input logic or circuit-level files.

December 1999 5-157


KCELL

KCELL <kcell_filename>

Description

Keeps cell texts in flat mode to improve LVSCHM performance.

Until the 4.8 release, Dracula kept only the top cell pin texts, but ignored all thepin texts of the cells below the top. This created two problems. The first problembeing that without the information of the cell pin text, some of the parallel groupscould be matched falsely. Secondly, without the cell pin text, the parallel groupstended to be bigger and slowed down the performance because breaking up ofthe parallel groups is costly.

In the 4.8 release, this new feature keeps the cell pin text in flat mode LVS thuseliminating false errrors and improving performance. This feature is applicableto the flat mode only.

Arguments

kcell_filenameSpecifies the name of the file containing the Kcell nametables

Example

KCELL ../myKcell.tab

CIR ../netlist.cdl

CON adder

December 1999 5-158


KFPIN

KFPIN

Description

Suppresses the filtering of floating nodes in cell instances when running incomposite mode. By default, Dracula assigns a floating pin on an HCELLinstance a node number of zero. To maintain the original floating node number,you must specify the KFPIN command. When you specify the KFPIN command,LOGLVS assigns non-zero node numbers to the floating pins.

Example

Sample command script:

LOGLVS <<!KFPIN ;Suppress the filtering of floatingCELL HCELL.TAB ;nodes in cell instances.CIR lib.cdlLIB gray.tegLINKCONVX!

December 1999 5-159


LIBRARY

LIBRARY{/option} filename...

Description

Reads the TEGAS5 logic library file.

Arguments





filename Names of the TEGAS5 library files. If a module is definedtwice, the second module definition overrides the first. Eachfile name can have up to 32 characters.

December 1999 5-160


LINK

LINK {top-module-name}

Description

Links and expands the library data into a logic network.

Arguments

top-module-name You must specify a top module name if your TEGAS file iswritten in random order or if you are using a Verilog netlistfile.

December 1999 5-161


NET

NET filename...

Description

Reads in EDIF netlist files. You can also use the EDIF command to read in EDIFnetlist files.

Arguments

filename Names of the files containing the EDIF data files. If youdefine a macro twice, the second macro definition overridesthe first. Unlike the logic simulator, a macro has to bedefined before you reference it. If you use a CDL or SPICEfile, you must import it before parsing the EDIF netlist file.

December 1999 5-162


NO_WARNING

NO_WARNING [TEGAS_PIN]

Description

Turns off the warnings from LOGLVS on ERC-type checks of the CDL netlist.The error messages are still printed.

To suppress warning messages from both input and output pins, specify theTEGAS_PIN option.

Use NO_WARNING before the CIRCUIT command.

Arguments

TEGAS_PIN Suppresses the warning messages from LOGLVS onexplicit pin connection checks. The error messages are stillprinted.

You must still specify the NO_WARNING command to suppress ERC-typechecks of the CDL netlist.

December 1999 5-163


NVER

NVER library_name top_cell_name

Description

Used to parse Verilog netlists. NVER reads Common Interface Representation(CIR) generated by VAN instead of reading netlists directly.

Note: Unlike the VER command, you do not need to run the LINK commandwhen using NVER.

Arguments

library_name User-specified library name. If you do not specify a libraryname, LOGLVS uses the default name.

top_cell_name User-defined cell name.

mylib The default library name. If there are only two arguments,LOGLVS assumes mylib to be the default and uses thesecond argument as top_cell_name. LOGLVS also issuesthe following warning:Library name missing. Assuming mylib.

Note: If mylib is the library name, LOGLVS continues after the warning.However, if mylib is not the library name, after the warning LOGLVS issues thefollowing message and stops:

Architecture not found in your design library.

December 1999 5-164


Example

case

cir data_mux.cir

nver lib_name bad_module

con/print bad_module

x

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PRECISION

PRECISION #

Description

Lets you specify the precision by which to specify device parameters. The LVSprecision cannot be better than LOGLVS.

Processes device parameters in .001 PRECISION.

Note: Outputs such as LVSLOGIC.DAT of this command can only be used byversions 4.7 or higher. You should run PDRACULA after LOGLVS. Then theprecision value can be passed to LVS comparison when you use this command.

Arguments

# Number of places after the decimal point 2~6. The default is2. The number of places before the decimal point plus thatafter the decimal point cannot be larger than 6.

December 1999 5-166


PRINT

PRINT lib

Description

Directs LOGLVS output to a printer.

Arguments

lib One of the following values:

CIRCUIT Acts on a circuit library.

LOGIC Acts on the logic network.

LIBRARY Acts on a TEGAS5 library.

December 1999 5-167


RESET

RESET data

Description

Resets the circuit library data, logic network data, or the logic library data.

Arguments

data One of the following values:

all Resets both circuit library data and logic network data.

circuit Resets only circuit library data.

logic Resets only logic data.

December 1999 5-168


RESISTOR

RESISTOR value

Description

Presets the resistor numbers. LOGLVS obtains swap spaces according to thisresistor number.

Argument

value The maximum number of resistors allowed in the circuit. Thedefault is 10,000. If the transistor number is less than thedefault, the specified number is ignored.

Caution

This command automatically restarts LOGLVS without anywarning.

December 1999 5-169


SAVE

SAVE data

Description

Saves the circuit library data or the logic library data files in program-assignedfiles. The SAVE command provides a reference file for LPEPRO. If you do notplan to run LPEPRO, you do not need to use SAVE.

Arguments

data Contains one of the following three values:

ALL Saves both circuit library and logic network data.

CIRCUIT Saves only circuit library data.

LOGIC Saves only logic data network. You must issue theSAVE LOGIC command before the CONVERT command.

December 1999 5-170


SET FANIN

SET FANIN value

Description

Specifies the maximum fan-in an instance can have. If the value you specify islarger than the default, Dracula uses the new value. Note that fan-in and fan-outare directly proportional: the larger the fan-in value is, the smaller the fan-outvalue is.

Argument

value Sets the fan-in value. Default is 218(262,144).

Example

In the following example, the fan-in value is changed to 219 (524,288).

: SET FANIN 300000

In the following example, the fan-in value remains the default value of 218

because the specified value is smaller than the default.

: SET FANIN 200000

December 1999 5-171


SET FANOUT

SET FANOUT value

Description

Specifies the maximum fan-out an instance can have. If the value you specify isbigger than the current value, Dracula uses the new value. Note that fan-out andfan-in are directly proportional: the larger the fan-out value, the smaller the fan-in value.

Argument

value Sets the fan-out value. The default is 214 (16,384).

Example

In the following example, the fan-out value remains the default value becausethe specified value is smaller than the default.

: SET FANOUT 10000

In the following example, the default value changes to 215 (32,768).

: SET FANOUT 20000

December 1999 5-172


STORE

STORE lib

Description

Stores LOGLVS output in a file, the circuit library, or the TEGAS5 logic librarydata.

Arguments


CIRCUITActs on a circuit library.LOGICActs on the logic network.LIBRARYActs on a TEGAS5 library.

December 1999 5-173


SUMMARY

SUMMARY

Description

Generates a summary of devices according to the device types and subtypes.Use SUMMARY after the CONVERT command.

December 1999 5-174


TEG

TEG{/option} filename...

Description

Reads in TEGAS netlist files.

Arguments

option Directs the command output.




filename The names of the files containing the TEGAS netlist files.The path to each file name can have up to 132 characters.

December 1999 5-175


TNAME

TNAME

Description

Lets you use top-level names as internal wires in the top cell when your designis composed of Verilog (or TEGAS) and CDL netlists. If you do not specify thiscommand, LOGLVS does not use the top-level names for internal wires.

December 1999 5-176


TRANSISTOR

TRANSISTOR value

Description

Presets the transistor numbers. LOGLVS obtains swap spaces according to thistransistor number. In order for this command to be effective, you must specify itfirst in the rules file.

Arguments

value The number of transistors needed by the circuit. The defaultis 100,000. If the transistor number you specify is smallerthan the default, this value is ignored.

Caution

This command automatically restarts LOGLVS without anywarning.

December 1999 5-177


TYPE

TYPE lib

Description

Directs LOGLVS output to the terminal.

Arguments


CIRCUITActs on a circuit library.LOGICActs on the logic network.LIBRARYActs on a TEGAS5 library.

December 1999 5-178


UNLIMIT

UNLIMIT

Description

This command is no longer supported. By default, LOGLVS creates a crossreference file, CROSREF.LIS, for long texts and their encoded string. If the netnames or cell names are long, CROSREF.LIS contains name mappinginformation. The CROSREF.LIS file is sorted and each entry appears only once.

The PRINT.OUT file no longer contains the cross reference list. A messageappears in the PRINT.OUT file referring you to the CROSREF.LIS file for crossreference information.

Example

The following example shows what the cross-reference pair in theCROSREF.LIS file looks like.

*1 = longStringLongerThan12Chars*2 = Xlevel1InTopCell*3 = MDeletionDv201

December 1999 5-179


VER

VER {/option} filename...

Description

Reads in Verilog netlist files.

Arguments

option Directs the command output.




filename The names of the files containing the Verilog netlist files.The path to each file name can have up to 132 characters.

December 1999 5-180


LOGLVS Example

Start LOGLVS by typing

LOGLVS

Dracula displays the following:

*********************************************************/N* LOGLVS(REV. 4.3 /SUN-4 /GENDATE: 14-AUG-95/07)

*** (Copyright 1995, Cadence) ***

*/N* EXEC TIME =16:00:22 DATE = 16-SEPT-95

******************************************************** currentxtrs estimate: 100000

DRACULA NETWORK COMPILER (LOGLVS) PROGRAM BEGINS..

**** COMMANDS SUMMARY ****

---- COMPILE HCELL TABLE FILE FIRST, ------- ---- THEN COMPILE TEGAS FILES ----- ---- THEN SPICE FILE ----

0) DATAFORMAT # : 4.2 :: Output 4.2 DataBase Format

1) TRANSISTOR # : pre-allocate virtual memory

2) HTV or DRE : generate Dracula Interactive files

DXF : generate EXPELE.LIS/EXPELE.CEL

UNLIMITED TX : turn unlimited text on

3) CASE : turn case sensitive on

4) CEL filename : compile H-CELL table file

December 1999 5-181


CEL/AUTO fn : AUTO CELL selection

CEL/BOX fn : HCELL becomes an empty SUBCKT (Blackbox) SPICE/CDL only

5) LIB filename : compile TEGAS-V netlist file

VER filename : compile VERILOG netlist file

6) CIR filename : compile SPICE/CDL netlist file

7) EDI filename : compile EDIF netlist file

8) LINK : expand logic network

9) GENPAD : generate 6GPADS.DAT file

10) CON : convert LOGIC NETWORK into XTR file

CON cellname : convert TOP CELL into XTR file

CON/NOTOP : convert CELL into XTR file for DRAC3

11) SUMMARY : print ELEMENT summary by types

12) NO_WARNING : turn connection checking off

13) EXIT/X/x : EXIT

December 1999 5-182


Using Hierarchical LOGLVSWhen running LOGLVS for an HLVS run, you must first use the CELL commandto input the Hcell file.

When you run hierarchical LOGLVS, a menu of commands appears on thescreen. You can use the following commands with hierarchical LOGLVS. The“Running LOGLVS” section describes them in detail.

CASECELLCIRCUITCONVERTEDIFEXITINPUTLIBRARYLINKVER

The following examples show how to run hierarchical LOGLVS.

SPICE Examples

Flat mode

:CIR file-a ; Specifies CDL file.:CON cell-name:X

Cell mode

December 1999 5-183


:CEL cell.tab:CIR file-a ; Specifies CDL file.:CON/NOTOP ; Indicates that file-a lists

; no top level circuits. This is optional.:X

Composite mode

:CEL/box cell.tab:CIR file-a ; Specifies CDL file.:CON cell-name

:X

EDIF TEGAS, and Verilog Examples

Flat mode

:CIR file-b ; Specifies CDL file.:EDI/INP/LOG/LIB/VER file-a ; Specifies netlist.:LINK:CON ; As in flat modeDracula.:X

Cell mode

:CEL cell.tab ; cell.tab describesHcells.:CIR file-b ; Specifies CDL file.:EDI/INP/LOG/LIB/VER file-a ; Specifies netlist.:LINK:CON ; As in flat mode Dracula.:X

Composite mode

:CEL/box cell.tab ; cell.tab describesHcells.

December 1999 5-184


:CIR file-b ; Specifies CDL file.:EDI/INP/LOG/LIB/VER file-a ; Specifies netlist.:LINK:CON ; As in flat mode Dracula.:X

Note: You must include a LINK command for the top level module of a Verilognetlist or of a TEGAS netlist in random order.

CDL and SPICE Formats

You can use a SPICE netlist for running cell mode and composite mode HLVS.The first character of each text item on the layout must be an alphabeticcharacter. Because true SPICE format allows only numbers to specify nodes,use a CDL netlist containing names to identify nodes.

You can use the following commands in the CDL or SPICE subcircuit file:

*.PIN VDD VSS .... etc

Place the *.PIN command at the top of the CDL or SPICE subcircuit netlist toindicate that these global I/O terminals exist for each subcircuit.

If the *.PIN command for an HLVS netlist is missing from the CDL or SPICE file,LOGLVS issues a warning. LOGLVS also issues a warning if there are anyunused outputs in a .SUBCKT command that contain multiple outputs. Here isan example:

.SUBCKT dff q qbar in clk clkbar set reset

If q is not used in the schematic netlist, Dracula issues a warning that q is usedonly once in the netlist.

*.NOPIN pin1 pin2 .... etc

December 1999 5-185


This *.NOPIN command overrides the designation of the *.PIN command andspecifies that these global I/O terminals are not part of this specific Hcellsubcircuit.

HLVS accepts a true SPICE netlist. LOGLVS accepts a local *.EQUIV commandin the .SUBCKT command. You must specify the *.EQUIV command before anydevice commands.

$ TRUE SPICE FILE $*.SPICE*.GLOBAL 0:G 99:P*.PIN 0 99*.EQUIV vss=0 vdd=99*+ d6=11 d5=12 d4=13 d3=14 d2=15 d1=16*+ g=23 ol=24 o2=25 o3=26 o4=27*.SUBCKT inv 3 6*.EQUIV in=6 out=3mnl 3 6 0 0 n 5 2mpl 3 6 99 99 p 10 2.ENDS inv

.SUBCKT top 11 12 13 14 15 16 23 24 25 26 27

.

.x1 44 11 invx2 . . . . . . . . . ....ENDS top

December 1999 5-186


TEGAS Format

You can use a TEGAS netlist for running cell mode and composite mode HLVS.However, you must observe the following restrictions when using the TEGASformat for Hcell descriptions:

■ Declare the TEGAS Hcell descriptions as modules. These give netlistconnectivity information, but cannot be used for primitive-level cells, whichcontain transistor-level information.

■ Every TEGAS Hcell requires a HEADER section in the CDL or SPICE fileto include *.NOPIN, *.PIN, and .SWAP commands.

December 1999 5-187


Hcell Definition Examples

This section contains Hcell definition examples. The Hcell is named HCELL1.Its inputs are A, B, and C, and its outputs are D, E, and F.

Example 1

TEGAS

MODULE HCELL1;INPUT A,B,C;OUTPUT D,E,F;DEFINE:.. netlist information in TEGAS format..END;

CDL

*.GLOBAL VDD,VSS*.PIN VDD,VSS.SUBCKT HCELL1 D E F A B C(*.NOPIN ..... ) ( optional ).. netlist information in CDL format (may be empty)...ENDS

Example 2

/ ********************************************************* /

/ * TEGAS TDL FOR GRAYCODE DESIGN */

/ * For running composite mode or cell mode */

/ ********************************************************* /

December 1999 5-188


MODULE: GRAYCODE ;

INPUT: CA MC1 SCT1 SCT2 SCT3 SCT4 ;

OUTPUT: Q1B Q2B Q3B Q4B CO ;

DEFINE:

VDD = PWR ;

VSS = GRND ;

CLK = INV(CA) ;

CLR1= INV(MC1) ;

N1A(Q1,Q1B)=JKFF1(CLK,VDD,VDD,SET1,CLR1) ;

SET1= INV(SCT1) ;

SET2= INV(SCT2) ;

N1B(Q2,Q2B)=JKFF1(CLK,Q1,Q1,SET2,CLR1) ;

S2 = NA2(Q1,Q2) ;

S2BAR= INV(S2) ;

R1A(Q3,Q3B)=JKFF1(CLK,S2BAR,S2BAR,SET3,CLR1) ;

SET3= INV(SCT3) ;

S3 = NA3(Q1,Q2,Q3) ;

S3BAR= INV(S3) ;

R1B(Q4,Q4B)=JKFF1(CLK,S3BAR,S3BAR,SET4,CLR1) ;

GH3D(SET4)=INV(SCT4) ;

TU2(CARRY)=NA4(Q1,Q2,Q3,Q4) ;

CIN = NOR(CARRY,CA) ;

RS2C(CO)=INV(CIN) ;

END ;

**********************************************

December 1999 5-189


** SPICE LIBRARY FOR GRAYCODE ***

**********************************************

*.GLOBAL VDD,VSS

*.PIN VDD VSS

.SUBCKT NA2 Z A B

* 2 INPUT NAND

MP1 Z A VDD VDD P

MP2 Z B VDD VDD P

MN1 Z A 5 VSS N

MN2 5 B VSS VSS N

.ENDS NA2

*

.SUBCKT NA3 Z A B C

* 3 INPUT NAND

.SWAP A B C

MP1 Z A VDD VDD P

MP2 Z B VDD VDD P

MP3 Z C VDD VDD P

MN1 Z A 6 VSS N

MN2 6 B 7 VSS N

MN3 7 C VSS VSS N

.ENDS NA3

*

.SUBCKT NA4 Z A B C D

* 4 INPUT NAND

MP1 Z A VDD VDD P

December 1999 5-190


MP2 Z B VDD VDD P

MP3 Z C VDD VDD P

MP4 Z D VDD VDD P

MN1 Z A 7 VSS N

MN2 7 B 8 VSS N

MN3 8 C 9 VSS N

MN4 9 D VSS VSS N

.ENDS NA4

*

.SUBCKT NOR Z A B

* 2 INPUT NOR

MP1 5 B VDD VDD P

MP2 Z A 5 VDD P

MN1 Z A VSS VSS N

MN2 Z B VSS VSS N

.ENDS NOR

*

.SUBCKT INV Z A

*INVERTER

MP1 Z A VDD VDD P

MN1 Z A VSS VSS N

.ENDS INV

*

.SUBCKT JKFF1 Q QN CL J K S R

MP1 6 CL VDD VDD P

MN2 6 CL VSS VSS N

December 1999 5-191


MP3 5 6 VDD VDD P

.

.

.

.

.

.

MN43 42 J VSS VSS N

MN44 44 39 45 VSS N

MN45 45 QN VSS VSS N

MN46 45 K VSS VSS N

.ENDS JKFF1

*

Hcell file (hcell.tab)

JKFFJKFF1INV INVND2 NA2ND3 NA3ND4 NA4NO2 NOR

December 1999 5-192


LOGLVS ExamplesThis section shows an example of a dual CMOS JK flip-flop. The following figureshows the schematic diagram of the JK flip-flop at the transistor level. Thefigures on the following pages show the same network redrawn at the logic leveland transistor level implementation of cells. The network is composed of twoidentical flip-flops with only power and ground in common.

Each of the netlist examples in the sections on the SPICE and TEGAS formatsdescribe the schematic in this example. The “Preparing TEGAS5 Files” sectionshows the CDL circuit description of the schematic.

Each cell name is listed at the top of the cell placement. The I/O pin names arealso listed.

JK Flip-flop Logic Level

K

J

clock

Q1

Q2

Q9 Q10

S1

SET

Q3Q4 Q5

S3

S4

Q8

Q7

QBQ6S2

RESET

NO2

(NOR)

A

B

B

AANI

C

ON

P

OA

B

NO2

(NOR)(NOR)

NO2

N (CXFR)O

NO2

(NOR)

N

P

O I

(NOR)

NO2 (INV)

(INV)

I

I

I(ROM #ANI)

(CXFR)

P

Q

December 1999 5-193


Transistor-Level Implementation

N I1O

I

I1 (or INV)P

VCC

O

GND

I

J001

J002

N

P

VCC

O

GND

I

J001

J002

December 1999 5-194


Transistor-Level Implementation (continued)

SPICE

In this example, the SPICE netlist is in the SPIC.CIR file. The cell nameJKFF4627 in the CON command indicates that this cell will be converted.


ENTER COMMAND:CIR SPIC.CIRREADING SPIC.CIRFILE SPIC.CIR INPUT

A

O

A

B

C

B

ANI

AN1 (or ROM #AN1)

C

J004

J002

P

J003

J001

1

VCC

P

N

O

J006

P

N2

J005N

GND

December 1999 5-195


ENTER COMMAND:CON JKFF4627TRANSISTOR-LEVEL FILE: LVSLOGIC.DAT CREATEDNUMBER OF TRANSISTORS (OR ELEMENTS):92

ENTER COMMAND:EXIT

TEGAS5

Use the following steps to compile the TEGAS5 network file. In this example, theTEGAS netlist is in JKFF.TEG and the circuit description file is in JKFF.CIR.


ENTER COMMAND:LIB JKFF.TEGREADING JKFF.TEGFILE JKFF.TEG INPUTLOGIC LIBRARY FILE INPUT AND PROCESSED

ENTER COMMAND:CIR JKFF.CIRREADING JKFF.CIRFILE JKFF.CIR INPUTCIRCUIT FILE INPUT AND PROCESSED

ENTER COMMAND:LINK

ENTER COMMAND:CONTRANSISTOR-LEVEL FILE:LVSLOGIC.DAT CREATEDNUMBER OF TRANSISTORS (OR ELEMENTS):92

ENTER COMMAND:EXIT

December 1999 5-196


Specify a TOPMODULE name in a LINK command if your TEGAS file is inrandom order.

Documents

Compiling Network Descriptions (LOGLVS)