CompArchCh03L06ArrayMult

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Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009

1

Lesson 06:

Array Multiplier

Chapter 03: Computer ArithmeticComputer Arithmetic




2

Objective

• Learn Array Multiplier method




3

Multiplication Process

By Array Multiplier




4

Multiplication of decimal 11 (0b1011),

multiplicand (Y ) by the decimal 5 (0b0l01)

• Multiplication of decimal 11 (0b1011)

• Multiplicand (Y ) by the decimal 5 (0b0l01)• Multiplier ( X )

• An n-bit × n bit multiplication done in steps




5



• Step A: First, 0b1011 is copied by each bit of

0b0l01 to get the product by lsb (=1)• Step B: then 0b1011 is taken as 0b0000 to get

the product by next to lsb (= 0) shown in the

second line

• Step C: then 0b1011 is copied by each bit of

0b0l01 to get the product by next to next of lsb=(1) shown in the third line




6



• Step D: then 0b1011 is taken as 0b0000 to get

the product by msb (=0) shown in the fourthline.

• The four results are added to get the final result.

Note that each successive line is shifted to the

left one position to the left to account for the

differing place values of the bits in the second

input




7

Array multiplier method

0b1011 ×××× multiplicand (Y ) by 0b0l01

• Step A: n × n Partial product generation using

array of AND gates by multiplying x0.y0, x0.y1,…, up to xn−1. yn−1 in parallel at the same time

• n = 4 in the example of multiplying 0b1011 with

0b0l01




8



• Step B: Use adders to add the partial products at

the n-levels. Note that each level m partial product x x

m.y

0, x

m.y

1, …, up to x

1. y

n–1is shifted

to the left one position to the left to account for

the differing place values of the bits in thesecond input



Schaum’s Outline of Theory and Problems of Computer ArchitectureCopyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009 9



• Step C: Generating final result using two-bit

operand adders




Step A: Partial product generation using

array of AND gate

• x0.y0, x0.y1, …, up to x0. y4−1in array of ANDs at thesame time

• Then x1.y0, in array x1.y1, …, upto x1. y4−1 of ANDs in parallel atthe same time

• and so on

0b1011

× 0b0101

1011 level 0

0000 level 1

1011 level 2

0000 level 3

+0b110111




Step A

• Partial product generation using array of 2-bit

ADDERs at (n − 1) levels• Logic circuit of generating partial products at

each level using 4 ANDs in 4 × 4 array of

ANDs when n = 4




Array Multiplier

• Refer Figure 3.21




Step B


ADDERs at (n − 1) levels




Step C


ADDERs at (n − 1) levels




Designing Array Multiplier

• Total Number of logic units in n-bit × m bit

Array Multiplier • n × m two-input ANDs and (m – 1) units of n-bit

adders




Total Delay in n-bit ×××× m bit Array Multiplier

• Delay due to ANDs in partial products at all

level is just one unit AND gate delay. But delayat levels 1 to (m – 1) units of n-bit adders = (m –

1) × delay of one-unit 16-bit adder

• The delay in adders is very large if ripple carryadders are used

• The delay in adders reduced by using carry-look-ahead adders




Advantage of Array Multiplier

1. An array multiplier ─ a multiplication method in

which an array of identical cells generates new partial product and accumulation of it at the

same time



Schaum’s Outline of Theory and Problems of Computer Architecture

Copyright © The McGraw-Hill Companies Inc. Indian Special Edition 2009 18


2. We can use pipelines at each level

• Result from the adder can be latched at eachlevel and used as input for next level adder

circuit






3. The delay is logarithmically proportional to the

bit size of multiplicand and multiplier if we usethe high speed array multiplier circuit





Disadvantage of Array Multiplier

• Large number of logic gates required to design

an array multiplier





Summary





• Multiplication circuit becomes fast by array

multiplier • A multiplication method in which an array

of identical cells generates new partial

product and accumulation of it at the sametime

We learntWe learnt





End of Lesson 06 on

Array Multiplier Circuit

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CompArchCh03L06ArrayMult