(Common to CSE & ISE) Sub Code: 06CSL38 IA Marks: 25

Electronic Circuits & Logic Design Lab 3 rd

–Semester 06CSE / 06ISE38

(Common to CSE & ISE)

Sub Code: 06CSL38 IA Marks: 25

Hrs / Week : 03 Exam Hours : 03

Total Hrs: 42 Exam Marks: 50

PART – A

1. a. To study the working of positive clipper, double-ended clipper and positive

Clamper using diodes.

b. To build and simulate the above circuits using a simulation package

2. a. To determine the frequency response, input impedance, output impedance, and

bandwidth of a CE amplifier.

b. To build the CE amplifier circuit using a simulation package and determine the

voltage gain for two different values of supply voltage and for two different

values of emitter resistance.

3.a. To determine the drain characteristics and transconductance characteristics of

an enhancement-mode MOSFET.

b. To implement a CMOS inverter using a simulation package and verify its

truthtable.

4. a. To design and implement a Schmitt trigger using Op-Amp for given

UTP and LTP values.

b. To implement a Schmitt trigger using Op-Amp using a simulation

package for two sets of UTP and LTP values.

5. a. To design and implement a rectangular waveform generator (Op-Amp

relaxation oscillator) for given frequency.

b. To implement a rectangular waveform generator (Op-Amprelaxation oscillator)

using a simulation package and observe the change in frequency when all

resistor values are doubled.

6. To design and implement an astable multivibrator circuit using 555

timer for a given frequency and duty cycle.

7. To implement a +5V regulated power supply using full-wave rectifier

and 7805 IC regulator in simulation package. Find the output ripple

for different values of load current.

http://www.neevia.com



PART – B

1. a. Given any 4-variable logic expression, simplify using Entered

Variable Map and realize the simplified logic expression using 8:1

multiplexer IC.

b. Write the Verilog /VHDL code for an 8:1 multiplexer. Simulate andverify its

working.

2. a. Realize a full adder using 3-to-8 decoder IC and 4 input NAND gates.

b. Write the Verilog/VHDL code for a full adder. Simulate and verify its working.

3. a. Realize a J-K Master/Slave Flip-Flop using NAND gates & verify its truth table.

b. Write the Verilog/VHDL code for D Flip-Flop with positive-edge triggering.

Simulate and verify its working.

4. a. Design and implement a mod-n (n<8) synchronous up counter using

J-K Flip-Flop ICs.

b. Write the Verilog/VHDL code for mod-8 up counter. Simulate & verify its

working.

5. a. Design and implement a ring counter using 4-bit shift register.

b. Write the Verilog/VHDL code for switched tail counter. Simulate & verify its

working.

6. Design and implement an asynchronous counter using decade counter

IC to count up from 0 to n (n<=9).

7. Design a 4-bit R-2R ladder D/A converter using Op-Amp. Determine

its accuracy and resolution.

Note 1. Any simulation package like MultiSim / Pspice etc. may be used.




1a. CLIPPING AND CLAMPING CIRCUITS

AIM: To study the working of positive clipper, double ended clipper and positive

clamper using diodes.

COMPONENTS REQUIRED: Diode (BY-127 / IN4007), Resistors-10 KΩΩΩΩ & 3.3kΩΩΩΩ, DC

regulated power supply ( Vref), Signal generator (for Vi) and CRO.

THEORY:

Clipper is a circuit with which the waveform is shaped by removing a portion of

the applied wave. Clippers clip off a portion of the input signal without distorting the

remaining part of the waveform.

In the positive clipper shown above the input waveform above Vref is clipped

off. If V ref = 0V, the entire positive half of the input waveform is clipped off.

To clip the negative half of the waveform, reverse the polarities of the diode in

the circuit, which results in negative clipping.

Plot of input Vi (along X-axis) versus output Vo (along Y-axis) called transfer

characteristics of the circuit can also be used to study the working of the clippers.

CIRCUIT DIAGRAM OF POSITIVE CLIPPER:

Fig.1 a Positive clipper Circuit b. Transfer Characteristics




DESIGN:

From the circuit of the clipper

Vomax = Vref + Vγγγγ Let Vγγγγ = 0.6v

∴ Vref = Vomax - Vγγγγ

∴ = 2 - 0.6 = 1.4v

Vref = 1.4v to clip the positive peak above +2v.

The value of R is choosen using the expression R = √√√√(Rf*Rr)

Where Rf = forward resistance of diode = 10ΩΩΩΩ

Rr = reverse resistance of diode = 1MΩΩΩΩ

Therefore R = √√√√(10*1*106) = 3.16kΩΩΩΩ

Let

R = 3.3 kΩΩΩΩ.

Characteristics expected:

Vout

2v

0 2v Vin

PROCEDURE:

1. Before making the connections check all components using multimeter. 2. Make the connections as shown in circuit diagram. 3. Using a signal generator (Vi) apply a sine wave of 1KHz frequency and a peak-

to-peak amplitude of 10V to the circuit. (Square wave can also be applied.) 4. Keep the CRO in dual mode, connect the input (Vi) signal to channel 1 and

output waveform (Vo) to channel 2. Observe the clipped output waveform which is as shown in fig. 2. Also record the amplitude and time data from the waveforms.

5. Now keep the CRO in X-Y mode and observe the transfer characteristic waveform.




Note: 1. Vary Vref and observe the variation in clipping level. For this use

variable DC power supply for Vref.

2. Change the direction of diode and Vref to realize a negative clipper.

3. For double-ended clipping circuit, make the circuit connections as shown in fig.3 and the output waveform observed is as shown in figure 5. 4. Adjust the ground level of the CRO on both channels properly and view the output In DC mode (not in AC mode) for both clippers and clampers.

WAVEFORMS :

Fig. 2. Input and output waveform for positive Clipper

RESULT:

Output of clipper circuit verified




DOUBLE ENDED CLIPPER

THEORY:

With a double-ended clipper, a portion of both the positive and negative half

cycles of input voltage can be removed or clipped.

OPERATION: When positive input voltage is greater than Vref1, diode D1 Conducts

heavily,D2 remains reverse biased. Therefore a voltage Vref1 appears across the load.

This output stays at Vref1 ,so long as the input voltage exceeds Vref1.On the other

hand, during the negative half cycle ,the diode D2 will conduct heavily and the output

stays at Vref2.So long as the input voltage is greater than Vref2.Between Vref1 and

Vref2 neither diode is ON.

CIRCUIT DIAGRAM:

Fig.3 Double ended clipper Circuit b. Transfer Characteristics

Design: From the circuit of the clipper circuit

Let the clipping points be = 4v and -4v

we have Vomax = Vr + Vγγγγ

Vr1 = Vr2 = Vomax - Vγγγγ

= 4 - 0.6 = 3.4v




The value of R is choosen using the expression R = √√√√(Rf*Rr)

Where Rf = forward resistance of diode = 10ΩΩΩΩ

Rr = reverse resistance of diode = 1MΩΩΩΩ

Therefore R = √√√√(10*1*106) = 3.16kΩΩΩΩ

Let R = 3.3kΩΩΩΩ.

Transfer characteristics Expected:

+4

-4

+4 Vin

WAVEFORMS:

Fig. 4. Input and output waveform for double-ended clipping circuit




Note: The above clipper circuits are realized using the diodes in parallel with the

load (at the output), hence they are called shunt clippers. The positive (and negative)

clippers can also be realized in the series configuration wherein the diode is in series

with the load. These circuits are called series clippers.

RESULT:

Output of double-ended clipper circuit verified

POSITIVE CLAMPER:

THEORY:

The clamping network is one that will “clamp” a signal to a different DC level.

The network must have a capacitor, a diode and a resistive element, but it can also

employ an independent DC supply (Vref) to introduce an additional shift. The

magnitude of R and C must be chosen such that time constant ζ=RC is large enough

to ensure the voltage across capacitor does not discharge significantly during the

interval of the diode is non-conducting.

COMPONENTS REQUIRED: Diode (BY-127), Resistor of 200 KΩΩΩΩ, Capacitor - 0.1 µµµµF, DC

regulated power supply, Signal generator, CRO

CIRCUIT:

Fig. 5 Positive Clamper




DESIGN:

Say for τ = 20msec (corresponding to a frequency of 50 Hz), then for RC >> τ, let

C=0.1µF, then R ≥ 200KΩ.

Clamper to clamp the positive peak at +3V.

Design: From the circuit of the clamper

Applying KVL, - Vref + Vγγγγ + Vomax = 0

Then Vomax = Vref - Vγγγγ Let Vγγγγ = 0.6V

∴ Vref = Vomax + Vγγγγ

∴ = 3 + 0.6 = 3.6V

∴ Vref = 3.6v to clamp the positive peak at +3V.

Let f = 1khz. ∴∴∴∴ T = 1msec. Let R = 10kΩΩΩΩ

For the circuit to perform satisfactorily RC = 10T

Therefore C = 10T / R = 10*1m / 10k

Therefore C = 1µµµµF.

PROCEDURE :

1. Before making the connections check all components using multimeter. 2. Make the connections as shown in circuit diagram (fig. 5). 3. Using a signal generator apply a square wave input (Vi) of peak-to-peak

amplitude of 10V (and frequency greater than 50Hz) to the circuit. (Sine wave can also be applied)

4. Observe the clamped output waveform on CRO which is as shown in Fig. 6.

Note: 1. For clamping circuit with reference voltage Vref, the output waveform is

observed as shown in Fig. 7. For without reference voltage, Keep Vref = 0V.

2. CRO in DUAL mode and DC mode. Also the grounds of both the channels can

be made to have the same level so that the shift in DC level of the output can be

observed.

3. For negative clampers reverse the directions of both diode and reference

voltage.




WAVEFORMS:

Fig. 6 Input and output waveform for positive clamper without reference voltage.

Fig. 7 Input and output waveform for positive clamper circuit with reference voltage= 2V

RESULT:Output of clamper circuit verified




2a. CE AMPLIFIER

AIM: To determine the frequency response, input impedance, output impedance and

bandwidth of a CE amplifier.

COMPONENTS REQUIRED: Transistor SL-100, Resistors -16 KΩΩΩΩ, 3.9 KΩΩΩΩ, 820ΩΩΩΩ, 220 ΩΩΩΩ,

Capacitors - 0.47 µµµµF, 100 µµµµF, DC regulated power supply, Signal generator, CRO

THEORY:

The frequency response of an amplifier is the graph of its gain versus the

frequency. Fig. 3 shows the frequency response of an ac amplifier. In the middle

range of frequencies, the voltage gain is maximum. The amplifier is normally operated

in this range of frequencies. At low frequencies, the voltage gain decreases because

the coupling (CC in Fig.1) and bypass (CE) capacitors no longer act like short circuits;

instead some of the ac signal voltage is attenuated. The result is a decrease of

voltage gain as we approach zero hertz. At high frequencies, voltage gain decreases

because the internal (parasitic) capacitances across the transistor junctions provide

bypass paths for ac signal. So as frequency increases, the capacitive reactance

becomes low enough to prevent normal transistor action. The result is a loss of

voltage gain.

Cutoff frequencies (f1 & f2 in Fig. 3) are the frequencies at which the voltage

gain equals 0.707 of its maximum value. It is also referred to as the half power

frequencies because the load power is half of its maximum value at these

frequencies.




CIRUIT DIAGRAM:

Fig. 1 : Transistor as a CE amplifier circuit diagram and actual connections

(does not show RL)


Electronic Circuits & Logic Design Lab

Fig. 2: CE Amplifier with DRBs

DESIGN 1:

Given: &5,10 == mAIVV CCC

To find RE, let RIV EERE ==

Hence ===5

1

mI

V

I

VR

C

RE

E

REE

To find RC, RC determines the Q

Applying KVL to the CE loop (in Fig. 1),

Substituting all the values we get R

value)

To find R1: We have VV BEB =

Assuming that the biasing network (R

R1, we have BR VRIV == 1101

Ω.



Fig. 2: CE Amplifier with DRBs connected at both input and output

100& =β

VVCC 110

1= , and CE II ≅

Ω= 200m

. Choose RE = 220Ω.

determines the Q-point. Choose RC such that VCE = VCC/2 = 5V

Applying KVL to the CE loop (in Fig. 1), 0=−−− RECECCCC VVRIV .

Substituting all the values we get RC = 800Ω. Choose RC = 820Ω(standard resistor

VVREBE 7.117.0 =+=+ and mI

I CB β 100

5==

the biasing network (R1 & R2) is designed such that 10

BCC VV − . Substituting the values of Vcc, V

Values

R

R

R

R

06CSE / 06ISE38

connected at both input and output

/2 = 5V

standard resistor

Aµ50=

) is designed such that 10IB flows through

. Substituting the values of Vcc, VB & IB, R1 = 16.6k

Values

R1 = 18kΩ

R2 = 3.9kΩ

RC = 820Ω

RE = 220Ω




Next to find R2, we have VR2 = 9IBR2 =VB. Hence Ω=×

== KAI

VR

B

B 7.3509

7.1

92 µ

. Choose

R1= 18kΩ and choose R2 =3.9kΩ

To find the bypass capacitor CE: Let XCE = RE/10 at f = 100 Hz (remember CE & RE are in

parallel). Hence 102

1 E

E

CE

R

fCX ==

π. Substituting all the values,

CE = 72.3 µF.

Choose CE =100 µF and the coupling capacitors CC1 = CC2 = 0.47 µF.

Design 2:

Let Vcc = 12V; IC = 4mA; VE = 2V; VCEQ = 6v; hfe = 100.

To find RE :

Given VE = 2v.

Therefore RE = VE / IE ≈≈≈≈ VE / IC

∴∴∴∴ RE = 2 / 4mA = 500ΩΩΩΩ

RE = 470ΩΩΩΩ ( standard)

To find RC:

From the collector loop writing KVL we get VCC = ICRC + VCE + VE

∴∴∴∴ RC = (VCC – VCE – VE) / IC

= ( 12 - 6 - 2 ) / 4mA

∴∴∴∴ RC = 1 kΩΩΩΩ

To find R1 and R2:

The base current IB = IC / hfe

= 4mA / 100

= 0.04mA.

Let I1 be current through R1 and I1 be 10 times of IB

i.e. I1 = 10 * IB = 10 * 0.04mA = 0.4mA

Writing the base loop KVL we get VB = VE + VBE

= 2 + 0.7

VB = 2.7V




Now R1 = (VCC – VB ) / I1

= (12 - 2.7 ) / 0.4mA

= 23.5 kΩΩΩΩ

R1 = 22 kΩΩΩΩ.

Also R2 = VB / I1

= VB / (I1 – IB) = 2.7 / ( 0.4mA – 0.04mA) = 7.5k

R2 = 8.2 kΩΩΩΩ

Input impedance ( Zin) :

In order to calculate the input impedance first calculate the value of Zin(base).

Zin(base) = ββββre′′′′ where re

′′′′ is the resistance of emitter diode.

re′′′′ ≅≅≅≅ 25mV / IC

= 25mV / 4mA = 6.25ΩΩΩΩ

Zin(base) = ββββre′′′′ = 100 * 6.25 = 625ΩΩΩΩ

The input impedance of an amplifier is the input impedance seen by the a.c. source

driving the amplifier. Therefore the biasing resistor R1 and R2 are included as follows

Zin = Zin(base) |||||||| R1 |||||||| R2.

= 625 |||||||| 22K |||||||| 8.2K

Zin = 0.566 kΩΩΩΩ

Output impedance (Zo):

The output impedance is given by Zo = RC |||||||| RL

Let RL = 10 kΩΩΩΩ.

Therefore Zo = 1k |||||||| 10k = 909ΩΩΩΩ

Zo = 909ΩΩΩΩ

To find CC1 , CC2 and CE :

Input coupling capacitor CC1 = 1 / ( 2*ππππ*Zin*Fin)

Let Fin = 200hz.




PROCEDURE:

1. Before making the connections check all components using multimeter. 2. Make the connections as shown in circuit diagram. 3. Using a signal generator apply a sinusoidal input waveform of peak-to-peak

amplitude 20mV ( = Vin) to the circuit and observe the output signal on the CRO.

4. Vary the frequency of input from 50Hz to 1MHz range and note down corresponding output voltage VO in the tabular column.

Note: When the input frequency is being changed the input amplitude

(i.e., around 20 mV) should remain constant.

Adjust the amplitude of Vin (in mV) such that the output Vo does not get

clipped (i.e., saturated) when the frequency is in the mid range say 1kHz.

5. After the frequency has been changed from 50 Hz to 1MHz and the readings are tabulated in a tabular column, calculate gain of the amplifier (in dB) using the formula, Gain in dB = 20 log 10 (Vo/Vin)

6. Plot the graph of gain versus frequency on a semilog sheet and hence determine the bandwidth as shown in Fig. 3. Bandwidth = B = f2-f1

TO MEASURE Zi :

1. To find input impedance, set the input DRBI to a minimum value and DRBO to a maximum value (say, 10k) as shown in figure 2.

2. Now apply an input signal using signal generator, say a sine wave whose peak-to-peak amplitude is 50mV with a frequency of 10 KHz.

3. Observe the output on CRO. Note this value of output with DRBI = 0 as Vx. 4. Now increase the input DRBI value till the output voltage Vo = (1/2) Vx. The

corresponding DRBI value gives input impedance.




TO MEASURE Zo :

1. To find output impedance, set DRBO which is connected across the output to a maximum value as shown in figure 2, with the corresponding DRBI at the minimum position.

2. Apply the input signal using signal generator, say a sine wave whose peak-to-peak amplitude is 50mV with a frequency of 10 KHz.

3. Observe the output on CRO. Note this value of output with DRBI = 0 as Vx. 4. Now decrease the DRBO value till the output voltage Vo = (1/2) Vx. The

corresponding DRBO value gives output impedance.

DRB

RC Coupled

Amplifier

Vi Vo

RC Coupled

Amplifier

Vi Vo DRB




Note: DRBI is connected between the signal generator and the input coupling

capacitor. DRBO is connected across the output (across the CRO terminals).

The ground symbol in the circuit diagram implies a common point. In some of the

power supplies, there will be three terminals - +(plus), -(minus) and GND (ground).

Never connect this GND terminal to the circuit.

TABULAR COLUMN

Vi = 50 mV (P-P)

f

in Hz

V0 P-P

volts

AV =iV

V0 Power Gain = 20 log10 Av

in dB

50 Hz

--

--

1 MHz

WAVEFORMS:




FREQUENCY RESPONSE:

Fig. 3 Frequency response plotted on semilog graph (X-axis is log scale)

RESULT:

1. BANDWIDTH = Hz

2. INPUT IMPEDANCE = Ω

3. OUTPUT IMPEDANCE = Ω

Note: Maximum gain occurs in mid frequency region. This is also called mid band

gain.

Gain-bandwidth product = Midband gain x Bandwidth




3a. CHARACTERISTICS OF AN ENHANCEMENT MODE MOSFET

AIM: To determine the drain characteristics and transconductance characteristics

of an enhancement mode MOSFET.

COMPONENTS REQUIRED: MOSFET (1RF 740), Resistor (1kΩ), Voltmeters (0-30V

range and 0-10V range), Ammeter (0- 25mA range) and Regulated power supply (2

nos. – variable power supply)

THEORY:

MOSFET is an important semiconductor device and is widely used in many

ciruits applications. The input impedence of a MOSFET is much more than that of

a FET because of very small gate leakage current. In MOSFET ,the source to drain

current is controlled by the electric field of capacitor formed at the gate.MOSFET

has no gate diode this make it to operate device with positive and negative

voltage.The input impedence is high(MΩΩΩΩ).

CIRCUIT DIAGRAM:

Fig.1a.Depletion mode(negative gate voltage) &

b.Enhancement mode(positive gate voltage)




Sample Characteristics to be obtained

Fig. 2 a. Drain Characteristics and b. Transconductance (or mutual/transfer) characteristics

PROCEDURE :

1. Make the connections as shown in the corresponding circuit diagram. Special care to be taken in connecting the voltmeters and ammeters according to the polarity shown in circuit diagram figures.

2. Repeat the procedure for finding drain and transconductance characteristics for both modes, that is for both depletion and enhancement modes.

3. Tabulate the readings in separate tabular columns as shown below. 4. Plot the drain characteristics (ID versus VDS for different values of gate voltages

VGS) of both modes (that is, depletion and enhancement) in one plot as shown below. (Take ID along the Y-axis and VDS along the X-axis in the plot)

5. From this plot of drain characteristics find the drain resistance D

DS

dI

Vr

∆

∆= ,

which is shown in Fig. 2a. 6. Similarly plot the transconductance characteristics of both modes in one plot,

with ID along the Y-axis and VGS along the X-axis in the graph for one value of VDS, say VDS = 5V.

7. From this plot find the mutual conductance or transconductance GS

Dm

V

Ig

∆

∆=

(Fig. 2b).

8. Lastly find the amplification factor, md gr •=µ




Procedure for finding the Transconcuctance Characteristics in

both modes:

1. Switch on the power supplies, with both V2 and V1 at zero voltage. 2. Initially set V1 =VGS = 0V. Now set V2 = VDS = 5V (say). Vary the power supply

V1 i.e., VGS and note down the corresponding current ID (in mA) (Simultaneously note down the VGS value from the voltmeter connected at the gate terminal).

3. Repeat the above procedure for a different value of VDS, say 10V.

Note: In the above procedure VDS (i.e., the power supply V2) is kept constant and the

power supply V1 (=VGS) is varied.

Drain Characteristics :

1. Initially set V1 = VGS =3.5V (say), slowly vary V2 and note down the corresponding current ID. Simultaneously note down in the tabular column the voltmeter reading VGS.

2. Repeat the above procedure for different values of VGS and note down the current ID for corresponding V1 = VDS.

3. Plot the graph of ID versus VDS for different values of gate voltages.

Note: In the above procedure VDS (i.e., the power supply V2) is varied and the power

supply V1 (=VGS) is kept constant.

READINGS TABULATED IN TABULAR COLUMN

Depletion mode:

(Note: In this mode VGS values are all negative and the minus sign to be appended to

the readings, though the voltmeter at the gate terminal shows the deflection in the

same way for both modes)




Drain Characteristics Transconductance Characteristics

Enhancement mode:

Drain Characteristics Transconductance Characteristics

RESULT:

Output of MOSFET Verified and tabulated




4 a. SCHMITT TRIGGER

AIM : To design and implement a Schmitt trigger circuit using op-amp for the given

UTP and LTP values.

COMPONENTS REQUIRED : IC µA 741, Resistor of 10KΩ, 90KΩ, DC regulated

power supply, Signal generator, CRO.

THEORY:

Schmitt Trigger converts an irregular shaped waveform to a square wave or

pulse. Here, the input voltage triggers the output voltage every time it exceeds certain

voltage levels called the upper threshold voltage VUTP and lower threshold voltage

VLTP. The input voltage is applied to the inverting input. Because the feedback voltage

is aiding the input voltage, the feedback is positive. A comparator using positive

feedback is usually called a Schmitt Trigger. Schmitt Trigger is used as a squaring

circuit, in digital circuitry, amplitude comparator, etc.

CIRCUIT DIAGRAM:

Fig: Circuit Diagram and actual connections of Schmitt Trigger Circuit




DESIGN 1:

From theory of Schmitt trigger circuit using op-amp, we have the trip points,

VR

RRLTPUTPV

KRKR

RRV

RR

VRLTPUTP

RR

VRLTPUTP

VRR

RR

VR

RR

VRLTP

VVRR

VR

RR

VRUTP

ref

sat

sat

ref

ref

satref

ccsatsatref

33.32

))(( have we(1)equation From

90 then ,10Let

9 yields (2)equation then 2V, LTP & 4V UTP10V,Let

-(2)----- 2

-(1)----- 2

used. isdesign following the values,&, thefind to values UTP& LTP given the Hence

&

of 90% opamp theof saturation positive theis where

1

21

12

21

21

1

21

1

21

21

2

21

1

21

2

21

1

=++

=

Ω=Ω=

====

+=−

+=+

+−

+=

=+

++

=

DESIGN 2:

Design a Schmitt Trigger for UTP=3V & LTP=-2V

UTP = [R1/(R1+R2)]* Vref + [R2/( R1+R2)] * (+Vsat)--------(1) where Vsat=12V

LTP = [R1/(R1+R2)] * Vref - [R2/(R1+R2)] * (Vsat) --------(2)

Adding Eqn.s (1) & (2), we get

UTP + LTP = [2R1/(R1+R2)] * Vref

3-2 = [2R1/(R1+R2)] * Vref

1=[2R1/(R1+R2)] * Vref---------(3)

Subtracting the (2) from (1) we get

UTP – LTP = [2R2/(R1+R2)] * Vsat

3-(-2) = [2R2/(R1+R2)] * Vsat

5 / 2 = [R2/(R1+R2)] * Vsat-------------(4)

From Eqn.(4)

5 / (2* Vsat) = R2/(R1+R2) [Vsat=12V]

5 / (2*12 ) = R2/(R1+R2)

0.2 = R2/(R1+R2)

R2(4.8) = R1+R2




∴∴∴∴R1= R2(3.8)

Let R2 = 1 kΩΩΩΩ ∴∴∴∴R1 = 3.8kΩΩΩΩ

Select R1 = 3.9kΩΩΩΩ

From Eqn.(3)

1 /2 = [R1/(R1+R2)] * Vref

0.5 = [(3.8 xR2)/(4.8 xR2)] Vref

0.5 = 0.79Vref

Vref = 0.63V

PROCEDURE :

1. Before doing the connections, check all the components using multimeter. 2. Make the connection as shown in circuit diagram. 3. Using a signal generator apply the sinusoidal input waveform of peak-to-peak

amplitude of 10V, frequency 1kHz. 4. Keep the CRO in dual mode; apply input (Vin) signal to the channel 1 and

observe the output (Vo) on channel 2 which is as shown in the waveform below. Note the amplitude levels from the waveforms.

5. Now keep CRO in X-Y mode and observe the hysteresis curve.

Waveforms:

CRO in DUAL mode




CRO in X-Y mode showing the Hysteresis curve

RESULT:

1 Practical value of UTP =……………Volts 2 Practical value of LTP =…………….Volts 3 Practical value of Hysteresis=………..Volts




Dept of CSE/ISE, DBIT

5a. OP-AMP AS A RELAXATION OSCILLATOR

AIM : To design and implement a rectangular waveform generator (op-amp relaxation

oscillator) for a given frequency.

COMPONENTS REQUIRED:

Op-amp µA 741, Resistor of 1KΩ, 10KΩ, 20 kΩ Potentiometer, Capacitor of 0.1

µF, Regulated DC power supply, CRO

THEORY:

Op-Amp Relaxation Oscillator is a simple Square wave generator which is also

called as a Free running oscillator or Astable multivibrator or Relaxation oscillator. In

this figure the op-amp operates in the saturation region. Here, a fraction (R2/(R1+R2))

of output is fed back to the noninverting input terminal. Thus reference voltage is

(R2/(R1+R2)) Vo. And may take values as +(R2/(R1+R2)) Vsat or - (R2/(R1+R2)) Vsat.

The output is also fed back to the inverting input terminal after integrating by means

of a low-pass RC combination. Thus whenever the voltage at inverting input terminal

just exceeds reference voltage, switching takes place resulting in a square wave

output.




CIRCUIT DIAGRAM:

Fig: Circuit Diagram & actual connections

Values

C=0.1μF


Electronic Circuits & Logic Design Lab 3 rd –Semester 06CSE / 06ISE38

DESIGN :

The period of the output rectangular wave is

given as

−

+=

ββ

1

1ln2RCT -------(1)

Where, 21

1

RR

R

+=β is the feedback fraction

If R1 = R2, then from equation (1) we have T = 2RC ln(3)

Another example, if R2=1.16 R1, then T = 2RC ----------(2)

Example: Design for a frequency of 1kHz (implies msf

T 11010

11 3

3==== −

)

Use R2=1.16 R1, for equation (2) to be applied.

Let R1 = 10kΩ, then R2 = 11.6kΩ (use 20kΩ potentiometer as shown in circuit

figure)

Choose next a value of C and then calculate value of R from equation (2).

Let C=0.1µF (i.e., 10-7), then Ω=×

==−

−

KC

TR 5

102

10

2 7

3

The voltage across the capacitor has a peak voltage of satc VRR

RV

21

1

+=

PROCEDURE :

1. Before making the connections check all the components using multimeter.

2. Make the connections as shown in figure and switch on the power supply. 3. Observe the voltage waveform across the capacitor on CRO. 4. Also observe the output waveform on CRO. Measure its amplitude and

frequency.




Dept of CSE/ISE, DBIT DEEPA YOGISH

WAVEFORMS

RESULT:

A rectangular wave generator has been designed and verified for a given

frequency.

The frequency of the oscillations = ___ Hz.



6. ASTABLE MULTIVIBRATOR USING 555 TIMER

AIM : To design and implement an astable multivibrator using 555 Timer for a

given frequency and duty cycle.

COMPONENTS REQUIRED: 555 Timer IC, Resistors of 3.3KΩ, 6.8KΩ, Capacitors

of 0.1 µF, 0.01 µF, Regulated power supply, CRO

THEORY:

Multivibrator is a form of oscillator, which has a non-sinusoidal output. The

output waveform is rectangular. The multivibrators are classified as: Astable or

free running multivibrator: It alternates automatically between two states (low and

high for a rectangular output) and remains in each state for a time dependent

upon the circuit constants. It is just an oscillator as it requires no external pulse

for its operation. Monostable or one shot multivibrator: It has one stable state and

one quasi stable. The application of an input pulse triggers the circuit time

constants. After a period of time determined by the time constant, the circuit

returns to its initial stable state. The process is repeated upon the application of

each trigger pulse. Bistable Multivibrators: It has both stable states. It requires the

application of an external triggering pulse to change the output from one state to

other. After the output has changed its state, it remains in that state until the

application of next trigger pulse. Flip flop is an example.

DESIGN :

Given frequency (f) = 1KHz and duty cycle = 60% (=0.6)

The time period T =1/f = 1ms = tH + tL

Where tH is the time the output is high and tL is the time the output is low.



From the theory of astable multivibrator using 555 Timer(refer Malvino), we have

tH = 0.693 RB C ------(1)

tL = 0.693 (RA + RB)C ------(2)

T = tH + tL = 0.693 (RA +2 RB) C

Duty cycle = tH / T = 0.6. Hence tH = 0.6T = 0.6ms and tL = T – tH = 0.4ms.

Let C=0.1µF and substituting in the above equations,

RB = 5.8KΩ (from equation 1) and RA = 2.9KΩ (from equation 2 & RB

values).

The Vcc determines the upper and lower threshold voltages (observed from the

capacitor voltage waveform) as CCLTCCUT VVVV3

1&

3

2== .

Note: The duty cycle determined by RA & RB can vary only between 50 & 100%. If

RA is much smaller than RB, the duty cycle approaches 50%.

Example 2: frequency = 1kHz and duty cycle =75%, RA = 7.2kΩ & RB =3.6kΩ,

choose RA = 6.8kΩ and RB = 3.3kΩ.



CIRCUIT DIAGRAM:

Circuit Diagram and actual connections

PROCEDURE:

1. Before making the connections, check the components using multimeter. 2. Make the connections as shown in figure and switch on the power supply. 3. Observe the capacitor voltage waveform at 6th pin of 555 timer on CRO. 4. Observe the output waveform at 3rd pin of 555 timer on CRO (shown

below). 5. Note down the amplitude levels, time period and hence calculate duty

cycle.



WAVEFORMS

Waveform:

s & Logic Design Lab 3 rd –Semester 06CSE / 06ISE38

Vo

Ton

Vcc

2/3Vcc

1/3Vcc

0 T

t

06CSE / 06ISE38

on

0 TOFF




RESULT:

The frequency of the oscillations = ……………Hz. (THEORETICAL)

=……………Hz (PRACTICAL)



PSPICE INTRODUCTION

SPICE is an analog circuit simulator that was developed at the University of

California at Berkeley.PSPICE is one of the many commercial SPICE derivatives,

and has been developed by Microsim Corporation.

SPICE stands for Simulation Program with Integrated Circuit Emphasis.PSPICE

helps the user simulate the circuit design graphically on the computer before

building a physical circuit. Hence, the designer can make any necessary changes

on the prototype without modifying any

circuits and verify the results by simulating the circuit by changing the different

parameters.

1. Double click the capture lite edition icon a Pspice window will be apper Creative a new project bellow.


PSPICE INTRODUCTION



and has been developed by Microsim Corporation.

Simulation Program with Integrated Circuit Emphasis.PSPICE



on the prototype without modifying any hardware. PSPICE is used to draw the


Or-CAD-Pspice-Procedure

Double click the capture lite edition icon a Pspice window will be apper Creative a new project from file manu in the main manu as shown in the fig

06CSE / 06ISE38



Simulation Program with Integrated Circuit Emphasis.PSPICE



hardware. PSPICE is used to draw the


Double click the capture lite edition icon a Pspice window will be apper from file manu in the main manu as shown in the fig




2. Enter your project name & select Analog or Mixed A/D. Select the location

which you want save the project by browsing & OK.

2. Select

blank

then click



Enter your project name & select Analog or Mixed A/D. Select the location

which you want save the project by browsing & OK.

06CSE / 06ISE38

Enter your project name & select Analog or Mixed A/D. Select the location

create a

project and

OK.



Part –A (Simulation)

1 (b) To build and simulate positive clipper, double-anded clipper and positive

clamper using diode with the help of Pspice simulation package

POSITIVE CLIPPER (SERIES)

To design circuit diagram:

Select → Place part :

1 Source → Vsin, set the values (Voff =0,Vampl = 5V,Freq = 1K) Source → Vdc(2V)

2 Eval → D1N4002 3 Analog_p → r (10K)

Part :Ground → gnd (0)

Place the voltage droppers



To simulate:

1 Create new simulation file 2 Click Pspice → new simulation profile → (filename…………….create ) →

simulation settings → Analysis (time –domain(Transient).

Procedure

1. Double click the place part icon in the tool bar select source in library, in the

2. Part type vsin and then click OK to select.

D1

D1N4002

V1

2

R110k

V3

FREQ = 1kVAMPL = 5VOFF = 0

V

0

V

SERIES CLIPPER



3. Double click VOFF, VAMP,& FREQ and enter the values shown in the circuit.

4. Similarly select all other components shown in the circuit

Select place part

Source Vdc

Eval D1N4002

Anolog_p r

Part: ground gnd(0) from 0/Source

5. Place the Voltage marker/ probe.

6. To simulate:

a. Create new simulation file, click Pspice select new simulation profile, a

new window will appears. Type the name & click create.

b. A new window called simulation settings

you are given will appears. Select Time domain in Analysis type,


Double click VOFF, VAMP,& FREQ and enter the values shown in the circuit.

Similarly select all other components shown in the circuit

place part

D1N4002

gnd(0) from 0/Source

Place the Voltage marker/ probe.

Create new simulation file, click Pspice select new simulation profile, a

new window will appears. Type the name & click create.

b. A new window called simulation settings-with simulation name which

are given will appears. Select Time domain in Analysis type,

06CSE / 06ISE38

Double click VOFF, VAMP,& FREQ and enter the values shown in the circuit.

Create new simulation file, click Pspice select new simulation profile, a

with simulation name which

are given will appears. Select Time domain in Analysis type,



enter 5ms in Run to time, enter 0 in start saving data after & enter 0.01ms

in Maximum step size, then click apply &



Maximum step size, then click apply & then OK.

06CSE / 06ISE38




6. 7 A Simulation waveform after simulation you will get as shown below



From the waveform calculate the value of the out put voltage at which

the input voltage is clipped out which should be equal to the design

value. The output voltage is calculated by using toggle Cursor & mark

the value of the o/p voltage by using the tool called Mark label.

Type of analysis: TIME DOMAIN (TRANSIENT)

Run to time: 5msec

step size:0.01msec




output voltage is calculated by using toggle Cursor & mark


TIME DOMAIN (TRANSIENT)

06CSE / 06ISE38



output voltage is calculated by using toggle Cursor & mark




Positive clipper (Shunt/Parallel) :



1 Source → Vsin, set the values (Voff =0,Vampl = 5V,Freq = 1K) Source → Vdc(2V)

2 Eval → D1N4002 3 Analog_p → r (10K)



D2

D1N4002

V

V5

1.5

SHUNT CLIPPING

0

V

V4

FREQ = 1kVAMPL = 5VOFF = 0

R4

10k



Input and output waveforms:


Run to time: 5msec

step size:0.01msec




06CSE / 06ISE38

For Evaluation Only.Copyright (c) by Foxit Software Company, 2004Edited by Foxit PDF Editor



Double-ended clipper:

D6

D1N4002

V

V12

3V11

3

R5

10k

DOUBLE ENDED CLIPPER

V2

FREQ = 1KHZVAMPL = 5VVOFF = 0

D5

D1N4002V

0

For Evaluation Only.Copyright (c) by Foxit Software Company, 2004Edited by Foxit PDF Editor






Run to time: 5msec

step size:0.01msec

POSITIVE CLAMPER [Without Reference Voltage]






POSITIVE CLAMPER [Without Reference Voltage]

06CSE / 06ISE38

Created by Neevia Document Converter trial version http://www.neevia.com





Source → Vpulse,set the values (V1=2.5V,V2=-2.5V,TD=0.01ms,TR=0.01µs,

TR=0.01 µs,TF=0.1 µs,pw=0.5 µs,PER=1ms)

1 Eval → D1N4002 2 Analog → r (200K) 3 Analog → c(0.1µF)



D7

D1N4002

V1TD = 0.01ms

TF = 0.01usPW = 0.5msPER = 1ms

V1 = 2.5v

TR = 0.01us

V2 = -2.5vV

C1

0.1uF

R6

200K

V

0

WITHOUT

REFERENCE

VOLTAGE







Run to time: 5msec

step size:0.01msec





POSITIVE CLAMPER [With Reference Voltage]

0

VV2

TD = 0.01ms

TF = 0.01usPW = 0.5mPER = 1ms

V1 = 2.5v

TR = 0.01us

V2 = -2.5v R7

200K

C2

0.1uF

D8D1N4002

V

WITH

REFERENCE

VOLTAGE

V17

1v







Run to time: 5msec

step size:0.01msec





2(b) To build the CE amplifier ciruit using a simulation package and determine

the voltage gain for two different values of supply voltage and for two different

values of emitter resistance

Procedure:

1. Double click the place part icon in the tool bar select source in library, in

the

Part type Vac then click OK to select.

2. Double click Vac & 0Vdc and enter the values shown in the circuit.

R7

220

0

C7

100uF

V

CE AMPLIFIER

R2

1k

C5

cv al

R6

3.9K

R5

16k

R4

820Q2

Q2N2222

0

C6

0.47uF

VV150mv

0Vdc

PARAMETERS:cv al = 1

V4

10v





3. Similarly select R in analog source and repeatedly place

resistor

& 1 load resistor; set resistor values and change its names.

4. Similarly all other components shown in the circuit.

To Simulate:

Create new simulation file, click Pspice select new simulation profile, a new

window will appears. Type the name & click create.

A new window called simulation settings

given will appears. Select AC sweep in Analysis

start frequency 10hz, end frequency 10Meg & Points per decad 40.Click apply &

then OK.




3. Similarly select R in analog source and repeatedly place

& 1 load resistor; set resistor values and change its names.

4. Similarly all other components shown in the circuit.


window will appears. Type the name & click create.

new window called simulation settings-with simulation name which you are

given will appears. Select AC sweep in Analysis type, Sweep type logarithmic,



06CSE / 06ISE38

3. Similarly select R in analog source and repeatedly place 4 biasing


with simulation name which you are

type, Sweep type logarithmic,






From the waveform calculate the maximum voltage and then the voltage

gain of the amplifier by ( Vout / Vin) .

Repeat the simulation with two different values of Vdc & RE & calculate its

value of voltage gain.

Type of analysis: Ac Sweep

Sweep type: logarithmic

Start frequency:10Hz

End frequency:10meg

Points per decade:40

3(b) To implement a CMOS inverter using a simulation package and verify its

truth table.

V1

5v

CMOS

INVERTER0

0

V

M2

MbreakN

M1

MbreakP

R2

100k

V

V2

TD = 0.01ns

TF = 1nsPW = 20usPER = 40us

V1 = 5v

TR = 1ns

V2 = 0v





Procedure:

1. From the place part select all the components as shown in the circuit diagram. Edit the values of the components & sources.

2. After simulation select Add to p

3. Add trace from trace Menu & select the i/p waveform V(Vs:+)

4. The I/P waveform with given period & amplitude will be displayed.



From the place part select all the components as shown in the circuit diagram. Edit the values of the components & sources.

After simulation select Add to plot window in plot Main menu



06CSE / 06ISE38

From the place part select all the components as shown in the circuit diagram. Edit the values of the components & sources.

lot window in plot Main menu







1. Similarly the O/P waveform along with I/P waveform will be displayed

By selecting the ADD Trace to V (RL: 1). from the simulation waveform Calculate & mark the O/P voltage using toggle Cursor & Mark label.



Similarly the O/P waveform along with I/P waveform will be

By selecting the ADD Trace to V (RL: 1). from the simulation waveform Calculate & mark the O/P voltage using toggle Cursor &

06CSE / 06ISE38

Similarly the O/P waveform along with I/P waveform will be

By selecting the ADD Trace to V (RL: 1). from the simulation waveform Calculate & mark the O/P voltage using toggle Cursor &







06CSE / 06ISE38





Input and output waveforms


Run to time: 100usec

Step size:0.1usec

4(b) To implement a Schmitt trigger using op Amp Using a simulation package

for two sets of UTP and LTP values







SCHMITT TRIGGER





V1

10v

V2

10v

V

V43.3v

0

V3

FREQ = 50hzVAMPL = 10vVOFF = 0v

0

0

R210k

U1

uA741

3

2

74

6

1

5+

-

V+

V-

OUT

OS1

OS2

R1

90k

0

06CSE / 06ISE38

V





Run to time: 40msec

step size:0.1msec


Run to time: 40msec

step size:0.1msec




06CSE / 06ISE38





5(b) To implement a rectangular waveform generator (Op-Amp relaxation

Oscillator) using a simulation package and observe the change in

frequency when all resistors values are doubled.

V1

12v

C1

.1uf

U1

uA741

3

27

4

6

1

5+

-V+

V-

OUT

OS1

OS2

R3

10k

V

0

V2

12v

RELAXATION OSCILLATOR

0R1

1k

R2

10k

0

0

V









06CSE / 06ISE38





TYPE OF ANALYSIS: TIME DOMAIN


RUN TO TIME: 4ms

MAXIMUM STEP SIZE: 0.01ms





MAXIMUM STEP SIZE: 0.01ms

06CSE / 06ISE38





6 To design and implement as astable multivibrator ciruit using 555 timer for given frequency and duty cycle.

C2

0.01uf

0

X1

555D

1

234

567

8GND

TRIGGEROUTPUTRESET

CONTROLTHRESHOLDDISCHARGE

VCC

0 0

C1

0.1u

R3

10meg

V110

ASTABLE MULTIVIBRATOR USING 555 TIMER

V

R2

5.8k

R1

2.9k

V

0







Run to time: 5msec

Step size:0.01msec





7 To implement a +5V regulated power supply using Full wave rectifier and

Zener diode in simulation package. Find the output ripple for different values of

load current.

REGULATED POWER SUPPLY

V

R1

220

V

D2

D1N4002

C1

47uf

D5D1N4002

0

D4

D1N4002

D1

D1N750

R2

1K

V1

FREQ = 60HzVAMPL = 10VVOFF = 0V

D3D1N4002






TYPE OF ANALYSIS : TIME DOMAIN

RUN TO TIME : 100ms

MAXIMUM STEP SIZE : 0.1ms




TYPE OF ANALYSIS : TIME DOMAIN

RUN TO TIME : 100ms

MAXIMUM STEP SIZE : 0.1ms

06CSE / 06ISE38





LOGIC DESIGN LABORATORY

1 a) Given a four variable expression, simplify using Entered Variable Map

(EVM)

And realize the simplified logic using 8:1 MUX.

b) Write a verilog/VHDL code for 8:1 MUX. Simulate and verify its working.

a) E.g., Simplify the function using MEV technique

f(a,b,c,d)=∑m(2,3,4,5,13,15)+dc(8,9,10,11)

Decimal LSB f MEV map entry

00

1

12

9

24

5

36

7

48

9

510

11

612

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

0

0

1

1

1

1

0

0

X

X

X

X

0

1

0------Do

1------D1

1-----D2

0-----D3

X-----D4

X-----D5

d----D6





13

714

15

1110

1111

0

1

d----D7

Theory:

Map Entered Variable Method:

Rules for entering values in a MEV K Map:

Rule

No.

MEV f Entry in

MEV map

Comments





1 0

1

0

0

0

If function equals 0 for both values of

MEV,enter 0 in appropriate cell of MEV Map

2 0

1

1

1

1

If function equals 1 for both values of

MEV,enter 1 in appropriate cell of MEV Map

3 0

1

0

1

MEV If function equals MEV enter MEV

4 0

1

1

0

------

MEV

If function equals complement of MEV enter

complement of MEV

5 0

1

X

X

X

If function equals don’t care for both values of

MEV enter X

6 0

1

X

0

0 If f=X for MEV=0 and f=0 MEV=1, enter 0.

7 0

1

0

X

0 If f=0 for MEV=0 and f=X MEV=1, enter 0.

8 0

1

1

X

1 If f=1 for MEV=0 and f=X MEV=1, enter 1.

9 0

1

X

1

1 If f=X for MEV=0 and f=1 MEV=1, enter 1.





Circuit Diagram:

Procedure:

1) Verify all components and patch chords whether they are in good condition or not.

2) Make connection as shown in the circuit diagram. 3) Give supply to the trainer kit. 4) Provide input data to Circuit via Swiches. 5) Verify truth table Sequence and observe outputs.





2) a) Realise a full adder using 3

b)Write the verilog /VHDL code for full adder . Simulate & gates verify its

working .

Ics Used: 74138IC and 7420

Pin Diagram of ICs used:

7420

74138



2) a) Realise a full adder using 3-8 decoder IC and 4 input NAND .


Ics Used: 74138IC and 7420

06CSE / 06ISE38






Theory:

The simplest Binary adder is a half adder. It has 2 inputs and 2 output bits. One is

the sum and the other is carry.

A half adder has no provision to add carry of lower order bits when binary

numbers are added. When two input bits and a carry are to be added, the number

of input bits become 3 and input combination increases to 8. For this a full adder

is used. Like half adder, it has 2 outputs. One is sum and the other is carry. New

carry generated is denoted as Cn and carry generated from addition of previous

lower order bits is denoted as Cn-1

A B C S C





S=∑m(1,2,4,7)

C=∑m(3,5,6,7)

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

0

1

0

0

0

1

0

1

1

1





Circuit Diagram:

Procedure:



3) a)Realize a J-K Master/Slave FF using NAND gates and verify its truth table.

b) Write a verilog/VHDL code for DFF with positive edge triggering. Simulate

and verify

its working.

ICs used: 7400, 7410, 7420

Pin Details of the ICs:

7400





7410



06CSE / 06ISE38





7420

Theory:

The circuit below shows the solution. To the RS flip

added two new connections from the Q and Q' outputs back to the

original input gates. Remember that a NAND gate may have any number

of inputs, so this causes no trouble. To show that we have

change the designations of the logic inputs and of the flip

inputs are now designated J (instead of S) and K (instead of R). The

entire circuit is known as a



The circuit below shows the solution. To the RS flip-flop we have



of inputs, so this causes no trouble. To show that we have done this, we

change the designations of the logic inputs and of the flip-flop itself. The


entire circuit is known as a JK flip-flop.

06CSE / 06ISE38

flop we have



done this, we

flop itself. The






In most ways, the JK flip

and Q' outputs will only change state on the falling edge of the CLK

signal, and the J and K inputs will control the future output state pretty

much as before. However, there are some

Since one of the two logic inputs is always disabled according to the

output state of the overall flip

back and forth while the CLK input is at logic 1. Instead, the enabled

input can change the state of the master latch

will not change again. This was not true of the RS flip

If both the J and K inputs are held at logic 1 and the CLK signal

continues to change, the Q and Q' outputs will simply change state

each falling edge of the CLK signal. (The master latch circuit will change

state with each rising edge of CLK.) We can use this characteristic to

advantage in a number of ways. A flip

this way is typically designate

input is in fact the CLK input for other types of flip

The JK flip-flop must

triggered JK latch circuit will oscillate rapidly if all three inputs are held

at logic 1. This is not very useful. For the same reason, the T flip



In most ways, the JK flip-flop behaves just like the RS flip-flop. The Q



much as before. However, there are some important differences.


output state of the overall flip-flop, the master latch cannot change state


ge the state of the master latch once, after which this latch

will not change again. This was not true of the RS flip-flop.


continues to change, the Q and Q' outputs will simply change state


edge of CLK.) We can use this characteristic to

advantage in a number of ways. A flip-flop built specifically to operate

this way is typically designated as a T (for Toggle) flip-flop. The lone T

input is in fact the CLK input for other types of flip-flops.

must be edge triggered in this manner. Any level


gic 1. This is not very useful. For the same reason, the T flip-flop

06CSE / 06ISE38

flop. The Q




flop, the master latch cannot change state


, after which this latch


continues to change, the Q and Q' outputs will simply change state with


edge of CLK.) We can use this characteristic to

flop built specifically to operate

flop. The lone T

be edge triggered in this manner. Any level-


flop





must also be edge triggered. For both types, this is the only way to

ensure that the flip-flop will change state only once on any given clock

pulse.

Because the behavior of the JK flip-flop is completely predictable

under all conditions, this is the preferred type of flip-flop for most logic

circuit designs. The RS flip-flop is only used in applications where it can

be guaranteed that both R and S cannot be logic 1 at the same time.

At the same time, there are some additional useful configurations of

both latches and flip-flops. In the next pages, we will look first at the

major configurations and note their properties. Then we will see how

multiple flip-flops or latches can be combined to perform useful

functions and operations.

Master Slave Flip Flop:

The control inputs to a clocked flip flop will be making a transition at

approximately the same times as triggering edge of the clock input occurs. This

can lead to unpredictable triggering.

A JK master flip flop is positive edge triggered, where as slave is negative edge

triggered. Therefore master first responds to J and K inputs and then slave. If J=0

and K=1, master resets on arrival of positive clock edge. High output of the master

drives the K input of the slave. For the trailing edge of the clock pulse the slave is

forced to reset. If both the inputs are high, it changes the state or toggles on the

arrival of thepositive clock edge and the slave toggles on the negative clock edge.

The slave does exactly what the master does.





Function Table:

Clk J K Q ---

Q

comment

0

0

1

1

0

1

0

1

Q0

0

1

Q0

----

Q0

1

0

Q0

No change

Reset

Set

toggle





Circuit Diagram:

Procedure:


2) Make connection as shown in the circuit diagram. 3) Give supply to the trainer kit. 4) Provide input data to Circuit via Swiches.





5) Verify truth table Sequence and observe outputs. 4)a) Design and implement a mod n (a<8)synchronous up counter using JK FF.

b) Write the verilog/VHDL code for mod 8 up counter simulate and verify its

working.

ICs used: 7476,7408.

Pin diagram of 7476

7408





Theory:

The ripple counter requires a finite amount of time for each flip flop to change

state. This problem can be solved by using a synchronous parallel counter where

every flip flop is triggered in synchronism with the clock, and all the output which

are scheduled to change do so simultaneously.

The counter progresses counting upwards in a natural binary sequence from

count 000 to count 100 advancing count with every negative clock transition and

get back to 000 after this cycle.

Exitation Table:

Qn Qn+1 J K





Transition Table:

Present State

Nert State Jc Kc Jb Kb Ja Ka

Qc Qb Qa

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Qc+1 Qb+1 Qa+1

0 0 1

0 1 0

0 1 1

1 0 0

0 0 0

x x x

x x x

x x x

0 x

0 x

0 x

1 x

x 1

x x

x x

x x

0 x

1 x

x 0

x 1

0 x

x x

x x

x x

1 x

x 1

1 x

x 1

0 x

x x

x x

x x

0

0

1

1

0

1

0

1

0

1

X

X

X

X

1

0





K Map Simplification:

Circuit Diagram:





Procedure:



5. (a) Design and Implement a Ring Counter using 4 bit Shift Register.





ICs Used: 7495

Pin Diagram of ICs:

7495

Theory:

Ring Counter is a basic register with direct feedback such that contents of the

register simply circulate around the register when the clock is running. Here last

output Qd in a shift register is connected back to the serial input.

Function Table:

Clk Qa Qb Qc Qd





0

1

2

3

4

1

0

0

1

1

0

1

0

0

0

0

0

1

0

0

0

0

0

1

0

Circuit Diagram:





Procedure:







6) Design and implement asynchronous counter using decade counter IC to count

up from 0 to n (n≤9).

Asynchronous counter using decade counter IC to count up from o to n

(n≤9).\

ICs used: 7490

Pin Diagram of 7490

Theory:





Asynchronous counter is a counter in which the clock signal is connected to the

clock input of only first stage flip flop. The clock input of the second stage flip flop

is triggered by the output of the first stage flip flop and so on. This introduces an

inherent propagation delay time through a flip flop. A transition of input clock

pulse and a transition of the output of a flip flop can never occur exactly at the

same time. Therefore, the two flip flops are never simultaneously triggered, which

results in asynchronous counter operation.

Circuit Diagram:

Function Table:

Clock Qa Qb Qc

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1





4 1 0 0

5 1 0 1

6 1 1 0

8 1 1 1

Procedure:







7) Design a 4-bit R-2R ladder D/A converter using Op-Amp. Determine its accuracy

and resolution.

Aim: To study the operation of 4-bit DAC using R-2R ladder network.

Components required:

Resistors, DMM, OP-741, connecting wires, IC trainer kit.

Circuit diagram:

Vref=5V

V0=(8D3+4D2+2D1+2D0)Vref/24

Smallest increment or change in the output voltage=VR/24*(2R/3R)

Accuracy=((Theorical Value-Practiacal Value)/Practical Value)*100





Tabular column:

Procedure:

1) Make connections as shown in the circuit diagram 2) In different digital inputs measure the analog output voltage using

multimeter. 3) Tabulate the results compare the theoretical output values with the

practical ones.





Experiments on VHDL/VERILOG

Procedure to edit VHDL Code & Run

It is one of most popular software tool used to synthesize VHDL code. This

tool

Includes many steps. To make user feel comfortable with the tool the steps

are

given below:-

• Double click on Project navigator. (Assumed icon is present on desktop).

• Select NEW PROJECT in FILE MENU. Enter following details as per your convenience

Project name : sample

Project location : C:\example

Top level module : HDL

• In NEW PROJECT dropdown Dialog box, Choose your appropriate device specification. Example is given below: Device family : Spartan2

Device : xc2s200

Package : PQ208

TOP Level Module : HDL

Synthesis Tool : XST

Simulation : Modelsim / others

Generate sim lang : VHDL

• In source window right click on specification, select new source Enter the following details





Entity: sample

Architecture : Behavioral

Enter the input and output port and modes.

This will create sample.VHD source file. Click Next and finish the

initial Project preparation.

• Double click on synthesis. If error occurs edit and correct VHDL code.

• Double click on Lunch modelsim (or any equivalent simulator if you are using) for functional simulation of your design.

• Right click on sample.VHD in source window, select new source Select source : Implementation constraints file.

File name : sample

This will create sample. UCF constraints file.

• Double click on Edit constraint (Text) in process window. Edit and enter pin constraints with syntax:

NET “NETNAME” LOC = “PIN NAME”

• Double click on Implement, which will carry out translate, mapping, place and route of your design. Also generate program file by double clicking on it, intern which will create .bit file.

• Connect JTAG cable between your kit and parallel pot of your computer.

• Double click on configure device and select mode in which you want to configure your device. For ex: select slave serial mode in configuration window and finish your configuration.

• Right click on device and select ‘program’. Verify your design giving appropriate inputs and check for the output.

• Also verify the actual working of the circuit using pattern generator

& logic analyzer.

1. FULL ADDER

FULL

ADDER

S

Cout

X

Y

Z Created by Neevia Document Converter trial version http://www.neevia.com




Truth Table

INPUTS OUTPUTS

X Y Z SUM CARRY

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1





1 1 0 0 1

1 1 1 1 1

Expession: Sum(S)=X ⊕⊕⊕⊕ Y ⊕⊕⊕⊕ Z

Carry(Cout) = XY +YZ + ZX

-- VHDL code for Full adder using data flow

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY fa IS

Port (X, Y, Z : in STD_LOGIC;

Cout, S : out STD_LOGIC);

End fa;

ARCHITECTURE df OF fa IS

Begin

Cout<= ((X XOR Y) AND Z) OR (X AND Y);

S<= (X XOR Y) XOR Z;

End df;





//Verilog Code for Full adder using data flow

module fa (cout,s,x,y,z);

input x,y,z;

output cout,s;

assign s=x^y^z;

assign cout=x&y!y&z!x&z;

endmodule

Full Adder Simulation Results

Sum Carry





2. 8 TO 1 MULTIPLEXER

TruthTable

INPUTS OUTPUTS

SEL (2) SEL (1) SEL (0) Zout

0 0 0 I(0)

0 0 1 I(1)

0 1 0 I(2)

0 1 1 I(3)

1 0 0 I(4)

1 0 1 I(5)

0 1 1 I(6)

1 1 1 I(7)

-- VHDL code for 8 to 1 mux (Behavioral modeling).

MULTIPLEXER

8 TO 1 8

Zout

I

SEL

3





library IEEE;


entity mux1 is

Port ( I : in std_logic_vector(7 down to 0);

sel : in std_logic_vector(2 downto 0);

zout : out std_logic);

end mux1;

architecture Behavioral of mux1 is

begin

zout<= I(0) when sel="000" else

I(1) when sel="001" else






I(7);

end Behavioral;





//Verilog code for 8 to 1 mux (Behavioral modeling).

module mux1(i0,i1,i2,i3,i4,i5,i6,i7,s2,s1,s0,y);

input i0,i1,i2,i3,i4,i5,i6,i7,s2,s1,s0;

output y;

reg y;

always @ (i0 or i1 or i2 or i3 or i4 or i5 or i6 or i7 or s2 or s1 or s0)

case (s2,s1,s0)

3’b000:y=i0;

3’b001:y=i1;

3’b010:y=i2;

3’b011:y=i3;

3’b100:y=i4;

3’b101:y=i5;

3’b110:y=i6;

3’b111:y=i7;

endcase

endmodule

8:1 Mux Simulation Results





3. D Flip Flop

output





--VHDL code for D Flip Flop Counter.

library IEEE;


entity dflipflop is

Port ( D,Clk : in std_logic;

Q : inout std_logic;

Qbar : out std_logic);

end dflipflop;

architecture Behavioral of dflipflop is

begin

process(clk)

begin

if rising_edge(clk) then

Q<= D;

end if;

end process;

Qbar<= not Q;

end Behavioral;

--Verilog code for D Flip Flop Counter.





module dflipflop(clk,reset,d,q);

input clk,reset,d;

output q;

reg q;

always @ (posedge clk or negedge reset)

if(~reset)

q=1’b0;

else

q=d;

endmodule





D-ff Simulation Results





4. Mod 8 Counter

Truth Table

VHDL code for Mod-8 Counter.

library IEEE;


entity mod_8 is

Port ( rst,clk,en: in std_logic;

q : inout std_logic_vector(3 downto 0));

end mod_8;

architecture Behavioral of mod_8 is

begin

process(clk,rst) is

begin





if rst='1' then q<="0000";

elsif rising_edge(clk) then

if en='1' then

Q<=Q+1;

end if;

if Q="0111" then

Q<= "0000";

end if;

end if;

end process;

end Behavioral;

//Verilog code for Mod-8 Counter.

module mod_8 (clk,reset,q);

input clk,reset;

output [2:0] q;

reg [2:0]q;

always @ (negedge clk,negedge reset)

if (~reset)





q=3’b000;

else

q=q+1’b1;

endmodule

Mod 8 Counter Simulation Results





Output

5. Johnson counter.

Truth Table

VHDL code for Johnson counter.

library IEEE;


use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity jc is

Port ( clk,e,rst : in std_logic;





q : inout std_logic_vector(3 downto 0));

end jc;

architecture Behavioral of jc is

begin

Process(clk,rst)

begin

if rst='1' then q<="0001";

elsif rising_edge (clk) then

if e='1' then

q<=(not q(0))& Q(3 downto 1);

end if;

end if;

end process;

end Behavioral;

Verilog code for Johnson counter.

module jc (clk,reset,q);

input clk,reset;

output [3:0] q;

reg [3:0]q;





always @ (negedge clk,negedge reset)

if (~reset)

q=4’b0000;

else

begin

q[0]<=~q[3];

q[1]<=q[0];

q[2]<= q[1];

q[3]<=q[2];

end

endmodule

Johnson Counter Simulation Results





Output

Viva Questions

1. What is logic & Logic Design? 2. What are the differences b/w analog circuits & digital

Circuits? 3. What are the differences b/w sequential circuits &

combinational Circuits?





4. what is SOP & POS expression? 5. How do you convert SOP(POS) to Standard SOP(POS)? 6. what are minterms & Maxterms? 7. How do you simplify Boolean expression using Kmap &

Quine meclusky method? 8. what are prime implicants? 9. what are multiplexers,decoders,encoders,parity

generators&checkers, demultiplexers? 10. How do you implement Boolean expression using

Multiplexers,decoders,demultiplexers?

11. what are Programmable Logic Devices & which are the

different types of PLD’s?

12. What is Fast Adder?

13. How do you substract two numbers using 2’s

complement method?

14. What are flip flops ? what are different types of Flip flops?

15. What is Race around condition? How do you eliminate?

16. What are the applications of Flip flops?

17. What are registers & Counters ? explain their applications.

18. What is exitation table? Write exitation table for different

types

of FF’s.

19. What is the difference between Synchronous counter &

Asynchronous Counter?

20. What is the difference between Mealy & moore model?



Documents

(Common to CSE & ISE) Sub Code: 06CSL38 IA Marks: 25