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Combining Decomposition and Unfolding for STG Synthesis (application paper). Victor Khomenko 1 and Mark Schaefer 2 1 School of Computing Science, Newcastle University, UK 2 Institute of Computer Science, University of Augsburg, Germany. Asynchronous circuits. - PowerPoint PPT Presentation
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Combining Decomposition and
Unfolding for STG Synthesis(application paper)
Victor Khomenko1 and Mark Schaefer2
1School of Computing Science,Newcastle University, UK
2Institute of Computer Science, University of Augsburg, Germany
2
Asynchronous circuits The traditional synchronous (clocked) designs
lack flexibility to cope with contemporarydesign technology challenges
Asynchronous circuits – no clocks: Low power consumption and EMI Tolerant of voltage, temperature and
manufacturing process variations Modularity – no problems with the clock skew
and related subtle issues[ITRS’05]: 22% of designs will be driven by ‘handshake
clocking’ in 2013, and 40% in 2020 Hard to synthesize efficient circuits The theory is not sufficiently developed Limited tool support
3
Syntax-directed translation
Idea:
Convert the specification to a network of standard handshake components (Balsa, Tangram)
Computationally efficient Solution is guaranteed Produces highly over-encoded circuits, with
large area and low performance
4
Logic synthesis
Idea:
Synthesize the circuit by exploring the state space of the specification
Produces good circuits Solution is not guaranteed State space explosion: synthesis
based on state graphs is feasible only for small specifications (20-30 signals for BDD-based Petrify)
5
Unfoldings
Alleviate the state space explosion problem More visual than state graphs Proven efficient for model checking Can often synthesize specifications with
100-200 signals Still not enough for real-life designs!
6
DecompositionIdea:
• Decompose the control path of the specification into smaller clusters and synthesize them one-by-one
• Use syntax-directed translation for clusters on which synthesis fails
Can halve the area of the control path and improve its latency [Carmona, Cortadella DAC’06]
7
Example: VME Bus Controller
lds-d- ldtack- ldtack+
dsr- dtack+ d+
dtack- dsr+ lds+
DeviceVME Bus
Controller
lds
ldtack
d
Data Transceiver
Bus
dsrdtack
8
Initial partition
lds-d- ldtack- ldtack+
dsr- dtack+ d+
dtack- dsr+ lds+Include signal triggers
and choices:• lds: dsr, ldtack, d• d: ldtack, dsr• dtack: d
lds: dsr, ldtack, d
d: ldtack, dsr dtack: d
lds
d dtack
dsr
ldtack
9
Initial decomposition
lds-d- ldtack- ldtack+
dsr- dtack+ d+
dtack- dsr+ lds+
lds-d- ldtack- ldtack+
dsr- dtack+ d+
dtack- dsr+ lds+
lds-d- ldtack- ldtack+
dsr- dtack+ d+
dtack- dsr+ lds+
10
Irreducible CSC conflict
Transition contraction
lds-d- ldtack- ldtack+
dsr- d+
dsr+ lds+
d-
dtack+ d+
dtack-
d- ldtack- ldtack+
dsr- d+
dsr+
ldsd
d- ldtack- ldtack+
dsr- d+
dsr+ lds+Merge similar components
11
Resolving CSC conflicts
lds-d- ldtack- ldtack+
dsr- d+
dsr+ lds+
lds-
d-
ldtack-
ldtack+ dsr-d+dsr+ lds+ lds+
dsr+e1 e2 e3 e4 e5 e7
e9
e11
e10
e8
12
Resolving CSC conflicts (cont’d)
lds-d- ldtack- ldtack+
dsr- d+
dsr+ lds+csc+
csc-
13
Resulting Circuit
Device
d
Data TransceiverBus
dsr
dtacklds
ldtack
csc
14
Implementation
DESIJ
PUNF
MPSAT
Large STGs(specification)
Medium STGs unfolding-based (exact) tests
Small STGs(components)
synthesis
structural (approximate) tests
decomposition
decomposition
15
Safeness-preserving contractions
• Unfolding is more efficient for safe nets
• Decomposition can create unsafe nets
• Contractions have to preserve safeness
t t t
Example Structural condition
16
Auto-conflicts
• Auto-conflicts appear if too many signals wereremoved
• Backtracking reinserts signals which remove the auto-conflict
• Unnecessary backtracking increases thefinal components
a+ a+
17
Implicit places
• Implicit places are places the absence of tokens in which can never be the sole reason for some transition to be disabled
• Such places can be deleted without changing the behaviour of the STG
• Removing such places is essential for decomposition, because they can cause false alarms for other tests prevent contractions
• Structural test looks for a subset of implicit places (redundant places, shortcut places)
18
Experimental results
• Large trees composed of alternating levels of sequencers and parallelisers were considered
• Intractable for stand-alone MPSAT and Petrify
19
Experimental results
0
500
1000
1500
2000
2500
3000
3500
4000
4500
0 1000 2000 3000 4000 5000Signals
Tim
e[s]
20
Experimental results
• Outperforms stand-alone
MPSAT and Petrify on large STGs• Some intractable for
stand-alone MPSAT and
Petrify benchmarks were
easily synthesized• Huge STGs can be synthesized, e.g.
SeqParTree-10 with 12598 places, 8188 transitions, and 1025 inputs and 3069 outputs was synthesized in less then 70 minutes
21
Thank you!Any questions?