Combinational Logic Review

2 © tjEE 3921 – Fall 2017

Basic Logic

• Buffers

In OutIn Out

0 0

1 1

In Tri OUT

0 0 1

0 1 0

1 0 Z

1 1 Z

In Out

Tri

In OutIn Out

0 1

1 0

notA ~A A’

non-Inverting

Inverting

Tri-State

In Tri OUT

A 0 ~A

X 1 Z

3 © tjEE 3921 – Fall 2017

Basic Logic

• Simple Gates

A

BOut

A

BOut

A

BOut

A

BOut

A

BOut

A

BOut

AND/NAND

OR/NOR

XOR/XNOR

A B AND OUT

NAND OUT

0 0 0 1

0 1 0 1

1 0 0 1

1 1 1 0

A and B A nand BA ^ B (A ^ B)’A & B A & BAB A*B

A B OR OUT

NOR OUT

0 0 0 1

0 1 1 0

1 0 1 0

1 1 1 0

A or B A nor BA v B (A v B)’A | B A | BA + B

A B XOROUT

XNOR OUT

0 0 0 1

0 1 1 0

1 0 1 0

1 1 0 1

A xor B A xnor BA ⊕ B (A ⊕ B)’

4 © tjEE 3921 – Fall 2017

Basic Logic

• Switches

A BSwitch

Ctl State

0 X

1 A = B

Ctl

A B

Ctl

Ctl

Switch

Ctl State

0 X

1 A = B

In Out

Tri

Tri

Tristate

In Tri Tribar

Out

A 0 0 U

A 0 1 A’

A 1 0 Z

A 1 1 U

5 © tjEE 3921 – Fall 2017

Basic Logic

• Coder / Decoder

4 to 2

b0

b1

b2

b3

out 12 to 4

b0

b1

b2

b3

in 1

out 0 in 0

b3 b2 b1 b0out

1out

0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

In 1

In 2

b3 b2 b1 b0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

6 © tjEE 3921 – Fall 2017

Basic Logic

• Multiplexer/ Demultiplexer

s1 s0

b0

b1

b2

b3

out

s1 s0

b0

b1

b2

b3

in

s1 S0 out

0 0 b0

0 1 b1

1 0 b2

1 1 b3

s1 s0 b3 b2 b1 b0

0 0 0 0 0 in

0 1 0 0 in 0

1 0 0 in 0 0

1 1 in 0 0 0

7 © tjEE 3921 – Fall 2017

Basic Logic

• Logic Analysis

A

B

C

X

Y

Out0

8 © tjEE 3921 – Fall 2017

Basic Logic

• Logic Analysis

A

B

C

X

Y

Out

A B C X Y Out

(B+0)’ (AC)’ (AXY)’

0 0 0 1 1 1

0 0 1 1 1 1

0 1 0 0 1 1

0 1 1 0 1 1

1 0 0 1 1 0

1 0 1 1 0 1

1 1 0 0 1 1

1 1 1 0 0 1

0

9 © tjEE 3921 – Fall 2017

Basic Logic

• de Morgan’s Laws

BABA )( BABA )(

BABA )( BABA )(

AA )( AA )(

10 © tjEE 3921 – Fall 2017

Basic Logic

• de Morgan’s Laws

A

B

C

X

Y

Out0

BABA )( BABA )(

BABA )( BABA )(

AA )( AA )(

11 © tjEE 3921 – Fall 2017

Basic Logic

• de Morgan’s Laws

Out = AXY

A(B+0)(AC)

A + (B+0) + (AC)

A + B + AC

A

B

C

X

Y

Out0

BABA )( BABA )(

BABA )( BABA )(

AA )( AA )(

12 © tjEE 3921 – Fall 2017

Basic Logic

• Sum-of-Products, Product-of-Sums

Why ???

Sum-of-Products )()()( FEDCBA EFCDAB

Product-of-Sums )()()( FEDCBA ))()(( FEDCBA

13 © tjEE 3921 – Fall 2017

Basic Logic

• minterm / maxterm

• SOP: Y = A’B + AB

• POS: Y = (A + B) (A’ + B)

A B Y minterm maxterm

0 0 0 A’B’ A + B

0 1 1 A’B A + B’

1 0 0 AB’ A’ + B

1 1 1 AB A’ + B’

14 © tjEE 3921 – Fall 2017

Basic Logic

• Karnaugh Maps

1 0 0 1

0 1 0 1

1 1 0 0

1 1 0 0

A

A’

B B’

C

C’

C’

D’ D’D

A’B + BCD + AB’D’ + AC’D’

A B C D Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 1

0 1 0 1 1

0 1 1 0 1

0 1 1 1 1

1 0 0 0 1

1 0 0 1 0

1 0 1 0 1

1 0 1 1 0

1 1 0 0 1

1 1 0 1 0

1 1 1 0 0

1 1 1 1 1

15 © tjEE 3921 – Fall 2017

Basic Logic

• Delays• tpd = propagation delay

• delay from input to valid output (max delay)

• tcd = contamination delay• delay from input to first movement on output (min delay)

A

Y

Time

A Y

tpd

tcd

src: Harris & Harris

16 © tjEE 3921 – Fall 2017

Basic Logic

• Shortcuts

1

AA

0

A1

1

A0

0

AA

17 © tjEE 3921 – Fall 2017

Basic Logic

• Physical world• Voltage levels

• System/Circuit dependent

• Ideal:

3.3v System ‘1’ = 3.3v ‘0’ = 0.0v

1.8v System ‘1’ = 1.8v ‘0’ = 0.0v

1.2v System ‘1’ = 1.2v ‘0’ = 0.0v

• Real world:

3.3v System 3.3v

0.0v

2.4vVOH

0.5vVOL

0.8vVIL

2.0 vVIH

18 © tjEE 3921 – Fall 2017

Basic Logic

• Clock Systems

T (period) timeHigh Low

F (frequency) = 1/T Duty Cycle = High / T

50MHz <-> 20nS High = 10ns, Low = 10ns

25% duty cycle, 12.5Mhz

75% duty cycle, 12.5MHz

19 © tjEE 3921 – Fall 2017

Basic Logic

• Clock Systems

• 3 – phase, non-overlapping clock

ph1

ph2

ph3

20 © tjEE 3921 – Fall 2017

Combinational Logic Review

• Basic VHDL file structure

EntityDescription(External Signals)

-- File Header ------- CombinationalReview.vhdl-- Created: 7/4/2017-- By: tj-- For: EE3921--

-- FIle Overview ------- This file demonstrates some combinational logic-- constructs

-- File Details -----

-- Behavioral Architecture Definitionarchitecture behavioral of CombinationalReview is

signal e: std_logic := '0';signal f: std_logic := '0';signal g: std_logic := '0';signal t: std_logic_vector(N-1 downto 0) := (others => '0');signal u: std_logic_vector(N-1 downto 0) := (others => '0');

Begin

e <= a and b;f <= c nor a;g <= e xor f;x <= g and not p(3);

t <= p xor q;u <= ("11" & a & t(4) & r(3 downto 2) & a & g);y <= (7 => '1' , 4 => u(5), 1 => a , 5 => t(4) , others => '1' );-- array assignment

end architecture;

-- Library inclusionslibrary IEEE;use ieee.std_logic_1164.all;

-- Entity definitionentity CombinationalReview is

generic( N: Integer := 8);port( a: in std_logic;

b: in std_logic;c: in std_logic;p: in std_logic_vector(N-1 downto 0);q: in std_logic_vector(N-1 downto 0);r: in std_logic_vector(N-1 downto 0);x: out std_logic;y: out std_logic_vector(N-1 downto 0)

);end entity;

ArchitecturalDefinition

Internalsignals

HeaderInformation

LibraryInclusions

Entity

Architecture

Generic

Ports

21 © tjEE 3921 – Fall 2017

Combinational Logic Review

• Basic VHDL - Logic

e <= a and b;f <= c nor a;g <= e xor f;x <= g and not p(3);

t <= p xor q;u <= ("11" & a & t(4) & r(3 downto 2) & a & g);y <= (7 => '1' , 4 => u(5), 1 => a , 5 => t(4) , others => '1' );-- array assignment

port( a: in std_logic;b: in std_logic;c: in std_logic;p: in std_logic_vector(N-1 downto 0);q: in std_logic_vector(N-1 downto 0);r: in std_logic_vector(N-1 downto 0);x: out std_logic;y: out std_logic_vector(N-1 downto 0)

);

22 © tjEE 3921 – Fall 2017

Combinational Logic Review

• Basic VHDL - Logic• View Properties

• Highlight a pin or gate

23 © tjEE 3921 – Fall 2017

Combinational Logic Review

• Basic VHDL - Structural

------------------------------------ FullAdder.vhdl---- by: tj---- created: 7/5/2017---- version: 0.0-------------------------------------------------------------------------- 1 bit full adder---- inputs: a, b, cin---- outputs: s, cout------------------------------------

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity FullAdder isport( a: in std_logic;

b: in std_logic;cin: in std_logic;s: out std_logic;cout: out std_logic

);end entity;

architecture behavioral of FullAdder is

signal p: std_logic;signal g: std_logic;

begin

p <= a xor b;g <= a and b;

s <= p xor cin;cout <= g or (p and cin);

end;

24 © tjEE 3921 – Fall 2017

Combinational Logic Review

• Basic VHDL - Structural

25 © tjEE 3921 – Fall 2017

Combinational Logic Review

• Basic VHDL - Structural------------------------------------- FullAdder4.vhdl---- by: tj---- created: 7/5/2017---- version: 0.0-------------------------------------------------------------------------- 4 bit adder to show cell instantiation---- inputs: - a, b, cin---- outputs: - sum, cout------------------------------------

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity FullAdder4 isport( a: in std_logic_vector(3 downto 0);

b: in std_logic_vector(3 downto 0);cin: in std_logic;sum: out std_logic_vector(3 downto 0);cout: out std_logic

);end entity;

architecture structural of FullAdder4 is

------------------------------------ 1 bit full adder prototype----------------------------------component FullAdder is

port( a: in std_logic;b: in std_logic;cin: in std_logic;s: out std_logic;cout: out std_logic

);end component;-----------------------------------

--------------------------------------- intermediate carrys mapped to co-- with 1st stage Cout mapped to co(0) and 4th stage cout mapped to co(3)-------------------------------------signal co: STD_LOGIC_VECTOR(3 downto 0); -- intermediate carrys

beginadd_0:FullAdder port map( a => a(0),

b => b(0), cin => cin, s => sum(0), cout => co(0));

add_1:FullAdder port map(a => a(1), b => b(1), cin => co(0), s => sum(1), cout => co(1));

add_2:FullAdder port map(a => a(2), b => b(2), cin => co(1), s => sum(2), cout => co(2));

add_3:FullAdder port map(a(3), b(3), co(2), sum(3), co(3)); -- NOT reccomended !

cout <= co(3);

end architecture;

ComponentPrototype

Instantiation

ExplicitMapping

Implicit notMapping recommended

26 © tjEE 3921 – Fall 2017

Combinational Logic Review

• Basic VHDL - Structural

27 © tjEE 3921 – Fall 2017

Combinational Logic Review

• Basic VHDL – Structural (generate)

label: for var in index1 to index2 generate

…

end generate;

label: if condition generate

…

end generate;

28 © tjEE 3921 – Fall 2017

Combinational Logic Review

• Basic VHDL – Structural

(generate)------------------------------------- FullAdder4G.vhdl---- by: tj---- created: 7/5/2017---- version: 0.0-------------------------------------------------------------------------- 4 bit adder to show cell instantiation-- using the generate command---- inputs: - a, b, cin---- outputs: - sum, cout------------------------------------

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity FullAdder4G isport( a: in std_logic_vector(3 downto 0);

b: in std_logic_vector(3 downto 0);cin: in std_logic;sum: out std_logic_vector(3 downto 0);cout: out std_logic

);end entity;

architecture structural of FullAdder4G is

------------------------------------ 1 bit full adder prototype----------------------------------component FullAdder is

port( a: in std_logic;b: in std_logic;cin: in std_logic;s: out std_logic;cout: out std_logic

);end component;-----------------------------------

--------------------------------------- intermediate carrys mapped to co-- with cin mapped to co(0) and cout mapped to co(4)-------------------------------------signal co: std_logic_vector(4 downto 0);

begin

co(0) <= cin;

gen_add_4: for i in 0 to 3 generateadd: FullAdder port map( a => a(i),

b => b(i),cin => co(i),s => sum(i),cout => co(i+1));

end generate gen_add_4;

cout <= co(4);

end architecture;

29 © tjEE 3921 – Fall 2017

Combinational Logic Review

• Basic VHDL – Structural

30 © tjEE 3921 – Fall 2017

Combinational Logic Review

• Basic VHDL – Structural

(generate)

(generic)

------------------------------------- FullAdderGN.vhdl---- by: tj---- created: 7/5/2017---- version: 0.0-------------------------------------------------------------------------- N bit adder to show cell instantiation-- using the generate command---- inputs: - a, b, cin---- outputs: - sum, cout------------------------------------

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity FullAdderGN isgeneric( N: INTEGER := 8);port( a: in std_logic_vector(N - 1 downto 0);

b: in std_logic_vector(N - 1 downto 0);cin: in std_logic;sum: out std_logic_vector(N - 1 downto 0);cout: out std_logic

);end entity;

architecture structural of FullAdderGN is

------------------------------------ 1 bit full adder prototype----------------------------------

component FullAdder isport( a: in std_logic;

b: in std_logic;cin: in std_logic;s: out std_logic;cout: out std_logic

);end component;

-----------------------------------

--------------------------------------- intermediate carrys mapped to co-- with cin mapped to co(0) and cout mapped to co(N)-------------------------------------signal co: std_logic_vector(N downto 0);

begin

co(0) <= cin;

gen_add_N: for i in 0 to N-1 generateadd: FullAdder port map( a => a(i),

b => b(i),cin => co(i),s => sum(i), cout => co(i+1));

end generate gen_add_N;

cout <= co(N);

end architecture;

31 © tjEE 3921 – Fall 2017

Combinational Logic Review

• Basic VHDL – Structural

32 © tjEE 3921 – Fall 2017

Combinational Logic Review• Basic VHDL – Arithmetic

• Arithmetic is NOT defined for• std_logic• std_logic_vector

• Arithmetic is only defined for some data types• signed• unsigned• integer• natural

• Include ieee.numeric_std.all to access the signed and unsigned types

33 © tjEE 3921 – Fall 2017

Combinational Logic Review

• Basic VHDL – Arithmetic------------------------------------- arithmetic.vhdl---- by: tj---- created: 7/5/2017---- version: 0.0-------------------------------------------------------------------------- Misc arithmetic circuits---- inputs: 3 bit logic vectors aa,bb---- outputs: logic x-- 3 bit logic vectors p,q,r,s-- 8 bit logic vectors t,u-- 3 bit logic vectors v,w------------------------------------

begin

---- Type Conversionsa_s <= SIGNED(aa);b_s <= SIGNED(bb);a_us <= UNSIGNED(aa);b_us <= UNSIGNED(bb);

c <= a_s + b_s;d <= a_s - b_s;e <= a_us + b_us;f <= a_us - b_us;

g <= a_s * b_s;i <= a_us * b_us;h <= a_s / b_s;j <= a_us / b_us;

---- Type Conversionsp <= STD_LOGIC_VECTOR(c);q <= STD_LOGIC_VECTOR(d);r <= STD_LOGIC_VECTOR(e);s <= STD_LOGIC_VECTOR(f);

t <= STD_LOGIC_VECTOR(g);u <= STD_LOGIC_VECTOR(i);v <= STD_LOGIC_VECTOR(h);w <= STD_LOGIC_VECTOR(j);

x <= not STD_LOGIC(d(1));

end architecture;

library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.NUMERIC_STD.all;

entity arithmetic isgeneric( N: INTEGER := 3);port ( aa, bb: in STD_LOGIC_VECTOR(N-1 downto 0);

p,q,r,s: out STD_LOGIC_VECTOR((N-1) downto 0);t,u: out STD_LOGIC_VECTOR((2*N-1) downto 0);v,w: out STD_LOGIC_VECTOR(((N-1)) downto 0);x: out STD_LOGIC

);end entity;

architecture behavioral of arithmetic is

signal a_s, b_s: SIGNED((N-1) downto 0);signal a_us, b_us: UNSIGNED((N-1) downto 0);signal c, d: SIGNED((N-1) downto 0);signal e, f: UNSIGNED((N-1) downto 0);signal g: SIGNED((2*N-1) downto 0);signal i: UNSIGNED((2*N-1) downto 0);signal h: SIGNED((N-1) downto 0);signal j: UNSIGNED((N-1) downto 0);

34 © tjEE 3921 – Fall 2017

Combinational Logic Review

• Basic VHDL – Arithmetic

4 bit input ???

35 © tjEE 3921 – Fall 2017

Combinational Logic Review• Basic VHDL – Arithmetic

• Subtraction – 2’s complement

a – b a + ( -b) a + ( b +1 )

• Extend both numbers by 1 bit (‘1’ on right side)• 1 + 1 in lsb positions add 1• Adder block has a built in invert capability

• 3 – 1 011 – 001 011 + (110 + 1) 011 + 111 010

011 1110 1010 0 010 2 in 2’s comp