Cognitive Radio Implemenation Ieee

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An Experimental Cognitive Radio for First

Responders

Peiman Amini , Ehsan Azarnasab, Pooyan AminiSalam Akoum, and Behrouz Farhang-Boroujeny

{pamini, azarnas, amini, akoum, farhang}@ece.utah.edu

ECE Department, University of Utah

Abstract—Small Form Factor (SFF) Software Defined Radio(SDR) platform is used to implement an experimental cognitiveradio for first responders. The system was demonstrated in the2007 Software Defined Radio technical conference and productexhibition, and is selected for presentation in the demonstrationsand experimentation track in the IEEE DySPAN 2008.

Different processing tasks are divided between a TI c64x+DSP and a Xilinx Virtex IV FPGA while an ARM9 core is used

to host Greenhills operating system. To tackle the complexityof development, we used progressive simulation based design.Starting from pure simulation of the system, we substitute themodels with real modules step by step to build a fully functionalmodem. To develop the network of the cognitive radio modems,we deploy the available real modems with simulated primaryand secondary users in a central simulation. Three real nodesare presented in our demonstration which perform channelsensing and data transmission.

I. INTRODUCTION

In disaster situations, it is necessary for law enforcement,

rescue agencies, and other first responders to have the abil-

ity to communicate and exchange information quickly and

reliably. Since wired networks cannot be depended upon to

survive in all types of disasters and may be impractical, wire-

less networks are the ideal choice. SDR has been successfully

applied to build cognitive radio systems. A radio for first

responders should be easy to reconfigure and also portable.

Small Form Factor design of Lyrtech platform, similar to

NAVYSYS [1], Kansas University Agile Radio (KUAR) [2],

and Motorola [3] platforms satisfies the requirements for

rescue workers and thus has been chosen in this research.

Cognitive radio technology has been presented as one

possible solution to the spectrum scarcity. From a user’s

perspective, a cognitive radio network should operate iden-

tically to a standard wireless network. However, cognitive

radio nodes should be “aware” of the operation context [4]

and can learn from the past [5]. A cognitive radio network

is built to coexist in a given portion of the spectrum with

the legacy devices. In this presentation, the Family Radio

Service (FRS) band is chosen for transmitting voice and

data [6]. Each node must be able to identify the presence

of non-cognitive communications and share this information

with other nodes. Collaboration allows the cognitive nodes to

communicate reliably and to avoid the legacy devices. Since

the legacy device communication is typically intermittent,

the cognition determines the time for switching frequencies

during transmission.

We denote the FRS users as Primary Users (PU); they

are the legacy users and accordingly have the priority access

to the channel. The cognitive radio (CR) users are called

Secondary Users (SU). The unused parts of the spectrumare called spectral holes (or opportunities) and can be used

by SUs to transmit data. In our experiment, 200 carriers on

462-467 MHz ISM band are used by the cognitive radio to

transmit voice or data, provided that the legacy users are

not using the channel. The method used for sensing should

feature a high spectral dynamic range to enable the detection

of the low power users. We choose the filterbanks spectrum

sensing because of its superior performance compared to FFT

in terms of detecting low power users when users with high

and low power are present [7], [8].

Spectrum sensing is performed on each node before trans-

mission and the results are passed to a basestation which

combines all the sensing information to compile a channelstate information (CSI). CSI is also used by the basesta-

tion for channel allocation. Control channels are used for

exchanging sensing information and control messages such

as channel assignment for the leaf nodes.

Design decisions such as dividing the tasks between FPGA

and DSP, and choosing the appropriate methods to implement

each block are made in order to optimize the usage of the

resources on hardware. First the modem is simulated in

Matlab and Simulink. Then we use System Generator for

DSP to implement the FPGA blocks. Simulink and Real

Time Workshop (RTW) are used to make individual modules

for the DSP. TI Code Composer Studio compiles the DSP

subsystems and combines different DSP modules.

The modeling and simulation environment that supports

this work is based on DEVS (Discrete Event System Spec-

ification) [9]. DEVS is a formalism derived from generic

dynamic systems theory. It has well-defined concepts of

coupling of components, hierarchical, modular model con-

struction, and an object-oriented substrate supporting repos-

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itory reuse. DEVS has been implemented and used as a

practical simulation tool in a variety of implementations. The

DEVSJava environmentis used in this work along with Pro-

gressive Simulation Based Design and development (PSBD)

technique [10] to simplify the development process.

The rest of the paper is organized as follows. An overview

of channel sensing, MAC layer, and transceiver are presentedin Section II. The system architecture including various

modules in DSP and FPGA as well as the interface between

them is presented in Section III. Development tools for

implementing DSP and FPGA are also described in this

section. In Section IV, we discuss the design decisions for

system implementation. Graphical User Interface for running

and monitoring the system is discussed in V. We finally talk

about the implementation status, future research, and draw

our conclusions in Section VI.

I I . TECHNICAL OVERVIEW

Based on PSBD methodology the system is broken into

interworking components. First, we start from a traditional

pure simulation of the system in a simulated environment.

In this example the environment is defined by frequency

usage and channel. Environment is changed as a result of

both PU and SU transmissions or different channel fading

parameters. In the course of PSBD real components are

added to the model, replacing the simulated models. It is

a challenging issue to what extent simulation assisted design

should be involved and to what level the system should be

decomposed. A single real modem itself comprises many

individual modules each a candidate for co-simulation along

with other simulated objects and the environment. Figure 1

shows the PSBD approach of designing a single transceiver

including packet generation, coding, decoding, channel sens-

ing, channel model and emulated PUs.

As we proceed with PSBD, we start using one SDR board.

Most of the functionalities of cognitive radio depend on

sensing the medium. Channel sensing is implemented in the

earliest stage as shown in Fig. 1. To test sensing module

we emulate PU traffic on different frequency bands using

a signal generator, while adjusting some design parameters

such as analogue to digital converter (ADC) gains, frequency

axis margins, and power threshold of PU detection. The

transmitted traffic of PU by the signal generator is a multi-

band waveform which is generated using a Matlab script and

uploaded to the device with Agilent Waveform DownloadAssistant via Ethernet connection with simulator on a PC.

All simulated objects are running on the same PC, while the

SDR board (running implemented components) is connected

to that PC via an Ethernet cable.

A. Channel Sensing and MAC Layer

The basestation assigns channels to the cognitive node

from the pool of discovered opportunities. The efficiency

of opportunity discovery in cognitive radio depends on both

physical and MAC layer design strategies [11]. Depending

on the PU traffic different sensing periods may result in

discovery of more opportunities and better channel alloca-

tion. Sensing the channel should take into consideration the

discrepancy in the received power levels from the different

users and needs to feature a high dynamic range in order to

reliably detect the spectrum holes.In our system, we sense the channel 10 times per second.

To sense the channel, each node halts its transmission, col-

lects the necessary samples and runs the filterbanks sensing

algorithm. The whole process takes less than 1ms. The

sensing information is next reported to the basestation. The

basestation collects the sensing results from all the cognitive

nodes, including itself, and broadcasts the channel allocation

results to all the leaf nodes in the network. The basestation

tags the CSI vector with the time that an activity is last seen

on each carrier to specify the availability of each channel.

Basestation tries to allocate a carrier which is less used and

has neighboring carries which are also idle. When assigning

channels, basestation weighs each carrier by the averageusage in 3 neighboring channels. In this way idle areas of

the spectrum are chosen more frequently.

B. Transmitter

The software defined modem provides two modes of

operation to process two different types of services. One

service is a 19.2 kbps computer-to-computer data stream

while the other service is a 16 kbps Continuously Variable

Slope Delta Modulation (CVSD) vocoded voice. The data

stream is encoded using a rate 1/2 convolutional encoder. An

8 PSK symbol mapping is used for data. For the voice stream,

we use a Reed-Solomon encoder and QPSK signalling.

To use only one digital upconverter from baseband to

Intermediate Frequency (IF) for both services, the packet

assembly is done such that the symbol rate at the input of

the pulse shaping filter is 20 kbps for both data and voice

streams. The transmitted packet consists of two major parts: a

192-sample cyclic preamble, generated using three identical

Binary Phase Shift Key (BPSK) modulated pseudo noise

(PN) sequences of length 64, and a payload constructed using

the data or voice streams output of the symbol mappers.

Upconversion is done using Cascaded-Integrator-Comb

(CIC) filters and a pulse-shaping filter (PSF) whose coef-

ficients are chosen to achieve the Nyquist-M property.

C. Receiver

The received signal is first down-converted by means of a

CPSCIC matched to its transmitter counterpart. The baseband

signal is then passed to the synchronization and channel

equalization modules, both of which implemented in the

fractional space. The fractional spacing between the samples

is chosen to be T s /2, where T s is the symbol interval.

Synchronization is performed using a cyclic preamble.

Cyclic preamble is chosen in our model because it can

2




ire ess anne

Emulator (Vector Signal Generator)

Simulated

Sensingo u ationDemo u ation

anne o inganne Deco ing

Packet DetectionPacket Assembly

Syncronization· · ·

Simulation Implementationrogress

PU2

Simu atePU1

Simu ate

MAC Layer

(On PC

SU

On SDR

Fig. 1. Progressive Simulation-Based design (PSBD) of a single cognitive modem. The implementation starts from the sensing component and progressivelymore of the simulated models (left dotted box) are implemented (right dotted box). The rectangles are DEVS models simulated, and parallelograms areimplemented components on SDR

serve the dual purpose of estimating the timing and carrier

offsets while at the same time equalizing the channel effectswhen coupled with a cyclic equalizer. [12]. The repetition

structure of the cyclic preamble allows us to detect the start

of the packet as well as the carrier offset. This method

exhibits good performance and is easy to implement. Packet

detection is performed by computing the autocorrelation of

the received signal. We correlate the signal with a shifted

version of itself and find the position of the preamble by

identifying the interval over which the autocorrelation is

significantly large [13]. After compensating for the carrier

offset, we make use of a half symbol spaced fractionally-

spaced adaptive equalizer to compensate for the channel

distortion, any residual carrier offset and to obtain the correct

timing phase [13]. The equalizer coefficients obtained using

this algorithm are further fine-tuned using a decision-directed

adaptive scheme.

III. SYSTEM A RCHITECTURE

The base of the platform is the digital processing module.

It is designed around the TMS320DM6446 (also called

DM6446) Digital Media Processor (DMP) System on Chip

(SoC) from TI and Virtex-IV XC4VX35 FPGA from Xilinx.

DM6446 combines an Advanced Very Long Instruction Word

(VLIW) 64x+ DSP and Reduced Instruction Set Computer

(RISC) ARM926J-S cores, where the ARM micro-controller

is mainly set to run the INTEGRITY Real-Time OperatingSystem (RTOS) and DSP performs complex data processing.

The data conversion module is equipped with a 125 MSPS,

14-bit dual channel ADC and a 500 MSPS 16-bit dual

channel interpolating DAC provided by TI. The RF module

is configured to have either 5 or 20 MHz bandwidth with

working frequencies of 200-930 MHz for the transmitter and

30-928 MHz for the receiver. The SDR modem implemen-

tation is divided into different tasks. The SFF SDR platform

gives the designer the option to choose the silicon device

that is most suitable to the task being developed. We use

the INTEGRITY and SMSHELL API provided by Lyrtechto target the board while we develop our signal processing

tasks on the DSP core and the FPGA. The division of

tasks between the DSP and the FPGA was made based on

the availability of resources, the inherent characteristics of

these cores, and the extra functionalities offered by TI and

Xilinx. We make use of the already available Xilinx Logicore

Blocksets for FPGA and the optimized DSP libraries written

for vectors of complex numbers for C64x+ core.

Interfacing between the DSP and FPGA is done using

the Video Processing Sub-system (VPSS) data port. The

DSP VPSS is a DM6446 DSP 16-bit synchronous video

transfer port modified to support transfer of non-video data to

and from the DSP. The VPSS consists of a Video Process-

ing Front End (VPFE) and a Video Processing Back End

(VPBE). The VPFE is used as an input interface to the DSP

and the VPBE as an output interface from the DSP to FPGA.

In the FPGA, a VPSS data port module, also consisting of

a VPBE and a VPFE, is implemented to interface with the

DSP VPSS. The data bus inside the FPGA is a 32-bit and the

VPSS of DM6446 DSP bus is a 16-bit. On the other hand,

custom registers, a shared memory of eight 32-bit words

between the DSP and the FPGA On-Chip Peripheral Bus

(OPB), are used as configuration registers. As a result, the fast

VPSS 32-bit bus, is our gateway between DSP and FPGA.

The tasks developed for the FPGA are implemented usingthe System Generator for DSP. System Generator, an add-on

to Simulink provided by Xilinx, produces a highly optimized

FPGA realization, since each module used in the architecture

maps to an FPGA library component that has been care-

fully constructed and optimized for the FPGA target device.

Moreover, the System Generator provides us with a visual

representation of the system that not only serves as the design

specification, but as the behavioral simulation model and the

source definition for the hardware. The system Generator

3




RS DecoderRS Enoder

Viter i

qua izer

FPGA (Vitex IV, XC4VX35)DSP (c64x+)

↓M 1 ↓M 2

rom RF Fronten

Demodulation

Rd = 1

Carrier Recoveryac et etection

Demapping

Rf =

Rf = 3d =

rom RF Fronten

Demodulation

Rd = 3

ensing Timer Rd =

↓M 3 Lowpass Fi terAGCFilterbank Sensing

inary ata

DSP (c64x+)

Binary Source

Symbol Mapping

Framing ↑M 1 ↑M 2 odulation

onv Encoder

o ronten

Rf = 0

Rf = 1

f =

Rd = 0

a Transmitter b Receiver

FPGA (Vitex IV, XC4VX35)

nter eaverDeinter eaver

CPSCIC I

IC

VPBE VPFE V PBE VPFE

Fig. 2. System data flow

implementation also facilitates the rapid investigation of

various design options in the system [14].

To develop the DSP subsystem, the algorithms targeting

the DSP processor are first implemented in Simulink blocks.

RTW is next used to produce the first version of the code

for the individual Simulink blocks. Each block is then in-

dividually tested in Simulink external simulation. Although

RTW is able to generate stand-alone C code for the Simulink

blocks, it can only be used for rapid prototyping and testingsince the code it generates is not optimized for a specific

DSP or GPP target. The RTW generated code often needs

extra memory and processing power and the optimization

burden is put on the compiler only. The RTW thus cannot

be used to implement the complete DSP subsystem whose

requirements include realtime performance in terms of mem-

ory and speed and special data alignment. To overcome this

problem, a Target Language Compiler (TLC) file is developed

to customize the code generation. In writing the TLC, it

is feasible to use optimized TI DSP libraries DSPLiband

compiler optimization techniques such as giving feedback to

the compiler. Furthermore, the wrapper TLC (unlike inline

TLC) saves a single version of each algorithm and thereforesimplifies code maintenance. The wrapper TLC code (written

for the individual blocks) can be reused in the independent

compilation of the complete DSP subsystem project, without

involving the RTW. Finally, the C code of the complete DSP

subsystem (either generated by RTW or written as wrapper

TLC is compiled by TI Code Composer Studio (CCS). CCS

makes use of the high performance VelociTI architecture of

DM6446 to optimize the code down to the programming level

optimization.

IV. IMPLEMENTATION P ROCESS

The distribution of the SDR modem components between

the DSP core and the FPGA is shown in Figures 2. The

VPBE and VPFE are used to transfer the data streams back

and forth between the two modules while the custom registers

are used for handshaking.

We use a custom register Rf to indicate the services

required by DSP to be done by FPGA. Depending on the

type of data processing required from the FPGA, the DSP

specifies a command number inside the custom register Rf

and then transfers the data through the VPSS. Similarly,

another custom register Rd is used by the FPGA to informthe DSP about the characteristics of the bit-stream arriving at

the VPFE in the DSP subsystem. The DSP, being sequence

based and often running an endless loop, uses the content of

the Rd register to select the appropriate DSP function to be

applied on the incoming data. The transmission is initiated,

as shown in Figure 2, in the DSP core. The binary source is

an arbitrary bitstream of voice or data incoming to the DSP.

The voice data is input from the pcm3008 stereo audio codec

at 48 KHz and encoded by the Continuously Variable Slope

Delta Modulation (CVSD) having a data rate of 16kbps. The

binary voice stream is zero padded to achieve a data rate

of 20kbps. The data traffic, on the other hand, is a fixed

computer-to-computer data stream. This data stream has alower bit error rate than the voice stream and is retransmitted

in the MAC layer (if missed or corrupted) to ensure data

integrity of critical information.

The transmit packet is sent to the FPGA through the VPSS.

The custom register Rf is set to zero if the source is audio

and one if non-audio. In the FPGA, depending on the data

content, either Reed Solomon (RS) coding or convolutional

coding combined with interleaving is performed. Following

the source coding in the FPGA, the binary vectors are

4




Fig. 3. Graphical User Interface

retransferred to the DSP (Rd = 0) to perform modulation

and framing. 8-PSK modulation is used for the data stream

while QPSK is used for voice as per the problem statement.

The binary vector is finally sent back to the FPGA (Rf = 2)

to upconvert the signal to intermediate frequency (IF) and

eventually transmit it over the air. Digital up conversion

in the FPGA consists of three blocks. Combined CIC and

pulse shaper (CPSCIC) that follow the Nyquist-M criterion,

a CIC integrator, and a Direct Digital Synthesizer (DDS) to

modulate the signal to the IF frequency. The CPSCIC filter

we used is a 80-tap FIR filter generated using the Xilinx

FIRCOMPILER provided by the System Generator for DSP.

The baseband signal was modulated to an IF frequency of

30 MHz at a sampling rate of 80 MHz. Note that in the SFF

SDR platform, the FPGA has access to IO, Data Conversion

(DConv) and RF modules.

At the receiver side, two separate functionalities are first

performed in the FPGA, digital down conversion (DDC)and sensing. The resulting signal is then passed to the

DSP (Rd = 1) where synchronization tasks and symbol

demapping are performed. After demapping, the signal is

passed back to the FPGA for decoding (Rf = 2 for voice

and Rf = 3 for data). The decoded signal is finally passed

to the DSP (Rd = 2).This timer activates the sensing module

10 times a second for almost 4µs. The timer control circuit

disables the transmitter functionality while the sensing is

performed. The sensing data is first demodulated to baseband

by means of a DDS whose frequency is centered at the IF

frequency. A lowpass polyphase decimator is used to filter

the required signal band and bring the sampling rate down

to 5 MHz. Note that in order to make use of the maximum

dynamic range of the ADC, An automatic gain amplifier

(AGC) is developed in the DSP to control the gain of the

analogue amplifiers available on the data conversion module

before the signal is digitized. The resulting signal is then sent

to the DSP (Rd = 3) for further processing. In the DSP, the

DSPLib library for C64x+ is used for efficient implementa-

tion of the filterbank sensing. A filterbank is implemented

in polyphase structure using 256 8-tap polyphase elements

which are the decimated coefficients of a prolate filter. The

output of the polyphase elements are then passed through

FFT. The output energy of the filterbanks is then averaged

over three decimated samples. The sensing information is

compared with a tunable threshold to locate possible active

primary users and create a 32-byte channel state information.This information is then transmitted to the basestation. The

basestation compiles the sensing information from all of the

users and creates a common CSI to be used for channel

assignment.

V. GRAPHICAL U SE R I NTERFACE

A Graphical User Interface (GUI) is implemented to

control one basestation, one transmitter and one receiver

(Fig. 3). The bullets in bottom of GUI show the connection

5




status of the boards. DSP and FPGA of these boards can

be reprogrammed in GUI (using buttons on the left). GUI

reads the sensing information from the basestation node and

displays the spectrum analysis results, allocated frequency

to the transmitter, and other cognition related activities in

the network. The results of three spectrum sensing meth-

ods are displayed: FFT, FFT with a Hanning window andfilterbank. These results are averaged over three decimated

sample. The GUI uses the filterbank sensing result of the

connected basestation, while FFT, and FFT with Hanning

window analysis are performed in Matlab modules which

are compiled for Java. The calculated PSD from 462MHz to

467MHz for these three methods are depicted in upper corner

of GUI. The GUI is developed in Java and interfaced with

SFF SDR board using Ethernet connection and SMSHELL

API. Furthermore, the PU detection threshold of sensing in

transmitter can be adjusted. The GUI in Fig. 3 shows the

frequency allocation of the only SU, among 12 detected PUs

which are emulated.

VI . CONCLUSION AND F UTURE R ESEARCH

A fully functional cognitive radio network for first respon-

ders was developed. The system performs channel sensing

to identify the presence of PU, and transmits over unused

portion of the spectrum. A demonstration of the system will

be given at the demonstrations and experimentation track in

the IEEE DySPAN 2008.

Currently we are working on a model for spectrum allo-

cation using game theory. We are going to use more than 8

Universal Software Radio Peripherals (USRP) provided by

Emulab in engineering building at the University of Utah to

record the spectrum activities in a long period. A potential

game model will be used for this problem and as a resultif the users make unilateral decisions the play will converge

to a Nash Equilibrium (NE) and it will have a steady-state

solution [15]. An action space and a utility function will be

defined for this game. The spectrum assignment in our system

will have a distributed algorithm and each cognitive radio

node will select its own frequency band based on the prob-

ability of availability of that frequency band. Game theory

will be used for this decision making process [16]. Similar to

the approach taken in the pioneering work in [17], we plan to

use the available wireless testbed of the Flux Group [18] as

a primary user network and study the effect of different types

of primary user traffics on our cognitive radio as well as the

effect of possible interference from the cognitive network onthe legacy networks. Our proximity with the FLUX group

provides us with this exciting opportunity. For intelligent

spectrum allocation, rather than merely the last sensing result,

a learning mechanism such as genetic algorithm boosts the

performance of the system [5].

ACKNOWLEDGMENTS

We would like to thank Flux Group for using their facility

at Emulab for our experiments. In addition we would like

to thank the hardware and software support that we have re-

ceived from SDR Forum, Lyrtech, Texas Instruments, Xilinx,

Mathworks, Greenhills, Prismtech, Zeligsoft, and Synplicity.

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Cognitive Radio Implemenation Ieee