Coding and Error Control

Coping with Transmission Errors Error detection codes

o Detects the presence of an error

Error correction codes, or forward correctioncodes (FEC)o Designed to detect and correct errorso Widely used in wireless networks

Automatic repeat request (ARQ) protocolso Used in combination with error detection/correctiono Block of data with error is discardedo Transmitter retransmits that block of data

Error Detection Probabilities

Probability of single bit error (BER) Probability that a frame arrives with no bit

errors = (1 - BER)F

Probability that a frame arrives withundetected errors (residual error rate)

Probability that a frame arrives with oneor more detected bit errors

Error Detection Process Transmitter

o For a given frame, an error-detecting code (check bits) iscalculated from data bits

o Check bits are appended to data bits

Receivero Separates incoming frame into data bits and check bitso Calculates check bits from received data bitso Compares calculated check bits against received check

bitso Detected error occurs if mismatch

Parity Check

Parity bit appended to a block of dataEven parity

o Added bit ensures an even number of 1s

Odd parityo Added bit ensures an odd number of 1s

Example, 7-bit character [1110001]o Even parity [11100010]o Odd parity [11100011]

Cyclic Redundancy Check (CRC)

Transmittero For a k-bit block, transmitter generates an (n-

k)-bit frame check sequence (FCS)o Resulting frame of n bits is exactly divisible by

predetermined number

Receivero Divides incoming frame by predetermined

numbero If no remainder, assumes no error

CRC using Modulo 2 Arithmetic

Exclusive-OR (XOR) operationParameters:

• T = n-bit frame to be transmitted• D = k-bit block of data; the first k bits of T• F = (n – k)-bit FCS; the last (n – k) bits of T• P = pattern of n–k+1 bits; this is the predetermined

divisor• Q = Quotient• R = Remainder

CRC using Modulo 2 Arithmetic

For T/P to have no remainder, start with

Divide 2n-kD by P gives quotient andremainder

Use remainder as FCS

FDTkn

+=!

2

P

RQ

P

Dkn

+=!

2

RDTkn

+=!

2

CRC using Modulo 2 Arithmetic

Does R cause T/P to have no remainder?

Substituting,

o No remainder, so T is exactly divisible by P

P

R

P

D

P

RD

P

Tknkn

+=+

=!!

22

QP

RRQ

P

R

P

RQ

P

T=

++=++=

CRC using Polynomials

All values expressed as polynomialso Dummy variable X with binary coefficients

( )( )

( )( )( )

( ) ( ) ( )XRXDXXT

XP

XRXQ

XP

XDX

kn

kn

+=

+=

!

!

Error Detection using CRC

All single bit errors, if P(X) has more than onenon-zero term

All double bit errors, as long as P(X) has a factorwith at least 3 terms

All odd errors, as long as P(X) contains X+1 as afactor

Any burst error of length at most n-k

CRC using Polynomials

Widely used versions of P(X)o CRC–12

• X12 + X11 + X3 + X2 + X + 1

o CRC–16• X16 + X15 + X2 + 1

o CRC – CCITT• X16 + X12 + X5 + 1

o CRC – 32• X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5

+ X4 + X2 + X + 1

CRC using Digital Logic

Dividing circuit consisting of:o XOR gates

• Up to n – k XOR gates• Presence of a gate corresponds to the presence of a

term in the divisor polynomial P(X)

o A shift register• String of 1-bit storage devices• Register contains n – k bits, equal to the length of the

FCS

Digital Logic CRC

Wireless Transmission Errors

Error detection requires retransmissionDetection inadequate for wireless

applicationso Error rate on wireless link can be high, results

in a large number of retransmissionso Long propagation delay compared to

transmission time

Block Error Correction Codes

Transmittero Forward error correction (FEC) encoder maps

each k-bit block into an n-bit block codewordo Codeword is transmitted; analog for wireless

transmission

Receivero Incoming signal is demodulatedo Block passed through an FEC decoder

FEC Decoder Outcomes

No errors presento Codeword produced by decoder matches

original codeword

Decoder detects and corrects bit errorsDecoder detects but cannot correct bit

errors; reports uncorrectable errorDecoder detects no bit errors, though

errors are present

Block Code Principles

Hamming distance – for 2 n-bit binary sequences,the number of different bitso E.g., v1=011011; v2=110001; d(v1, v2)=3

Redundancy – ratio of redundant bits to data bits Code rate – ratio of data bits to total bits Coding gain – the reduction in the required Eb/N0

to achieve a specified BER of an error-correctingcoded systemo BER refers to rate of uncorrected errors

Block Codes

The Hamming distance d of a Block code isthe minimum distance between two codewords

Error Detection:o Up to d-1 errors

Error Correction:o Up to

!"

!#$

# %

2

1d

Coding Gain

Definition:o The coding gain is the amount of additional SNR or Eb/N0

that would be required to provide the same BERperformance for an uncoded signal

If the code is capable of correcting at most terrors and PUC is the BER of the channel withoutcoding, then the probability that a bit is in errorusing coding is:

in

UC

i

UC

n

ti

CBPP

i

ni

nP

!

+=

!""#

$%%&

'( ) )1(1

1

Hamming Code Designed to correct single bit errors Family of (n, k) block error-correcting codes with

parameters:o Block length: n = 2m – 1o Number of data bits: k = 2m – m – 1o Number of check bits: n – k = mo Minimum distance: dmin = 3

Single-error-correcting (SEC) codeo SEC double-error-detecting (SEC-DED) code

Hamming Code Process

Encoding: k data bits + (n -k) check bitsDecoding: compares received (n -k) bits

with calculated (n -k) bits using XORo Resulting (n -k) bits called syndrome wordo Syndrome range is between 0 and 2(n-k)-1o Each bit of syndrome indicates a match (0) or

conflict (1) in that bit position

Cyclic Block Codes Definition:

o An (n, k) linear code C is called a cyclic code if every cyclic shiftof a code vector in C is also a code vector

o Codewords can be represented as polynomials of degree n. Fora cyclic code all codewords are multiple of some polynomialg(X) modulo Xn+1 such that g(X) divides Xn+1. g(X) is calledthe generator polynomial.

Examples:o Hamming codes, Golay Codes, BCH codes, RS codeso BCH codes were independently discovered by Hocquenghem

(1959) and by Bose and Chaudhuri (1960)o Reed-Solomon codes (non-binary BCH codes) were

independently introduced by Reed-Solomon

Cyclic Codes

Can be encoded and decoded using linearfeedback shift registers (LFSRs)

For cyclic codes, a valid codeword (c0, c1, …, cn-1),shifted right one bit, is also a valid codeword (cn-1,c0, …, cn-2)

Takes fixed-length input (k) and produces fixed-length check code (n-k)o In contrast, CRC error-detecting code accepts arbitrary

length input for fixed-length check code

Cyclic Block Codes

A cyclic Hamming code of length 2m-1 with m>2 is generatedby a primitive polynomial p(X) of degree m

Hamming code (31, 26)o g(X) = 1 + X2 + X5, l = 3

Golay Code:o cyclic code (23, 12)o minimum distance 7o generator polynomials: either g1(X) or g2(X)

119765

2

11106542

1

1)(

1)(

XXXXXXXg

XXXXXXXg

++++++=

++++++=

BCH Codes

For positive pair of integers m and t, a (n,k) BCH code has parameters:o Block length: n = 2m – 1o Number of check bits: n – k <= mto Minimum distance:dmin >= 2t + 1

Correct combinations of t or fewer errorsFlexibility in choice of parameters

o Block length, code rate

Reed-Solomon Codes Subclass of non-binary BCH codes Data processed in chunks of m bits, called

symbols An (n, k) RS code has parameters:

o Symbol length: m bits per symbolo Block length: n = 2m – 1 symbols = m(2m – 1) bitso Data length: k symbolso Size of check code: n – k = 2t symbols = m(2t) bitso Minimum distance: dmin = 2t + 1 symbols

Block Interleaving Data written to and read from memory in different

orders Data bits and corresponding check bits are

interspersed with bits from other blocks At receiver, data are deinterleaved to recover

original order A burst error that may occur is spread out over a

number of blocks, making error correctionpossible

Block Interleaving

Convolutional Codes Generates redundant bits continuously Error checking and correcting carried out

continuouslyo (n, k, K) code

• Input processes k bits at a time• Output produces n bits for every k input bits• K = constraint factor• k and n generally very small

o n-bit output of (n, k, K) code depends on:• Current block of k input bits• Previous K-1 blocks of k input bits

Convolutional Encoder

Decoding Trellis diagram – expanded encoder diagram Viterbi code – error correction algorithm

o Compares received sequence with all possibletransmitted sequences

o Algorithm chooses path through trellis whose codedsequence differs from received sequence in the fewestnumber of places

o Once a valid path is selected as the correct path, thedecoder can recover the input data bits from the outputcode bits

Automatic Repeat Request

Mechanism used in data link control andtransport protocols

Relies on use of an error detection code(such as CRC)

Flow ControlError Control

Flow Control Assures that transmitting entity does not

overwhelm a receiving entity with data Protocols with flow control mechanism allow

multiple PDUs in transit at the same time PDUs arrive in same order they’re sent Sliding-window flow control

o Transmitter maintains list (window) of sequencenumbers allowed to send

o Receiver maintains list allowed to receive

Flow Control

Reasons for breaking up a block of databefore transmitting:o Limited buffer size of receivero Retransmission of PDU due to error requires

smaller amounts of data to be retransmittedo On shared medium, larger PDUs occupy

medium for extended period, causing delays atother sending stations

Flow Control

Error Control

Mechanisms to detect and correcttransmission errors

Types of errors:o Lost PDU : a PDU fails to arriveo Damaged PDU : PDU arrives with errors

Techniques:o Timeoutso Acknowledgmentso Negative acknowledgments

Hybrid ARQ

Combining error correction and error detectiono Chase combiningo Incremental redundancy

Chase combining (Type I)o At receiver, decoding done by combining retransmitted

packets

Incremental redundancy (Type II/III)o First packet contains information and selected check bitso Subsequent packets contain selected check bitso Receiver decodes by combining all received bits

Commonly used in wireless networks