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Code VHDL, hướng dẫn học VHDL

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Page 1: code vhdl

Library IEEE;Use IEEE.STD_LOGIC_1164.ALL;Use IEEE.STD_LOGIC_ARITH.ALL;Use IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY Led7 ISPORT ( a_to_g : OUT std_logic_vector (6 downto 0);

en: out std_logic_vector (3 downto 0);CLK: in std_logic ); END Led7;

ARCHITECTURE Behav OF Led7 ISSIGNAL display: std_logic_vector (6 downto 0);SIGNAL number_dv: std_logic_vector (3 downto 0);SIGNAL number_chuc: std_logic_vector (3 downto 0);SIGNAL buff: std_logic_vector (3 downto 0);SIGNAL counter_time: std_logic_vector (27 downto 0); -- tan so –SIGNAL counter_led: std_logic_vector (20 downto 0);SIGNAL sel: std_logic;BEGINPROCESS (CLK)

BEGIN IF rising_edge(CLK) then

IF counter_time < “101111101011110000100000000” THEN –- tan so 100000000 hz --

counter_time <= counter_time +1;ELSE couter_time <= (other => ‘0’);IF number_dv < “1001” THEN number_dv <= number_dv +1;ELSE number_dv <= “0000”;IF number_chuc < “1001” THENnumber_chuc <= number_chuc +1;ELSE number_chuc <= “0000”;END IF;END IF;END IF;

IF counter_time < “11110100001001000000” THEN --- tan so 1000000 –counter_led <= counter_led +1;ELSE counter_led (other => ‘0’);sel <= not (sel);END IF;END IF;IF (sel = ‘0’) THEN buff <= number_chuc ;en <= “1101”;elsebuff <= number_dv;en <="1110";

Page 2: code vhdl

end if;case buff is when “0000” => display “0000001”when "0001" => display <= "1001111";when "0010" => display <= "0010010";when "0011" => display <= "0000110";when "0100" => display <= "1001100";when "0101" => display <= "0100100";when "0110" => display <= "0100000";when "0111" => display <= "0001111";when "1000" => display <= "0000000";when others => display <= "0000100";end case;end process ;a_to_g <= display;

end Behavioral;