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8/10/2019 Co Introduction
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COMPUTERORGANIZATION
AND
ARCHITECTURE
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BASIC STRUCTURE OF COMPUTERS
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Functional Units
Input
Output
Arithmetic
and logic
Control
Memory
I/O Processor
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Input Unit
Input Unit reads the dataThe most common Input devices are Keyboard,
joystick, trackballs, microphone and mouse
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Memory Unit
The function of memory unit is to store programs and
data
There are 2 classes of storage:
Primary Storage:
Fast memory that operates at electronic speeds The memory contains a large number of semiconductor
storage cells, each capable of storing 1 bit of information
These cells are processed in groups of fixed size called word
The number of bits in each word is known as word length
Range from 16 to 64 bits
To provide easy access to any word in the memory, a
distinct addressis associated with each word
location
Addresses are numbers that identify successive locations
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Memory in which any location can be reached in ashort and fixed amount of time after specifying itsaddress is RAM
Time required to access one word is called thememory access time
Memory of a computer is normally implemented asa memory hierarchy of 3 or 4 levels ofsemiconductor RAM units with different speeds &sizes
The small, fast, units are called caches The largest & slowest unit is referred to as themain memory
Primary storage is expensive
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Secondary Storage: Is used when large amount of data and
many programs have to be stored
It contains infrequently accessedinformation
Additional & cheaper memory
Ex: Magnetic disks and tapes & optical
disks (CD-ROMs)
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Arithmetic And Logic Unit
ALU performs all the arithmetic and logicoperations
For ex: addition, multiplication, division,comparison etc
Any operation is initiated by bringing therequired operands into the processor, wherethe operation is performed by the ALU
When operands are brought into the
processor, they are stored in high- speedstorage elements called registers
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Each register can store one word of dataAccess time to registers are faster than cache
unit
CU & ALU are many times faster than other
devices connected to a computer system
This enables a single processor to control a
number of external devices such as keyboards,
displays, magnetic & optical disks, sensors &
mechanical controllers
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Control Unit
It controls the entire operations of the computerThe control unit is the nerve centre that sends control
signals to other units and senses their states
The timing signals that govern the I/O transfers are
generated by control circuits Timing signalsare signals that determine when a
given action is to take place
Data transfers b/w processor & memory are also
controlled by CU through timing signalsA large set of control lines (wires) carries the signals
used for timing & synchronization of events in all
units
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Operation of a Computer - Summarized
The computer accepts information in the form ofpgms & data through an I/P unit & stores it in the
memory
Information stored in the memory is fetched, under
pgm control, into an ALU, where it is processedProcessed information leaves the computer through
an O/P unit
All activities inside the machine are directed by the
CU
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Information Vs Instructions
Instructions/ Machine instructions : Are explicit commands that
Governs transfer of information within the computer as
well as between computer and its I/O devices
Specify arithmetic and logic operations to be performed
Data:
Numbers and encoded characters that are used as operands
by the instructions
Any digital information
Programs can also be considered as data if it is to be
processed by another pgm
Ex: Compiling a HLL source pgminto machine language pgm,
called the object pgm
(Source pgmis I/P data to compiler & object pgmis O/P data)
The processed data is called information
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Information must be encoded in a suitable formatEach number, char/ instruction encoded as a string of
binary digits called bits, each having either 0 or 1
Ex:
BCD (Binary - Coded Decimal) Each decimal digit is encoded by 4 bits
ASCII (American standard Code for Information
Interchange)
Each char is represented as a 7-bit code EBCDIC ( Extended Binary- Coded Decimal
Interchange Code)
8 bits are used to denote a char
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Basic Operational Concepts
For processing, individual instructions are brought from memory intothe processor, which executes the specified operations
Data to be used as operands are also stored in memory
A typical instruction may be:
Add A,R0
Adds the operand at memory location A to the operand in register R
and store the result in R0
The original content of A is preserved, whereas R0 are overwritten
Instruction requires several steps
Load A, R1Add R1,R0
The first instruction transfers the contents of A into the processor
register R1
The second instruction adds the contents of R1 and R0 and places the content
in R0
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MAR - Memory Address Register
MDR - Memory Data Register
PC - Program Counter
IR - Instruction Register
Control
Unit
Arithmetic
Logic
Unit
Connection between the processor and memory
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CPU = ALU + CU + registers
Diff: types of registers are:
IR (instruction register):
Holds the instruction that is currently being executed
Its o/p is available to control circuits, which generate the timing
signals that control the various processing elements involved in
executing the instruction
PC (program counter):
Keeps track of the execution of a pgm
Contains the memory address of next instruction to be fetched &
executed
During the execution of an instruction, the contents of PC are
updated to correspond to the address of next instruction that is to
be fetched from the memory
PC points to the next instruction that is to be fetched from memory
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n general- purpose registers (R0 thru Rn-1): are used for holding data, intermediate results of operations.
They are also known as scratch-pad registers.
MAR (memory address register):
Facilitates communication with memory
Holds the address of the location to be accessed
MDR (memory data register):
Facilitates communication with memory
Contains data to be written into or read out of the addressedlocation
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Execution of an instruction
Execution of an instruction by CPU during pgmexecution involves the following steps: The CU takes the address of the next instruction to be
executed from the PC register & reads instruction fromcorresponding memory address into the instruction registerof CU
The CU sends the operation part & address part ofinstruction to the decoder & MAR respectively
The decoder interprets the instruction and accordingly theCU sends signals to the appropriate unit which needs to beinvolved in carrying out the task specified in the instruction
Ex: if it is arithmetic/logical operation, the signal is send to ALU As each instruction is executed, the address of the next
instruction to be executed will be automatically loaded intothe PC register & steps 1 to 4 are repeated
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Normal execution of pgms may be preemptedif some device requires urgent servicing
To deal with the situation immediately, normalexecution of current pgm must be interrupted
To do this, the device raises an interruptsignal
Interrupt Is a request from an I/O device for service by the
processorProcessor provides the requested service byexecuting an appropriate interrupt-serviceroutine
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Computer Instructions
Assembly Language
MOVE NUM1,R1
MOVE #1,R2
ADD #1,R1
ADD R1,R2
Register Transfer
Notation
R1
[NUM1]
R21
R11 + [R1]
R2[R1] + [R2]
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The fetch-execute cycle
Fetch the instruction whose address isin the program counter
Increment the PC so it holds the
address of the next instructionExecute the instruction just fetched
Fetch the next instruction
Etc.
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Example Instruction
Fetch
MAR
[PC] PC[PC] + 1
MDR[MEM([MAR])]
IR[MDR]
Execute
MARNUM1 MDR[MEM([MAR])]
R1[MDR]
MOVE NUM1,R1
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Another Example
Fetch
MAR
[PC] PC[PC] + 1
MDR[MEM([MAR])]
IR[MDR]
Execute
R1
1 + [R1]
ADD #1,R1
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Bus Structures
A group of lines that serves as aconnecting path for several devices is
called a bus
Bus must have lines for Data
Address
Control
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Single-bus Structure
Input Output Memory Processor
The simplest way to interconnect functional units to use
a single bus
Since the bus can be used for only one transfer at a
time, only two units can actively use the bus at any
given time
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Its basic feature is its low cost and flexibility forattaching peripheral devices
Systems containing multiple buses increase its
performance capability (by concurrency in
operations) but at an increased cost
Buffer registers
to hold the information during transfers with the
devices
Allows processor to switch rapidly from one deviceto another
Ex: use of printer buffer during printing
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Transfer of a character from a processor to acharacter printer
Processor sends the character to the
printer buffer
Once buffer is loaded, the printer can start
printing without intervention by the
processor
The system bus is also called the frontside bus, memory bus, local bus, or
host bus.
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Simplified Illustration of a Bus
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Two-Bus Structure
Input
Output
ProcessorMemory
I/O bus
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The bus is said to perform two distinct functions
by connecting the I/O units with memory and
processor unit with memory. The processor
interacts with the memory through a memory
bus and handles input/output functions over I/Obus.
The main advantage of this structure is good
operating speed but on account of more cost.
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Software
A set of instructions/ programs is known as SoftwareSoftware's are of 2 types:
System Software:
It is responsible for the coordination of all activities in a
computing system
It perform functions such as:
Receiving & interpreting user commands
Entering & editing application pgms & storing themas files in secondary storage devices
Managing the storage & retrieval of files in
secondary storage devices
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Running standard application pgms such asword processors, spreadsheets or games
with data supplied by the user
Controlling I/O units to receive input
information & produce output results
Translating pgms from source form
prepared by the user into object form
consisting of machine instructions
Linking & running user-written application
pgms with existing standard library routines,
such as numerical computation packages
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Ex: for System Software
Compiler High-level LanguageMachine LanguageAssembler Assembly LanguageMachine Language
Operating System Control Sharing & Interaction
Assign & Manage Resources Memory
Disk Space
Handle I/O
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Application Software: Application software is used for
implementing a particular application
Ex: MSWord, Excel
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Figure 1.4. User program and OS routine sharing of the processor.
Printer
Disk
Program
routines
OS
Timet0 t1 t2 t3 t4 t5
User program and OS routine sharing of the processor
Time-line diagram (an ex:)
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OS manages the concurrent execution of several
application pgms to make best possible use of
computer resources
Multiprogramming/multitasking
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Performance
The most important measure of theperformance in a computer is how quickly it
can execute programs
The speed of execution depends on thedesign of its hardware and its machine
language instructions and also the compiler
For better performance all componentsshould be designed in a coordinated way
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Elapsed timeTotal time required to execute the pgm
Measure of computers performance
Depends on speed of processor, disk &printer
Processor time
Period during which the processor isactive to execute the pgm
Th P C h
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The Processor Cache
Main
memoryCache
memoryProcessor
Bus
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At the start of execution, all pgm instructions& the required data are stored in mainmemory
As execution proceeds, instructions are
fetched one by one over the bus into theprocessor, and a copy is placed in the cache
When the execution of an instruction calls fordata located in the main memory, the data
are fetched & a copy is placed in the cacheLater, if the same instruction/ data item areneeded a second time, it is read directly fromthe cache
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A program will be executed faster if themovement of instructions and data between
the processor and main memory is
minimized, which is achieved by using
cache
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Processor Clock
Processor circuits are controlled by a timing signalcalled a clock
The regular time intervals are known as clock cycles
To execute machine instructions the processor divides
the action into a sequence of steps such that each step
can be completed in one clock cycle
The length P of one clock cycle is an important
performance parameter of processorClock rate, R=1/P, measured in cycles/sec
(Hertz/Hz)
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Million - Mega (M)Billion - Giga (G)
500 million cycles/sec500 MHz
Clock period is 2 ns
1250 million cycles/sec1.25 GHz Clock period is 0.8 ns
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Basic Performance Equation
T=(N x S) / R
T is the processor time required to execute a program
N is the actual number of instruction executions
S is the average number of basic steps needed to executeone machine instruction
R is the clock rate
To achieve high performance, reduce the value of T,
which means reducing N & S and increasing R
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Performance Equation
MIPS: Millions of instructions persecond
Megaflops: Millions of floating point
operations per secondMegahertz: Millions of clock cycles per
second
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Pipelining and Superscalar Operation
Assumed that instructions are executed one after another
Improvement in performance can be achieved by
overlapping the successive instructions using a
technique called pipelining
Consider the instruction Add R1,R2,R3
Which adds the contents of registers R1 & R2 and places the sum intoR3
Contents of R1 & R2 are first transferred to the inputs of ALU
After add operation is performed, sum is transferred to R3
The processor can read the next instruction while the addition operationis being performed
Then, if that instruction also uses ALU, its operands can be transferredto the ALU inputs at the same time that the result of Add instruction is
being transferred to R3
Pi li i
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Pipelining
F1 E1
I1
F2 E2
I2
F3 E3
I3
Sequential Execution
F1 E1I1
F2 E2I2
F3 E3I3
Pipelined Execution
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For purpose of computing, effective value of S is 1(cant attain in practice)
Pipelining increases rate of executing instructionssignificantly & causes the value of S to approach 1
A higher degree of concurrency can be achieved if
multiple instruction pipelines are implemented in theprocessor Means that multiple functional units are used, creating
parallel paths through which different instructions can beexecuted in parallel
With this, it becomes possible to start the execution ofseveral instructions in every clock cycle
This mode of operation is called Superscalar executio n
C
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Clock Rate
There are 2 possibilities for increasing theclock rate, R
First, improving the Integrated Circuit (IC)technology makes logic circuits faster, which
reduces the time needed to complete a basic step This allows the clock period, P to be reduced and the
clock rate, R to be increased
Second, reducing the amount of processing done in
one basic step makes it possible to reduce clockperiod, P
I i S CISC & RISC
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Instruction Set: CISC & RISC
Simple instructions require small number of basicsteps to execute (Reduced Instruction SetComputers)
Complex instructions involve a larger number ofbasic steps (Complex Instruction Set Computers)
For RISC a large number of instruction is needed,lead to large value for N, and small value for S
For CISC individual instructions perform morecomplex operations with fewer instructions,
leading to lower value of N and larger value of SIt is not obvious if one choice is better than theother
CISC RISC
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CISC vs RISC
Complex Instruction Set Computers(CISC)
Smaller N
Larger SReduced Instruction Set Computers
(RISC)
Larger N Smaller S
Easier to Pipeline
C il
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Compiler
High-level LanguageMachine Language
To reduce N, suitable machine instruction set + compilerthat makes good use of it
An optimizing compilermust reduce the number of clockcycles needed to execute a program
The number of clock cycles is dependent not only on thechoice of instructions but also on the order in which theyappear in the program
The compiler may rearrange the instructions to achievebetter performance
Such changes must not affect the result of the computation
Ultimate objective is to reduce the total no: of clock cyclesneeded to perform a required pgmg task
P f M t
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Performance Measurement
The only parameter that describes the performance of
a computer is the execution time T
A nonprofit organization called System
Performance Evaluation Corporation (SPEC)
publishes representative application programs fordifferent application domains, together with test
results for many commercially available computers
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SPEC rating = Running time on thereference computer
Running time on the
computer under test
Spec rating of 50 means that computer under test
is 50 times as fast as UltraSPARC10 for this
particular benchmark
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The overall SPEC rating for the computer is SPEC rating =(SPECi)1/n
Where n is the no: of pgms in the suite
Bcoz the actual execution time is measured,the SPEC rating is a measure of the
combined effect of all factors affecting
performance, including the compiler, the OS,
the processor & the memory of the computer
system being tested
i=1
n
M lti
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Multiprocessors
Larger computer systems may contain a number ofprocessor units, in which case they are called
Multiprocessor Systems
These systems either execute a number of different
application programs in parallel or they execute thesubtasks of a single large task in parallel
All processors have access to all of the memory in
such systems and the term shared memory
multiprocessor systemsis often used
High performance of the system increased
complexity and cost
M lti t
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Multicomputers
It is possible to use an interconnected group ofcomplete computers to achieve high total
computational power
These computers have access to their own memory
units When the tasks they are executing need to communicate
data, they do so by exchanging messages over a
communication network
This property leads to the name message-passingmulticomputers
St i l i I t ti F t h & E ti
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Steps involving Instruction Fetch & Execution
Pgms reside in the memory and usually getthere through the i/p unit
INSTRUCTION FETCH
Execution of a program starts by setting thePC to point to the first instruction of theprogram
The contents of PC are transferred to theMAR and a Read control signal is sent to thememory
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The addressed word (here it is the firstinstruction of the program) is read out of
memory and loaded into the MDR
The contents of MDR are transferred to
the IR
Now the instruction is ready to be decoded &executed
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INSTRUCTION EXECUTION
The operation field of the instruction in IR
is examined to determine the type ofoperation to be performed by the ALU
The specified operation is performed byobtaining the operand(s) from the memorylocations or from GP registers in theprocessor
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Fetching the operands from the memory
requires sending the memory location address
to the MAR and initiating a Read cycle
The operand is read from the memory into the
MDR and then from MDR to the ALUThe ALU performs the desired operation on one
or more operands fetched in this manner and
sends the result either to memory location or to
a GP register
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If the result of this operation is to be stored in thememory, then the result is sent to MDR
The address of the location where the result is tobe stored is sent to MAR and a Write cycle is
initiated
Thus, the execute cycle ends for the currentinstruction and the PC is incremented to point tothe next instruction for a new fetch cycle.