CMPE 421 Advanced Computer Architecture Supplementary material for Pipelining PART1

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  • CMPE 421 Advanced Computer Architecture Supplementary material for Pipelining PART1
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  • 3 304020304020304020304020 6 PM 789 10 11 Midnight Time Pipelining Lessons: Laundry Machine example Slow Way If each load is done sequentially it takes 6 hours
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  • 4 Pipelined laundry takes 3.5 hours Pipelining Lessons: Laundry Machine example Quick way 6 PM 789 Time 3040 20
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  • 5 Single Cycle Datapath
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  • 6 ALU Pipeline Divisions Divide datapath into steps 1 cycle each Instructions range from 3-5 stages in MIPS pipeline RegsRegs RegsRegs Data Memory Instr. Memory IF Instruction Fetch ID/RF Register Fetch EX Execution MEM. Memory WB Write back PCPC
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  • 7 Revised: Single Cycle Datapath
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  • 8 Multicycle Datapath/Control xtend 3216 Instruction [2521] Instruction [2016] Instruction [150] Instruction register ALU control ALU result ALU Zero Memory data register A B IorD MemRead MemWrite MemtoReg PCWriteCond PCWrit e IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op [50] Instruction [31-26] Instruction [50] M u x 0 2 Jump address [31-0] Instruction [250] 2628 Shift left 2 PC [31-28] 1 1 M u x 0 3 2 M u x 0 1 ALUOut Memory MemData Write data Address write control
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  • 9 Pipeline Datapath
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  • 10 Load Datapath: Stage 1 A
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  • 11 Load Datapath: Stage 2 B
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  • 12 Load Datapath: Stage 3
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  • 13 Load Datapath: Stage 4 A
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  • 14 Load Datapath: Stage 5 B
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  • 15 Store Datapath: Stage 3
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  • 16 Store Datapath: Stage 4
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  • 17 Store Datapath: Stage 5
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  • 18 Corrected Pipelined datapath for lw