cmos12

IC design L. 13 September 18, 2001

13 Input/Ouput Circuits

Input/Output circuits (I/O pads) are intermediate structures connectinginternal signals from the core of the integrated circuit to the externalpins of the chip package.

An I/O pad consists of

a bonding pad an area to which the bond wire is soldered.The wire goes to a chip pin.

ESD (electrostatic discharge) protecting circuitry. Driving and logic circuitry.

Typically I/O pads are organized into a rectangular Padframe.

The smallest padframe available for the MOSIS chip fabrication( http://www.mosis.org/ ), TinyChip, consists of 40 pins, 10 on eachside.

Examples of the 40-pin padframe and the size of an individual pad forthe AMI0.5 technology follows.

Note that in this technology = 0.3.

The complete AMI0.5 pad documentation is given inhttp://www.mosis.org/cell-libraries/scn05-pads-tiny/mAMI05P.pdf

The size of the 40-pin padframe is 1.51.5mm, to core area being0.90.9mm.The size of the bonding pad is 6060 (200).The ESP circuitry takes twice the area of 7878 (260).

A.P.Paplinski 131


mAMI05P MOSIS AMI 0.5m Hi-ESDPad Cell Library

Rev. APADFRAME

Page4 of 4

Copyright 1998 by Tanner Research, Inc. All rights reserved.

Pad Frame Layout PADFRAME

A.P.Paplinski 132


A.P.Paplinski 133


A.P.Paplinski 134


13.1 The simplest I/O pad

The simplest I/O signal pad consists of only

Bonding pad, and ESD Protection circuitry

The bonding pad consists of metal1 and metal2 squares connectedtogether by a perimeter of vias as in the following figure

The ESD protection circuit is symbolically shown in the schematic andconsists of a pair of equivalent MOS transistors with gates tied up tothe respective power supply terminals.

A.P.Paplinski 135



Rev. APADAREF

Page3 of 4


Analog Ref Pad Schematic PADAREF

SIGNALSIGNAL

PadARef

L='3*l'

M=6

TESDP

W='100*l'

BONDING

PAD

L='3*l'

M=6

TESDN

W='100*l'

A.P.Paplinski 136



Rev. APADAREF

Page4 of 4


Analog Ref Pad Layout PADAREF

A.P.Paplinski 137


13.2 ESD Protection

Electrostatic discharge (ESD) occurs when the charge stored in thehuman body or other devices is discharged to the gate of a MOStransistor on contact or by static induction.

If, for example, the charge on the human body is discharged as acurrent of 10A flowing for 1s to a gate capacitor of Cg = 0.025pF,then the voltage which will build up on the transistor gate is

V =10 106 1060.025 1012 = 400V

Such a voltage destroys MOS transistors, therefore, ESD protection isessential for the I/O circuitry.

A typical solution of the ESD protection problem is to use clampingdiodes implemented using MOS transistors with gates tied up to eitherGND for nMOS transistors, or to VDD for pMOS transistors.

For normal range of input voltages these transistors are in the off state.If the input voltage builds up above (or below) a certain level, one ofthe transistor starts to conduct clamping the input voltage at the savelevel.

These clamping transistors are very big structures consisting of anumber of transistors connected in parallel, and are able to sustainsignificant current.

A.P.Paplinski 138


Figure 131: The pMOS section of the ESD protection circuitry. 1. The completelayout. 2. The metal1 and polysilicon layers. 3. The polysilicon and the p+select(around p diffusion) layers. 4. The polysilicon, p+select and n+select layers.

Note:

Parallel connected pMOS transistors with gates and sourcesconnected to VDD,

Double guard rings: n+ guard ring connected to VDD aroundpMOS, and p+ guard ring connected to GND around the n+ ringin order to prevent latch-up effect.

A.P.Paplinski 139


13.3 The Latch-up Problem and its prevention

Large MOS transistor are susceptible to the latch-up effect.In the chip substrate, at the junctions of the p and n material, parasiticpnp and npn bipolar transistors are formed as in the followingcross-sectional view:

These bipolar transistors form a silicon-controlled rectifier (SRC) withpositive feedback as in the following circuit model:

The final result of the latch-up is the formation of a short-circuit (a lowimpedance path) between VDD and GND which results in destructionof the MOS transistor.

A.P.Paplinski 1310


Guidelines for Avoiding Latch-Up

(Quoted from Kang, Leblebici)

Use p+ guardband rings connected to ground around nMOStransistors and n+ guard rings connected to VDD around pMOStransistors to reduce Rw and Rsub and to capture injected minoritycarriers before they reach the base of the parasitic BJTs.

Place substrate and well contacts as close as possible to the sourceconnections of MOS transistors to reduce the values of Rw andRsub.

Use minimum area p-wells (in case of twin-tub technology orn-type substrate) so that the p-well photocurrent can beminimized during transient pulses.

Source diffusion regions of pMOS transistors should be placed sothat they lie along equipotential lines when currents flow betweenVDD and p-wells. In some n-well I/O circuits, wells areeliminated by using only nMOS transistors.

Avoid the forward biasing of source/drain junctions so as not toinject high currents; the use of a lightly doped epitaxial layer ontop of a heavily doped substrate has the effect of shunting lateralcurrents from the vertical transistor through the low- resistancesubstrate.

Lay out n- and p-channel transistors such that all nMOStransistors are placed close to GND and pMOS transistors areplaced close to VDD rails. Also maintain sufficient spacingsbetween pMOS and nMOS transistors.

A.P.Paplinski 1311


13.4 Output pads

The simplest driver for the output pad consists of a pair of inverterswith large transistors.

The driver must be able to supply enough current (must have enoughdriving capability) to achieve satisfactory rise and fall times (tr, tf ) fora given capacitive load.

In addition the driver must meet any required DC characteristicsregarding the levels of output voltages for a given load type, namely,CMOS or TTL.

A.P.Paplinski 1312


13.5 Bidirectional pads

In the AMI05 pad library there is a bidirectional pad that can also beused as a tri-state output pad or an input pad.

A logic diagram of the tri-state output pad is as follows:

OE OEB Dout P N PAD0 1 x 1 0 Z1 0 0 1 1 01 0 1 0 0 1

PAD =

Z if OE = 0Dout if OE = 1

The complete transistor level schematic of the bidirectional pad isshown below.

A.P.Paplinski 1313



Rev. APADBIDIR

Page3 of 4


Bi-Directional Pad Schematic PADBIDIR

OEOEB

OEB

OEB

OE OE

DataIn

DataInB

Pad

DataOut

EN

R=100

L='2

*l'

T14a

W='5

2*l'

L='2

*l'

M=6

T11

W='5

2*l'

L='2

*l'

M=6

T9

W='5

2*l'

L='3

*l'

M=6

TESD

P

W='1

00*l

'L=

'2*l

'

M=5

T4

W='5

2*l'

L='2

*l'

M=4

T2

W='5

2*l'

L='2

*l'

M=5

T1

W='5

2*l'

L='2

*l'

T13a

W='5

2*l'

BOND

ING PA

D

L='2

*l'

T14b

W='3

0*l'

L='2

*l'

M=6

T12

W='3

0*l'

L='2

*l'

M=6

T10

W='3

0*l'

L='3

*l'

TESD

N

W='1

00*l

'L=

'2*l

'

M=5

T6

W='3

0*l'

L='2

*l'

M=4

T5

W='3

0*l'

L='2

*l'

M=5

T3

W='3

0*l'

L='2

*l'

T13b

W='3

0*l'

A.P.Paplinski 1314


Figure 132: The output section of the bi-directional pad. 1. The complete layout.2. The polysilicon and metal1 layers. 3. The polysilicon and active layers

A.P.Paplinski 1315


Figure 133: The input section of the bi-directional pad. 1. The complete layout.2. The polysilicon and metal1 layers. 3. The polysilicon and active layers

A.P.Paplinski 1316

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