CMOS Transistor Mismatch Model valid fromWeak to Strong Inversion

Teresa Serrano-Gotarredona and Bernabé Linares-Barranco

Instituto de Microelectrónica de Sevilla, Ed. CICA, Av. Reina Mercedes s/n, 41012 Sevilla, SPAIN.

Phone: 34-954-5056666, Fax: 34-954-5056686, E-mail: bernabe@imse.cnm.es

AbstractA five parameter mismatch model continuos from weak

to strong inversion is presented. The model is an extensionof a previously reported one valid in the strong inversionregion [1]. A mismatch characterization of NMOS andPMOS transistors for 30 different geometries has beendone with this continuos model. The model is able topredict current mismatch with a mean relative error of13.5% in the weak inversion region and 5% in stronginversion. This is verified for 12 different curves,sweeping , and .

1. IntroductionCharacterization of transistor mismatch is crucial for

precision analog design. Using very reduced transistorgeometries produces large deviations in the transistorelectrical parameters. This may render the analog circuituseless due to unexpected large variations of the circuitspecifications. On the contrary, if too conservativetransistor geometries are used, the consequence is a wasteof area, that also produces an increase in circuitcapacitances. This may degrade the speed specificationsand increase the circuit power consumption. Thus, aprecise mismatch characterization as a function oftransistor area is necessary for optimizingarea-speed-power consumption in analog design.

Some works on statistical characterization have beenpreviously published in literature [1]-[3]. These works dostatistical characterization in the ohmic and/or saturationfor the strong inversion region of operation. However, aslow-power and low-voltage are becoming increasinglyimportant specifications in analog design, the analogdesign is moving towards the moderate and weakinversion regions of the transistor operation. Recently, amismatch model valid for all regions of operation hasbeen published [4]. However, relative errors in the weakinversion region of the order of 100% are reported. In thepresent work, we report a continuous 5-parametermismatch model valid for all regions of operation. Themodel predicts the current mismatch with a mean relativeerror of 13.5% in weak inversion and 5% in the stronginversion region. The maximum prediction error of ourmodel is less than 50% for all the operation regions, for12 different curves. NMOS and PMOS transistors of 30different geometries have been characterized. The modelis an extension of a previously reported 5-parametersmismatch model [1] to the weak inversion region.

2. Mismatch ModelTo generate a unique mismatch model valid in all

regions of operation, a transistor model continuos fromweak to strong inversion is necessary [5]-[6]. The presentmismatch model is based on the ACM transistor modelwhich is continuos for all regions of operations and isphysically based, so that it has a reduced number ofphysically meaningful parameters [6]. This makes thismodel especially suitable for transistor mismatchcharacterization. We have verified that very similarresults are obtained if the EKV model [5] is used.

In the ACM model, the current through the transistor is expressed as,

(1)

where , and are, respectively, the gate, sourceand drain voltages referred to the bulk. Parameter isthe thermal voltage; is the body factor; is Fermipotential; is mobility; is density of oxidecapacitance and and are the transistor width andlength, respectively.

The complete transistor model taking into accountsome second order effects relevant for mismatch andsmall transistor geometries, is

, (2)

where, in ohmic region;

in saturation.Parameter models the channel pinchoff, andparameters and model mobility degradation,velocity saturation and, drain and source seriesresistances [1]. The operator in equation (2) is asmoothed rectification function as shown in Fig. 1. Thefunction in Fig. 1 is continuos and has continuosderivative. It is defined as,

V G V DS V S

I DS

I DS I s i f V p V S–( ) ir V p V D–( )–( )=

V P V S D( )– φt 1 i f r( )+ 2– 1 i f r( )+ 1–( )ln+( )=

V P

V G V TO–

n------------------------=

n 1 γ

2 V G V TO 2φF γ 2φF+ +– 1 4⁄ γ2+ 1 2⁄ γ–( )

----------------------------------------------------------------------------------------------------------------------+=

I S I S'n µnC'oxW L⁄ φt2 2⁄= =

V G V S V D

φt

γ φF

µ C'ox

W L

I DS

I S i f ir–( ) 1 λ V D V S–( )+( )

1 θo V P V S–[ ] ++( ) 1 θeV DSeff

+( )------------------------------------------------------------------------------------=

V DSeffV DS=

V DSeffV P V S–[ ] +=

λθe θo

[ ] +

. (3)

However, in equation (2), a discontinuity in the derivativestill exits in the definition of . This problem can beeasily solved by expressing as the combination oftwo smoothed rectification operators,

. (4)

The extension of the smoothed region has beenempirically chosen to be a fraction of , namely,

.Our five parameter mismatch model, expresses the

current mismatch as a first order Taylor seriesexpansion of 5 mismatch parameters

,

, (5)

where the set of 5 mismatch parameterscharacterizes transistor

mismatch for any bias point.

3. Mismatch Characterization ResultsTo characterize the mismatch, arrays of 36 NMOS

transistors of 30 different geometries and arrays of 36PMOS transistors of 30 different geometries weremeasured accessing to a reduced number of pins [1]. Acell containing 30 different sized NMOS transistors and30 different sized PMOS transistors is arranged in amatrix.This characterization chip was fabricated in astandard CMOS technology. The 30 geometriescorrespond to 6 different widths and 5 different transistorlengths.

The transistor widths are: , , , , and .

The transistor lengths are: , , ,and .

For each transistor in the array, we measured 12different curves. In each curve, we swept voltagewhile keeping the other voltages constant. The 12different measured curves correspond to a twodimensional sweep of four values and three different

voltages. Each curve is measured with 101 datapoints for and varied in steps. The

12 measured curves correspond toand .

and voltages are referred to the local substrate.To extract the mismatch parameters, first the large

signal parameters have to beextracted in order to compute the partial derivatives ofequation (5). The large signal parameter extraction isdone using nonlinear curve fitting techniques.

To extract the mismatch parameters we compute thecurrent difference between two consecutivetransistors in the array. This way, we transform thearray of transistors into a array of transistor pairs.For each transistor pair, we fit the measured data for9 of the curves ( and

) to equation (5). From this fitting,we extract a unique set of 5 mismatch parameters

for each transistor pair. Notethat we have not used the 3 curves with duringthe extraction of the mismatch parameters. We have leftthese curves only for evaluation purposes.

For each transistor type (NMOS or PMOS) and foreach transistor size, we compute the five standarddeviations andthe 10 corresponding correlation terms.

The current mismatch can be predicted using themismatch parameters, through the theoretical equation,

(6)

Fig. 2 shows a comparison, for the 30 geometries ofNMOS transistors, between the measured currentmismatch (circles) and the current standard deviationcomputed using the extracted mismatch parameters andequation (6) (solid lines). Fig. 2(a) corresponds to therandom current standard deviations measured andcomputed for , while sweeping thegate voltage . Fig. 2(a) depicts 6 subfigures, one foreach transistor witdh. Each subfigure plots 5 curves, eachone corresponding to a different transistor length. Fig.2(b) corresponds to the random current standarddeviations measured and computed for ,

while sweeping the gate voltage .In Fig. 3, we show the error between measured and

predicted values (in %) for all 12 curves for NMOStransistors. In each subfigure, the errors are superimposedfor all sizes. The mean relative error is 8% in the weakinversion region and 4% in strong inversion.

Fig. 4 shows the errors (in %) between predicted andmeasured current mismatch. In each subfigure, the errorsobtained for the 30 PMOS transistor geometries aresuperimposed. The mean relative error, in this case, is13.5% in the weak inversion region and 5% in stronginversion. The maximum prediction error of the currentmismatch is less than 40% in the weak inversion regionand below 20% in the strong inversion region.

The current mismatch in Fig. 2, Fig. 3 and Fig. 4 iscomputed using the five standard deviations

and the 10possible correlation terms. However, only the three

−0.5 0 0.50

0.5

x

[x]+

E

E −E

Fig. 1. Smoothed rectification operator

x[ ] +

0 if x E–<x E+( )2

4E-------------------- if E– x E< <

x if x E>

=

V DSeffV DSeff

V DSeffV p V S–[ ] + V p V D–[ ] +–=

V DS

E 0.3V DS=

∆ I DS I DS⁄

∆ I S' I s'⁄ ∆γ ∆V TO ∆θe ∆θo, , , ,{ }

∆ I DS

I DS-------------

∆ I S'

I s'----------

1I DS---------

γ∂∂I DS∆γ 1

I DS---------

V TO∂∂I DS ∆V TO+ +=

V P V S–[ ] +

1 θo V P V S–[ ] ++

-------------------------------------------– ∆θo

V DSeff

1 θeV DSeff+

-------------------------------∆θe–

∆ I S' I s'⁄ ∆γ ∆V TO ∆θe ∆θo, , , ,{ }

6 6×

0.35µm

40µm 20µm 10µm 5µm2µm 0.8µm

10µm 5µm 2µm 0.8µm0.35µm

V G

V S

V DS

V G 0 3.3V[ , ]∈ 0.033V

V S 0V 0.5V 1V 1.5V, ,{ , }= V DS 0.1V 0.7V 1.3V,{ , }= V G

V S

I s' γ φF V TO θe θo λ, , , , ,{ , }

∆I6 6×

5 6×∆I I⁄

V S 0V 0.5V 1V,{ , }=V DS 0.1V 0.7V 1.3V,{ , }=

∆ I S' I s'⁄ ∆γ ∆V TO ∆θe ∆θo, , , ,{ }V S 1.5V=

σ ∆I s' I s'⁄( ) σ ∆γ( ) σ ∆V TO( ) σ ∆θe( ) σ ∆θo( ), , , ,{ }

σ2 ∆II

------ σ2

∆ I s'

I S'---------

1I---

γ∂∂I

2

σ2 ∆γ( ) 1I---

V TO∂∂I

2σ2 ∆V TO( )+ +=

1I---

θo∂∂I

2σ2 ∆θo( ) 1

I---

θe∂∂I

2σ2 ∆θe( ) correlation terms+ +

V S 0.5V= V DS 0.1V=V G

V S 0.5V=V DS 1.3V= V G

σ I s I s⁄∆( ) σ γ∆( ) σ V TO∆( ) σ θe∆( ) σ θo∆( ), , , ,{ }

correlations , andare relevant for the NMOS transistor mismatch. For thePMOS transistors we find correlation is alsoimportant. Fig. 5 depicts the mismatch parameters

obtained for theNMOS transistors of the 30 different geometries. In Fig.6, we draw the mismatch parameters

for the PMOStransistors of the 30 different geometries.

4. ConclusionsThis paper presents a 5 parameter mismatch model

valid for all regions of operation. The model is based on atransistor model continous from weak to strong inversion[5]-[6] and a previously reported mismatch model for the

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Fig. 3. Errors (in %) between the measured and computed current random standard deviation for the 30 geometriesof NMOS transistors. Each subfigure corresponds to one of the 12 curves and

.V S 0V 0.5V 1V 1.5V, , ,{ }=

V DS 0.1V 0.7V 1.3V, ,{ }=

VS=0V, VDS=0.1V

VS=0V, VDS=0.7V

VS=0.5V, VDS=0.1V

VS=0.5V, VDS=0.7V

VS=0.5V, VDS=1.3V

VS=1V, VDS=0.1V

VS=1V, VDS=1.3V

(σmeas-σcomp)/σmeas (%)

VG (V) VG (V)VG (V)

VS=1.5V, VDS=0.7V

VS=1.5V, VDS=1.3V

VG (V)

VS=0V, VDS=1.3V

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Fig. 4. Errors (in %) between the measured and computed current random standard deviation for the 30 geometries ofPMOS transistors. Each subfigure corresponds to one of the 12 curves and

.V S 0V 0.5V 1V 1.5V, , ,{ }=

V DS 0.1V 0.7V 1.3V, ,{ }=

VS=0V, VDS=0.1V

VS=0V, VDS=0.7V

VS=0V, VDS=1.3V

VS=0.5V, VDS=0.1V

VS=0.5V, VDS=0.7V

VS=0.5V, VDS=1.3V

VS=1V, VDS=0.1V

VS=1V, VDS=0.7V

VS=1V, VDS=1.3V

(σmeas-σcomp)/σmeas (%)

VG (V) VG (V)VG (V)

VS=1.5V, VDS=0.1V

VS=1.5V, VDS=0.7V

VS=1.5V, VDS=1.3V

VG (V)

r I s I s⁄∆ θe∆,( ) r I s I s⁄∆ θo∆,( ) r θe∆ θo∆,( )

r ∆γ ∆V TO,( )

σ ∆I s I s⁄( ) σ ∆γ( ) σ ∆V TO( ) σ ∆θe( ) σ ∆θo( ), , , ,

σ ∆I s I s⁄( ) σ ∆γ( ) σ ∆V TO( ) σ ∆θe( ) σ ∆θo( ), , , ,

strong inversion region. This is, to our knowlegde, thefirst mismatch model published in literature able topredict the current mismatch with mean error less than13.5% in all the transistor operation regions, and for sucha wide range of transistor curves and geometries.

5. References[1]T. Serrano-Gotarredona and B. Linares-Barranco,

“Systematic Width-and Length Dependent CMOSTransistor Mismatch Characterization andSimulation,” Analog Integrated Circuits and SignalProcessing, vol 21, pp. 271-296, Kluwer AcademicPublishers, 1999.

[2]M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G.Welbers, “Matching Properties of MOS Transistors,”IEEE Journal of Solid State Circuits, vol. 24, No. 5, pp.1433-1440, 1989.

[3]J. Bastos, Characterization of MOS TransistorMismatch for Analog Design, Ph. D. Dissertation,Katholieke Universiteit Leuven, 1998.

[4]J. Croon, M. Rosmeulen, S. Decoutere, and W. Sansen,“An Easy-to-Use Mismatch Model for the MOSTransistor,” IEEE Journal of Solid State Circuits, vol.37, No. 8, pp. 1056-1064, August, 2002.

[5]C.C. Enz, F. Krummernacher and E. A. Vittoz, “AnAnalytical MOS Transistor Model Valid for All

Regions of Operation and Dedicated to Low-VoltageLow-Current Applications,” Analog IntegratedCircuits and Signal Processing Journal, vol. 8, pp83-114, July 1995.

[6]C. Galup-Montoro, M. C. Schneider and A. I. A.Cunha, “A Current-Based MOSFET Model forIntegrated Circuit Design”, Chapter 2 inLow-Voltage/Low-Power Integrated Circuits andSystems, edited by E. Sanchez-Sinencio and A. G.Andreou, IEEE Press, August 1998.

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(a)

(b)

w=40µm w=20µm w=10µm

w=5µm w=2µm w=0.8µm

w=40µm w=20µm w=10µm

w=5µm w=2µm w=0.8µm

σ(∆I/I)(%)

σ(∆I/I)(%)

VG (V) VG (V)VG (V)

VG (V) VG (V)VG (V)

VG (V) VG (V)VG (V)

VG (V) VG (V)VG (V)

Fig. 2. Comparison between the measured and computedcurrent random standard deviation for the 30 differentsizes of NMOS transistors. (a) Curve ,

, and (b) curve ,V s 0.5V=

V DS 0.1V= V s 0.5V= V DS 1.3V=

0.5 1 1.5 2 2.5

x 106

0.005

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0.015

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x 106

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* w=40µmw=20µmw=10µmw=5µmw=2µmw=0.8µm

σ(∆Is/Is)

1/L (µm-1)

σ(∆γ)

σ(∆VTO)1/L (µm-1)

1/L (µm-1)

σ(∆θo)

1/L (µm-1)1/L (µm-1)

Fig. 5. Mismatch parameters for all the geometries ofNMOS transistors

σ(∆θe)

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σ(∆Is/Is)

1/L (µm-1)

σ(∆γ)

σ(∆VTO)1/L (µm-1)

1/L (µm-1)

σ(∆θe) σ(∆θo)

1/L (µm-1)1/L (µm-1)

Fig. 6. Mismatch parameters extracted for all thegeometries of PMOS transistors