CMOS Tech Loose Mod

7/29/2019 CMOS Tech Loose Mod

1/17

CMOS - 1

CMOS Detector Technology

Alan HoffmanRaytheon Vision Systems

Scientific Detector Workshop, Sicily 2005

Markus Loose

Rockwell Scientific

Vyshnavi Suntharalingam

MIT Lincoln Laboratory
http://www.raytheon.com/http://www.rockwellscientific.com/index.html


2/17

CMOS - 2

General CMOS Detector Concept

CCD Approach CMOS Approach

Pixel

Charge generation &charge integration

Charge generation,

charge integration &charge-to-voltage conversion

+

PhotodiodePhotodiode Ampl i f ier

Array ReadoutCharge transfer

from pixel to pixel

Multiplexing of

pixel voltages:

Successively

connect amplifiers

to common bus

Sensor OutputOutput amplifier performs

charge-to-voltage conversion

Various options possible:

- no further circuitry (analog out)

- add. amplifiers (analog output)

- A/D conversion (digital output)


3/17

CMOS - 3

Common CMOS Features

CMOS sensors/multiplexers utilize the same process as modern

microchips Many foundries available worldwide

Cost efficient

Latest processes available down to 0.13 m

Electronic shutter (snapshot, rolling shutter, non-destructive reads) No mechanical shutter required

CMOS process enables integration of many additional features

Various pixel circuits from 3 transistors up to many 100 transistors per pixel

Random pixel access, windowing, subsampling and binning

Bias generation (DACs)

Analog signal processing (e.g. CDS, programmable gain, noise filter)

A/D conversion

Logic (timing control, digital signal processing, etc.)

Low power consumption

Radiation tolerant (by process and by design)


4/17

CMOS - 4

Astronomy Application: Guiding

Special windowing can be used to

perform full-field science integration inparallel with fast window reads.

Simultaneous guide operation and science

data capture within the same detector.

Full field row Window Full field row

Full field row

Window Window

Full field row Full field row

Two methods possible:

Interleaved reading of full-field and window

No scanning restrictions or crosstalk issues

Overhead reduces full-field frame rate

Parallel reading of full-field and window

Requires additional output channel

Parallel read may cause crosstalk or conflict

No overhead maintains maximum full-fieldframe rate


5/17

CMOS - 5

Stitching Enables Large Sensor Arrays

array

horiscan1

horiscan2

V

3

V

2

V

1

array array array

array array array

array array array

horiscan1 horiscan2

V

3

V

2

V

1

The small feature size of modern CMOS processes limits the maximum

area that can be exposed in one step (so-called reticle) to about 22 mm. However, larger chips can produced by breaking up the design into

smaller sub-blocks that fit into the reticle.

Sub-blocks are exposed one afteranother

Some blocks are used multiple

times Ultimate limit is given by wafer size

Reticle

St i tched CMOS Senso r

22mm


6/17

CMOS - 6

Monolithic CMOS

Reset

Select

SF

PD

Read Bus

Read Bus

Select

SFPinned PD

Reset

p-sub

n+n+p+

TG

A monolithic CMOS image sensor combines the photodiode and the

readout circuitry in one piece of silicon

Photodiode and transistors share the area => less than 100% fill factor

Small pixels and large arrays can be produced at low cost => consumer

3T Pixel

4T Pixel

applications (digital cameras, cell phones, etc.)

photodiode transistors


7/17CMOS - 7

Complete Imaging Systems-on-a-Chip

Monolithic CMOS technology has enabled highly integrated,complete imaging systems-on-a-chip:

Single chip cameras for video and digital still photography Performance has significantly improved over last decade and is

better or comparable to CCDs for many applications.

Especially suited for high frame rate sensors (> Gigapixel/s) orother special features (windowing, high dynamic range, etc.)

2 Mpixel HDTV CMOS Sensor

Quantum Efficiency of a CMOS sensor

Si PINNIR AR coating

Si PINUV AR coating

3T pixelw/ microlenses

However, monolithic CMOS is still limited with respect toquantum efficiency:

Photodiode is relatively shallow=> low red response

Metal and dielectric layers ontop of the diode absorb orreflect light=> low overall QE

Backside illumination possible,but requires modification of

CMOS process

photodiode

Microlenses increase fill factor:


8/17CMOS - 8

Sensor Chip Assembly (SCA) Structure:

Hybrid of Detector Array and ROIC Connected by Indium Bumps

Mature interconnect technique:

Over 4,000,000 indium bumps per SCA demonstrated99.9% interconnect yield

Silicon Readout Integrated Circuit (ROIC)

Indium bump

Detector Array

16,000,000

Also called a Focal Plane Array (FPA) or Hybrid Array

Detector Array


9/17CMOS - 9

CMOS SCA Revolution

Large CMOS hybrids revolutionized infrared astronomy

Growth in size has followed "Moore's Law" for over 20 years

18 month doubling time

1E+02

1E+03

1E+04

1E+05

1E+06

1E+07

1E+08

1E+09

1980 1985 1990 1995 2000 2005 2010

Year First used in Astronomy

Numbero

fPixelsperArr

ay

MWIR arrays

Moore's law with 18 month doubling time

predicted


10/17CMOS - 10

Three Most Common Input Circuits

for CMOS ROICs

Circuit

SFD

(Source Follower per

Detector)

also called "Self

Integrator"

CTIA

(Capacitance

Transimpedance

Amplifier)

DI(Direct Injection)

Advantages

simple

low noise

low FET glow

low power

very linear

gain determined by

ROIC design (Cfb)

detector bias remains

constant

large well capacity gain determined by

ROIC design (Cint)

detector bias remains

constant

low FET glow

low power

Disadvantages

gain fixed by detector

and ROIC input

capacitance

detector bias changes

during integration

some nonlinearity

more complex circuit

FET glow

higher power

poor performance at

low flux

Comments

Most common

circuit in IR

astronomy

Very high gains

demonstrated

Standard

circuit for high

flux


11/17CMOS - 11

Temperature and Wavelengths of

High Performance Detector Materials

Si:As IBC

Si PIN

InSb

InGaAs

SWIR HgCdTe

LWIRHgCdTe

MWIR HgCdTe

Approximate detector temperatures for dark currents


12/17CMOS - 12

Detector Material Choices for CMOS Hybrid Arrays

Detector

Material

Si PIN

InGaAs

HgCdTe:

1.7m2.5 m5.2 m10 m

InSb

Si:As IBC

(BIB)

Spectral

Range*, m0.4 1.0

0.9** 1.7

0.9** 1.7

0.9** 2.5

0.9** 5.2

5 10

0.4 5.2

5 28

* Long wave cutoff is defined as 50% QE point

** Spectral range can be extended into visible range by removing substrate

*** Approximate detector temperatures for dark currents


13/17CMOS - 13

CCD CMOS

> 35 years of evolution

Trailing edge fabs

Economics of scale accelerate progress

Lower fabrication cost, Foundry access

High resistivity (deep depletion) substrates

Controlled temperature ramps & stress control

Epi doping optimized for digital CMOS

Scalable to 300mm

Buried channel

Multiple oxidation cycles

Complex implant engineering

Rapid Thermal Processing (RTP)

Single gate dielectric thickness Multiple gate dielectric thicknesses

Doped polysilicon (single type)Complementarily doped polysilicon

Silicided polysilicon and FET source/drain

Highly nonplanar surfaces

Conservative design rules

Fine-line patterning

Multiple metal layers (dense routing)

Vulnerable to space-radiation-induced trapsHighly suitable for long-term space-based

applications

Process Comparison

Stacked via to poly2m

180-nm SRAM cell2m 2m

Four-Poly OTCCD


14/17CMOS - 14

RST

ROW

OUT

VDD

photodiode

Pixel Layout

p-epi

n-Wellp-well

Field Oxide

VDD

p+

ROW

OUT

n+

p+ Substrate

RST

Limitations of Standard Bulk CMOS APS

Fill factor tradeoff

Photodetector and pixel transistors sharesame area

PD from Drain-Substrate or Well-Substratediode

Low photoresponsivity

Shallow, heavily doped junctions

Limited depletion depth Absorption and reflection in poly, metal, andoxide layers

Surface recombination at Si/SiO2 interface

QE*FF > 60% is good, many < 20%

High leakage

LOCOS/STI, salicide Transistor short channel effects

Substrate bounce and transient couplingeffects


15/17CMOS - 15

Conventional Monolithic APS 3-D Pixel

pixel

Addressing

A/D, CDS,

Addressing

LightPD

3T

pixel

PD

ROIC

Processor

Advantages of Vertical Integration

Pixel electronics and detectors

share area

Fill factor loss Co-optimized fabrication

Control and support electronics

placed outside of imaging area

100% fill factor detector

Fabrication optimized by

layer function Local image processing

Power and noise

management

Scalable to large-area focal

planes


16/17CMOS - 16

Approaches to 3D Integration

10 m

Bump Bond used to

flip-chip interconnect

two circuit layers

Two-layer stack using

Lincolns SOI-based viasTwo-layer stack with

insulated vias through

thinned bulk Si

10 mPhoto Courtesy of RTI

3D-Vias

Tier-1

Tier-2

(To Scale)

10 m3D-Vias


17/17C OS

Comparison CMOS vs. CCD for Astronomy

Property CCD Hybrid CMOS

Resolution > 4k x 4k 2k x 2k in use, 4k x 4k demonstrated

Pixel pitch 10 20 m 18 40 m, < 10 m demonstrated

Typ. wavelength

coverage

400 1000 nm 400 1000 nm with Si PIN

400 5000 nm with InSb or HgCdTe

Noise Few electrons Few electrons with multiple sampling

Shutter Mechanical Electronic, rolling shutter

Power Consumption High Typ. 10x lower than CCD

Radiation Sensitive Much less susceptible to radiation

Control Electronics High voltage clocks, at

least 2 chips needed

Low voltage only,

can be integrated into single chip

Special Modes Orthogonal Transfer,

Binning,

Adaptive Optics

Windowing, Guide Mode,

Random Access, Reference Pixels,

Large dynamic range (up the ramp)

Silicon PIN hybrid detectors have become a serious alternative to CCDs providing a

number of significant advantages, specifically for large mosaic focal plane arrays.

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CMOS Tech Loose Mod