CMOS Lecture2

8/10/2019 CMOS Lecture2

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CSET 4650Field Programmable Logic Devices

Dan Solarek

Introduction to CMOSComplementary Metal-OxideSemiconductor


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2

CMOS Logic Structures

Static logic circuitshold their outputvalues indefinitelyDynamic logiccircuits store theoutput in a capacitor,so it decays with timeunless it is refreshed.We will look at a fewof these structures


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Pass TransistorsTransistors can be used as switches

g

s d

g = 0s d

g = 1s d

0 strong 0

Input Output

1 degraded 1

g

s d

g = 0s d

g = 1s d

0 degraded 0

Input Output

strong 1

g = 1

g = 1

g = 0

g = 0


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Pass Transistor

Pass-transistor circuits are formed by dropping the PMOStransistors and using only NMOS pass transistorsIn this case, CMOS inverters (or other means) must be used

periodically to recover the full V DD level since the NMOS pass transistors will provide a V OH of V DD V Tn in somecasesThe pass transistor circuit requires complementary inputsand generates complementary outputs to pass on to the nextstage


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5

Pass Transistor

This figure shows a simpleXNOR implementationusing pass transistors:

If A is high, B is passedthrough the gate to theoutputIf A is low, -B is passedthrough the gate to theoutput


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Pass Transistor

At right,(a) is a 2-input NAND passtransistor circuit(b) is a 2-input NOR passtransistor circuit

Each circuit requires 8transistors, double thatrequired using conventional

CMOS realizations


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7

Pass Transistor

Pass-transistor logic gate can implement Boolean functions NOR, XOR, NAND, AND, and OR depending upon the P1-P4 inputs, as shown below.

P1,P2,P3,P4 = 0,0,0,1 gives F(A,B) = NORP1,P2,P3,P4 = 0,1,1,0 gives F(A,B) = XORP1,P2,P3,P4 = 0,1,1,1 gives F(A,B) = NANDP1,P2,P3,P4 = 1,0,0,0 gives F(A,B) = ANDP1,P2,P3,P4 = 1,1,1,0 gives F(A,B) = OR

Circuit can beoperated withclocked P pull-updevice or inverter-based latch


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Transmission Gates N-Channel MOS Transistors pass a 0 better than a 1

P-Channel MOS Transistors pass a 1 better than a 0

This is the reason that N-Channel transistors are used in the pull-downnetwork and P-Channel in the pull-up network of a CMOS gate.Otherwise the noise margin would be significantly reduced.


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Transmission GatesA transmission gate is a essentially a switch that connects two

points. In order to pass 0s and 1s equally well, a pair oftransistors (one N-Channel and one P-Channel) are used asshown below:

When s = 1 the two transistors conduct and connect x and yThe top transistor passes x when it is 1 and the bottom transistor passes xwhen it is 0

When s = 0 the two transistor are cut off disconnecting x and y


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10

Transmission GatesPass transistors produce degraded outputsTransmission gates pass both 0 and 1 well

g = 0, gb = 1a b

g = 1, gb = 0a b

0 strong 0

Input Output

1 strong 1

g

gb

a b

a bg

gb

a b

g

gb

a b

g

gb

g = 1, gb = 0

g = 1, gb = 0

symbols


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Transmission GatesImplementing XOR gates

With NAND gates and inverters:

With transmission gates:

Why would one of these circuits be preferable to the other?


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12

Transmission GatesImplementing a multiplexer with transmission gates:

When S = 0, input X1 is connected to the output YWhen S = 1, input X2 is connected to the output Y


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Dynamic Domino CMOS LogicOne technique to help decrease power in MOS logiccircuits is dynamic logicDynamic logic uses different precharge and

evaluation phases that are controlled by a systemclock to eliminate the dc current path in singlechannel logic circuitsEarly MOS logic required multiphase clocks toaccomplish this, but CMOS logic can be operateddynamically with a single clock


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Static NMOSTotem-Pole Output

as we have seen previously

Does not need to be refreshedWhich is why it is called static

PMOS Acts as ConstantCurrent Source for ActivePull-Up

Faster rise-times as compared tonon-CMOS implementations input

output

Vdd

ground


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Static CMOS

Complementary MOSExample of a 2-input

NAND gate

Input 1

Input 2

ground

VDD

output


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Dynamic NMOS

Output is 1 unlessdischarged

f 1 Charges Output

f 2 ConditionallyDischarges Output

input

ground

Vdd

output f1

f2


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Dynamic Domino CMOS LogicThe figure demonstrates the basic concept of dominoCMOS logic operation


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Simple Dynamic Domino Logic Circuit


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Dynamic Domino CMOS LogicDomino CMOS circuits only produce true logic outputsThis can be overcome by using registers that have both trueand complemented output to complete the function shown bythe following circuit:

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CMOS Lecture2