CSET 4650 Field Programmable Logic DevicesDan
SolarekIntroduction to CMOSComplementary Metal-Oxide
Semiconductor
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CMOS TechnologyComplementary MOS, or CMOS, needs both PMOS and
NMOS FET devices for their logic gates to be realizedThe concept of
CMOS was introduced in 1963 by Frank Wanlass and Chi-Tang Sah of
Fairchilddid not become common until the 1980s as NMOS
microprocessors were dissipating as much as 50W and alternative
design techniques were needed CMOS still dominates digital IC
design today
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MOSFET TransistorsMetal-Oxide-Semiconductor Field Effect
Transistors (MOSFETs) are the transistors most widely used in
integrated circuits todayThe name is due to:the structure of the
device - a sandwich of a metal conductor, an oxide insulator, and a
semiconductor substratethe way it works - an electric field
controls the flow of current through the deviceAlthough early
MOSFET transistors used metal for the first layer, current ones use
a polysilicon material a conductive material with somewhat more
resistance than a normal conductor and is easier to fabricate
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N-Channel MOSFET TransistorsWith no voltage between the gate
terminal and the substrate, there are two junctions between the two
N regions and the P region.This acts like two oppositely connected
diodes, and no current can flow between source and drain.
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N-Channel MOSFET TransistorsApplication of a positive voltage
between the gate terminal and the substrate creates an electric
field that drives holes out of the region under the gate, creating
a channel of N-type material that connects the source and drain
terminalsCurrent is due to electron movement in the N-channel
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P-Channel MOSFIT TransistorsThe P and N regions are reversed
from the N-Channel device.Application of a voltage on the gate
terminal that is negative relative to the substrate creates a P
channel beneath the gate and charge flow is due to hole
movement.
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MOSFET Circuit SymbolsThe following symbols are used to
represent MOSFET transistors in circuit diagrams:normally
onnormally off
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MOSFET Circuit SymbolsThe following simplified symbols are used
to represent MOSFET transistors in most CMOS circuit
diagrams:negative voltage
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MOSFET Circuit SymbolsThe gate of a MOS transistor controls the
flow of the current between the drain and the source.The MOS
transistor can be viewed as a simple ON/OFF switch.
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MOSFET Circuit SymbolsSeries behavior of MOS transistorsnMOS: 1
= ONpMOS: 0 = ON
Series: both must be ON
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MOSFET Circuit SymbolsParallel behavior of MOS transistorsnMOS:
1 = ONpMOS: 0 = ON
Parallel: either can be ON
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Complementary MOSFETS (CMOS)N-Channel and P-Channel transistors
can be fabricated on the same substrate as shown below
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CMOS Logic Families
CMOS Series
Prefix
Example
Original CMOS
40
4009
Pin compatible with TTL
74C
74H04
High-speed and pin compatible with TTL
74HC
74HC04
High-speed and electrically compatible with TTL
74HCT
74HCT04
Very High-speed and pin compatible with TTL
74VHC
74VHC04
Very High-speed and electrically compatible with TTL
74VHCT
74VHCT04
Advanced High-speed and pin compatible with TTL
74AHC
74AHC04
Advanced High-speed and electrically compatible with TTL
74AHCT
74AHCT04
Fast and electrically compatible with TTL
74FCT
74 FCT 04
Fast and electrically compatible with TTL with TTL VOH
74FCT-T
74 FCT04T
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CMOS Logic Families
74-series (commercial) parts are designed for temperatures
between 0C and 70C54-series (military) parts are designed for
operation between -55C and 125Cthe 00 NAND gate is the smallest
logic-design building block in each familythe 138 is a MSI part
(~15 NAND gates)
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CMOS Logic Families
These specs assume that the 5 Volt supply has a 10% margin; that
is, VCC can be anywhere between 4.5 and 5.5 V.
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CMOS Logic Families
Specifications for TTL-compatible CMOS outputs have two sets of
output parameters; only one set is used depending on how an output
is loaded.
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CMOS Logic Families
A CMOS load is one that requires the output to sink and source
very little DC current20 A for HC/HCT50 A for VHC/VHCTA TTL load
can consume much more sink and source currentup to 4 mA from and
HC/HCT output8 mA from a VHC/VHCT outputCMOS outputs maintain an
output voltage within 0.1V of the supply rails, 0 and VCC.a
worst-case VCC=4.5V is used for the table; hence, VOHminC=4.4V
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Comparison of Logic Levels(a) 5-V CMOS; (b) 5-V TTL, including
5-V TTL-compatible CMOS; (c) 3.3-V LVTTL; (d) 2.5-V CMOS; (e) 1.8-V
CMOS
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Properties of NMOS and CMOS Logic GatesNo current flows through
the gate unless the input signal is changingHigh input
impedanceHigh fan-outSandwich structure of MOS transistor creates
capacitor between the gate and substrateHigh input capacitanceSlows
transition timeLimits fan-out or switching speedNMOS dissipates
power in low output stateCMOS gate only dissipates power when it is
changing stateThe faster a CMOS gate switches the more power it
dissipates, so there is a tradeoff between speed and power
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Why CMOS is BetterLow DC Power ConsumptionAbrupt & well
defined Voltage transfer CharacteristicNoise Immunity due to Low
impedance between logic levels and Supply/Gnd.Symmetry between
Tfall & TriseHigh Density: Si real estate Yield CostHighly
Integrated Active & High input Impedance Composition equality
No real trade off between the above
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Static vs Dynamic CMOS DesignStaticEach gate output have a low
resistive path to either VDD or GNDDynamicRelies on storage of
signal the value in a capacitancerequires high impedance nodesWe
will only worry about static design today.
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NMOS LogicNegative charge carriers (electrons)Positive biasing
voltage at gate
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CMOS LogicTransistors come in complementary pairs
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CMOS InverterCMOS gates are built around the technology of the
basic CMOS inverter:SymbolCircuit
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Basic CMOS Logic TechnologyBased on the fundamental inverter
circuit at rightTransistors (two) are enhancement mode
MOSFETsN-Channel with its source groundedP-Channel with its source
connected to +VInput: gates connected togetherOutput: drains
connected
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CMOS Inverter - OperationWhen input A is grounded (logic 0), the
N-Channel MOSFET is unbiased, and therefore has no channel enhanced
within itself. It is an open circuit, and therefore leaves the
output line disconnected from ground.
At the same time, the P-Channel MOSFET is forward biased, so it
has a channel enhanced within itself, connecting the output line to
the +VDD supply. This pulls the output up to +VDD (logic
1).VDDA
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CMOS Inverter - OperationWhen input A is at +VDD (logic 1), the
P-channel MOSFET is off and the N-channel MOSFET is on, thus
pulling the output down to ground (logic 0). Thus, this circuit
correctly performs logic inversion, and at the same time provides
active pull-up and pull-down, according to the output
state.VDDA
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CMOS Inverter - OperationSince the gate is essentially an open
circuit it draws no current, and the output voltage will be equal
to either ground or to the power supply voltage, depending on which
transistor is conducting.VinVoutVDDVDDindeterminant range
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CMOS Inverter A Switch ModelCircuit schematic for a CMOS
inverterSimplified operation model with a high input
appliedSimplified operation model with a low input applied
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Static Characteristics of the CMOS Inverter Switch ModelThe
figure shows the two modes of static operation with the circuit and
simplified models Logic 1 (a) and (b)Logic 0 (c) and (d)Notice that
VH = 5V and VL = 0V, and that ID = 0A which means that there is no
static power dissipation
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CMOS Inverter OperationWhen vI is pulled high (VDD), the PMOS
inverter is turned off, while the NMOS is turned on pulling the
output down to GNDWhen vI is pulled low (GND), the NMOS inverter is
turned off, while the PMOS is turned on pulling the output up to
VDD
Summarizing:
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Propagation Delay EstimateThe two modes of capacitive
discharging and charging that contribute to propagation delay
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Fan-Out in CMOS CircuitsWhile the fan-out of CMOS gates is
affected by current limits, the fan-out of CMOS gates driving CMOS
gates is enormous since the input currents of CMOS gates is very
low.Why are the input currents low?On the other hand the high
capacitance of CMOS gate inputs means that the capacitive load on a
gate driving CMOS gates increases with fan-out.This increased
capacitance limits switching speeds and is a far more significant
limit on the maximum fan-out.
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Complementary CMOSComplementary CMOS logic gatespMOS pull-up
networknMOS pull-down networka.k.a. static CMOS
Pull-up OFFPull-up ONPull-down OFFZ (float)1Pull-down ON0X
(crowbar)
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Complementary CMOSTo build a logic gate we need to build two
switch networks:
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Conduction ComplementComplementary CMOS gates always produce 0
or 1Ex: NAND gateSeries nMOS: Y=0 when both inputs are 1Thus Y=1
when either input is 0Requires parallel pMOSRule of Conduction
ComplementsPull-up network is complement of pull-downparallel
series, series parallel
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CMOS Gate DesignWork out the values for both the push and pull
networksCompare themWhat is the result?
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CMOS Gate DesignA 2-input CMOS NAND gate
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CMOS Gate DesignWork out the values for both the push and pull
networksCompare themWhat is the result?
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CMOS Gate DesignA 2-input CMOS NOR gate
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CMOS Gate DesignA 4-input CMOS NOR gate
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NAND and NOR are PopularLogical inversion comes free as a result
an inverting gate needs smaller number of transistors compared to
the non-inverting oneIn CMOS (and in most other logic families) the
simples gates are invertersthe next simplest are NAND and NOR
gates
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Compound GatesLets take a look at a gate that implements a more
complex function
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Compound GatesCompound gates can do any inverting functionEx:
DCBAY+=
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Example: O3AI
For additional information, contact any of the following
individuals:
Dan SolarekProfessor and
[email protected]@eng.utoledo.eduVoice:
419-530-3377
Allen RiouxDirector of Online
[email protected]@utnet.utoledo.eduVoice:
419-530-3377
To leave a message for any of these individuals call the
department secretary at 419-530-3159. You may send a FAX to
419-530-3068
Richard SpringmanDirector of Student
[email protected]@eng.utoledo.eduVoice:
419-530-3276
Myrna SwanbergAcademic Program
[email protected]@eng.utoledo.eduVoice:
419-530-3062Reference:
http://www.play-hookey.com/digital/electronics/cmos_gates.html
Reference:
http://www.play-hookey.com/digital/electronics/cmos_gates.html
Reference:
http://www.play-hookey.com/digital/electronics/cmos_gates.html
Reference:
http://www.play-hookey.com/digital/electronics/cmos_gates.html
