44
2013/9/4 1 Yuan Taur Electrical & Computer Engineering University of California, San Diego CMOS Device ScalingPast, Present, and Future

CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

  • Upload
    others

  • View
    1

  • Download
    0

Embed Size (px)

Citation preview

Page 1: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

2013/9/4 1

Yuan Taur

Electrical & Computer Engineering

University of California, San Diego

CMOS Device Scaling—

Past, Present, and Future

Page 2: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

2013/9/4 2

Outline

How short can a MOSFET be?

Early Short-Channel Models (1970s-1980s)

Charge sharing model.

Polynomial potential models.

Solving 2D Poisson’s equation analytically (1980s-1990s)

In silicon only.

In silicon and in SiO2.

Two-region, three-region scale length models (1990s-2000s)

Bulk CMOS.

Double-gate MOSFET, Nanowire MOSFET.

Projecting scaling limits.

The part on bulk MOSFET follows “Review and Critique of Analytic Models of MOSFET Short-Channel

Effects in Subthreshold,” Qian Xie, Jun Xu, and Yuan Taur, IEEE Transaction on Electron Devices, 2012.

Page 3: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 3

History of transistors and VLSI

Page 4: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 4

MOSFET Schematic

From “Guide to State-of-the-Art Electron

Devices,” IEEE Press/Wiley, 2013.

Can be turned on

with no conduction

current in silicon.

Page 5: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 5

MOSFET Scaling

Currents scale as 1/; Capacitances scale as 1/.

Gate delay scales as 1/.

Power per circuit scales as 1/ .2

Dennard et al., 1974

But no specific relation

of Lg to other device

parameters.

Page 6: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

2013/9/4 6

If L ,

and , delay CV/I . But

I I CW

L

V V

mds dsat eff ox

g t

( )2

2

C WLCg ox2

3

When the channel length is

too short, the drain begins to

gain control of the barrier,

thus losing transistor action. source

gate-controlled

barrier

drain

Why Short Channel? How short?

Short-channel threshold voltage roll-off.

Drain Induced Barrier Lowering (DIBL).

Page 7: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 7

Short-Channel Vt Roll-off

DIBL

Degradation of subthreshold

slope.

Page 8: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 8

2D potential contours

(Same gate voltage)

Long channel Short channel

Page 9: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 9

Charge Sharing Model

n+ DrainWdm

L

tox

Gate

L

n+ Source

p-type Substrate

+ + + ++

+

+++++

+

+ + + +

Gate

oxide

xj

(Yau, SSE 1974)

1

2112

j

dmj

ox

dmaBfbt

x

W

L

x

C

WqNVV

• First to point out the importance of max. gate depletion depth Wdm.

• But, rather arbitrary partition of charge with no tox dependence.

• Difficult to deal with high drain bias.

Fixed

depletion

charge

Fixed

depletion

charge

Page 10: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 10

Polynomial Potential Models

sourcen+ drainn+

Gate

p-type substrate

x

y0 L

Wdm

tox

Na

Vgs

Vds

Vbs

(Toyabi and Asai, TED 1979)

a

si

Nq

yx

2

2

2

2

3

3

2

210 )()()()(),( xyaxyaxyayayx

),0(),0( yx

tVyVVox

sioxoxfbgs

bsdm VyW ),( 0),(

yW

xdm

Assume the solution to 2D

Poisson’s eq. in subthreshold

is of the form

Boundary condition at the Si-oxide interface: Continuity of vertical displacement,

Boundary conditions at the bottom of depletion region: Constant potential, zero field,

Page 11: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 11

Polynomial Potential Models

sourcen+ drainn+

Gate

p-type substrate

x

y0 L

Wdm

tox

Na

Vgs

Vds

Vbs

Using the 3 BC’s and the Poisson’s

eq., one obtains an ordinary

differential eq. for the surface

potential, s(y) = a0(y),

where

With the source and drain boundary conditions, s(0) = bi and s(L) = bi + Vds,

s has a minimum value (maximum energy barrier for electrons),

0

2

02

2

)/2( Aldy

dsa

s

dm

oxsidmox

oxsia W

tW

tl

32

20

1

/)(2

1

/2

100 )()()( AeAVeAy aa lLy

dsbi

ly

bis

1

/

11min0))((2 AeAVA alL

dsbibi

Page 12: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 12

Polynomial Potential Models

The L-dependent term of min describes SCE.

For SCE to be negligible (< 100 mV), Lmin ~ 3l0a.

l0a is called the “scale length”.

dm

oxsidmox

oxsia W

tW

tl

32

20

1

/

11min0))((2 AeAVA alL

dsbibi

• The first introduction of exponential SCE and “scale length” concept.

However, l0a is clearly incorrect because it is independent of tox in the limit

of thick tox.

• The polynomial (x,y) satisfies the 2D Poisson’s eq. only at x = 0, not the

region below the interface.

• The boundary condition at x = 0 is for long-channel MOSFETs which

implicitly assumes 2/x2 = 0 in the oxide, i.e., 1D Poisson’s eq.,

inconsistent with the 2D fields in Si.

Page 13: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 13

Other Polynomial Potential Models

• Yan et al., TED 1992:

Assumed a parabolic potential with constant potential at the bottom

boundary (field 0).

But same problem as Toyabe and Asai, l0b is independent of tox in the limit of

thick tox.

• Liu et al. TED 1993 (later BSIM3):

Assumed zero field at the bottom boundary with no restriction on potential

at x = Wdm.

Disqualifies as a predictive scale length as it all hinges on the fitting

parameter h.

dm

oxsidmox

oxsib W

tW

tl

20

ox

dmoxsic

Wtl

h

20

Page 14: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 14

Solving 2D Poisson’s eq. in silicon

• Ratnakumar and Meindl, JSSC 1982

Top: (mostly constant)

Bottom: (zero field)

Left:

Right:

)(),0( yy s

0),(

yW

xd

bix )0,(

dsbi VLx ),(

0

2

02

)12(sinh

2

)()12(sinh

2

)12(sinh

2

)12(sin

1),(n d

n

d

n

d

d

d

sW

ynB

W

yLnA

W

Ln

W

xn

W

xyx

a

si

Nq

yx

2

2

2

2

Scale length: l0d = 4Wdm/.

Key problem: Top boundary condition is conductor-like.

Long

channel

term

Satisfies 2D Poisson’s eq. at every (x, y).

Page 15: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 15

Solving 2D Poisson’s eq. in silicon

• Poole and Kwong, EDL 1984

Changed the top condition to:

Continuation of vertical displacement at

Si-SiO2 interface.

a

si

Nq

yx

2

2

2

2

Eigenvalue eq. from the top boundary condition:

where SCE ~ exp(L/l0e) with l0e = 2/g0 (longest).

Scale length, thin oxide: l0e = 4Wdm/, thick oxide:

),0(),0( yx

tVyVVox

sioxoxfbgs

ox

dmoxsie

Wtl

20

noxsi

oxdn

tW

g

g )tan(

0

2

0 sinh)(sinhsinh

)(cos1),(

n

nnnn

n

dn

d

s yDyLCL

Wx

W

xyx gg

g

g

Page 16: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 16

Two Issues: Top and Bottom BC

• A popular top boundary condition:

Continuation of vertical displacement at

Si-SiO2 interface.

But, it implicitly assumes constant vertical field in the oxide, i.e., 2/x2 = 0.

Lateral field will not be continuous at the Si-SiO2 interface if 2D in Si but 1D

in oxide.

Must solve 2D eq., 2/x2 + 2/y2 = 0, in both Si and SiO2.

),0(),0(

yxt

yVVsi

ox

fbgs

ox

Page 17: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 17

Two Issues: Top and Bottom BC

• Bottom boundary condition:

Zero field or

constant potential?

• 1D depletion approximation,

uniform doping:

both zero field and constant potential.

• But for 2D, must make a choice. If zero

field, then potential is not constrained. If

constant potential, then field may not be 0.

• Must choose constant potential because

field may not be continuous at x = Wdm, but

potential must be continuous everywhere.

0),(

yW

xdm

bsdm VyW ),(

Extreme retrograde

doped channel:

Page 18: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 18

Gate

DrainSourceH G L y

A

B C D E

F

-toxn+poly

Nan+ n+

xSubstrate

0

Wd

Boundary conditions:

Top: GH,

Left: AB,

Right: EF,

Bottom: CD.

( , ) 3t y V Vox g fb

( , )x bi0

( , )x L Vbi ds

( , )W yd 0

To eliminate the boundary condition

at the Si/oxide interface, the oxide

region is replaced by an equivalent

Si region (si/ox)tox 3tox thick.

In AFGH

(oxide),

In ABEF

(silicon),

2

2

2

2 0x y

2

2

2

2x y

qNa

si

One region scale length

Solving 2D Poisson’s eq. in silicon and oxide

Nguyen and Plummer, IEDM 1981.

In subthreshold,

Page 19: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 19

General approach to a 2-D boundary value problem

Let:

v(x,y) is a solution to the inhomogeneous equation (with Na) and

satisfies the top boundary condition.

uL, uR, uB are solutions to the homogeneous equation such that

(x,y) satisfies the other B.C.’s.

( , ) ( , ) ( , ) ( , ) ( , )x y v x y u x y u x y u x yL R B

Gate

DrainSourceH G L y

A

B C D E

F

-toxn+poly

Nan+ n+

xSubstrate

0

Wd

Superposition

uL = 0 on top, bottom, right; uR = 0 on top, bottom, left; etc.

Page 20: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 20

1 3

)3(sin

3sinh

3sinh

),( n oxd

ox

oxd

oxd

nRtW

txn

tW

Ln

tW

yn

cyxu

Gate

DrainSourceH G L y

A

B C D E

F

-toxn+poly

Nan+ n+

xSubstrate

0

Wd

For satisfying the

Boundary conditions:

Note that for u=sin(kx),

d2u/dx2=-k2u;

And that for u=sinh(ky),

d2u/dy2=k2u.

1 3

)3(sin

3sinh

3

)(sinh

),( n oxd

ox

oxd

oxd

nLtW

txn

tW

Ln

tW

yLn

byxu

1

sin)3(

sinh

)3(sinh

),( n oxd

ox

nBL

yn

L

tWn

L

txn

dyxu

uL = 0 on top, bottom, right; uR = 0 on top, bottom, left; etc.

y = 0 y = L

Page 21: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 21

Approximate 2-D Solution of Potential

Neglect uB and higher order terms in uL, uR:

oxd

ox

oxd

oxdoxd

d

stW

tx

tW

L

tW

yc

tW

yLb

W

xyx

3

)3(sin

3sinh

3sinh

3

)(sinh

1),(

112

oxd

oxtW

L

sctW

tecby oxd

3

)3(sin2),0(

3

2/

11

source

gate-controlled

barrier

drain

For x = 0, apply sinh z ez/2 and u + v 2(uv)1/2, the surface potential has a

minimum at y = yc:

SCE ~ exp(L/l0g),

Scale length:

Lmin 3l0g (Note: b1 bi, c1 bi + Vds)

ox

ox

sidmg tWl

20

Long channel

Page 22: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 22

One region scale length model

The scale length is given by the sum of Wdm and (si/ox)tox.

Valid for tox << Wdm so vertical field dominates in oxide.

Must reduce both Wdm (by higher doping) and tox to scale to shorter

gate lengths.

tox cannot scale much below 1 nm because of tunneling. The industry

went to high- insulators.

However, high- insulators can be physically thick. The one-region

model based on vertical fields is no longer correct.

Both the lateral and the vertical fields must be taken into

consideration two-region scale length model.

It is not only i/ti (vertical field), but also ti (lateral field).

ox

ox

sidmg tWl

20

Page 23: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 23

Two-Region Scale Length

Source Drain

Gate

Body

ti

Wd

L

si

i

1

2

D. Frank et al., EDL 10/98

In the one-region model,

the eigenvalues are:

For two regions, assume

the eigenvalues are kn.

for ti ≤ x ≤ 0,

for 0 ≤ x ≤ Wdm.

oxd

ntW

nk

3

1

111 )(sin

sinh

sinh)(sinh),(

n

in

n

nnnn txkLk

ykcyLkbyxu

1

222 )(sin

sinh

sinh)(sinh),(

n

dmn

n

nnnn WxkLk

ykcyLkbyxu

Note that u1 = 0 at the top (x = ti) while u2 = 0 at the bottom (x = Wdm).

Page 24: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 24

Two-Region Scale Length

Source Drain

Gate

Body

ti

Wd

L

si

i

1

2

D. Frank et al., EDL 10/98

),0(),0( 21 yuyu

),0(),0( 21 yx

uy

x

usii

At the interface (x = 0),

match potential,

and normal displacement,

(Tangential field matched

if potential matched.)

0tan1

tan1

dmn

si

in

i

Wktk

Every term must match since the BCs apply for any y. For nontrivial solutions, obtain

eigenvalue eq.:

(same eq. from cn1, cn2.)

1

2

1

1 )sin()(sinh)sin)(sinh n

dmnnn

n

innn WkyLkbtkyLkb

1

2

1

1 )cos()(sinh)cos)(sinh n

dmnnsinn

n

inninn WkkyLkbtkkyLkb

Page 25: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 25

Example: Two-Region

0tan1

tan1

dmn

si

in

i

Wktk

For si =11.70, i =7.80, ti =5.0 nm, and Wdm =10.0 nm,

k1 = 0.20 nm-1, k2 = 0.43 nm-1,

k3 = 0.63 nm-1,

Each SCE term exp(knL/2).

k1 term dominates.

Define l0i = 2/k1 so SCE exp(L/l0i)

and Lmin 3l0i.

Note that

5.31~2exp

2exp

min2

min1

Lk

Lk

02

tan12

tan1

00

i

dm

sii

i

i l

W

l

t

k1 k2 k3

kn

An infinite number of discrete,

irregularly spaced eigenvalues kn.

Page 26: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 26

Two-Region Scale Length

Lowest eigenvalue:

Note that:

l0i (2/)Wdm or (2/)ti,

whichever is longer.

If ti=Wdm, l0i=(4/)Wdm =

(4/)ti, regardless of i, si.

If i=si, l0i=(2/)[Wdm+ti],

the total height of box.

If ti<<Wdm, l0i (2/)[Wdm

+ (si/i)ti] (dotted line),

back to the one-region l0g.

02

tan12

tan1

00

i

dm

sii

i

i l

W

l

t

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

Normalized Si Depletion Depth,

No

rmali

ze

d G

ate

In

su

lato

r T

hic

kn

es

s,

10

31

/ =i si

1/3 (SiO )2

W /d

t /i

(2/)(Wdm/l0i)

(2/)(ti/l0i)

In general, requires ti < ( /4)l0i or Lmin/4, even if i >>si.

Page 27: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 27

Graphical Method

Previous example, si =11.70, i =7.80, ti =5.0 nm, and Wdm =10.0 nm.

Draw a straight line

with slope ti/Wdm

(=1/2) through (0, 0).

Interpolate the i/si

(=2/3) value between

the curves.

Read off (2/)(Wdm/l0i)

(=0.63).

Obtain l0i = 10 nm.

Lmin 3l0i = 30 nm.

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

Normalized Si Depletion Depth,

No

rmalized

Gate

In

su

lato

r T

hic

kn

ess,

10

31

/ =i si

1/3 (SiO )2

(2/)(ti/l0i)

(2/)(Wdm/l0i)

Page 28: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 28

Verification by 2-D simulation

0 10 20 30 40 5010

-3

10-2

10-1

100

s, m

in (

V)

L (nm)

Vds = 0.05V

Vds = 1V

Lmin

~ 3l0

s,min s,min(short ch.)

s,min(long channel)

exp(-L/l0) for low/high Vds.

Pre-exponential factor1.7V,

Lmin 3l0 so s,min < 0.1 V.

source

gate-controlled

barrier

drain

(For L 2l0, s,min below exp(-L/l0) because exp(-L/l1) term is negative.)

(l0 = 8.6 nm)

Page 29: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 29

Comparison of 9 scale length models

0 5 10 15 200

5

10

15

20

Points: 2-D simulation

Lines: models l0a

- l0i

tox

(nm)

Sca

le l

ength

(n

m)

a

f

b

i

d

gc

eh

0 10 20 30 40 50 60 70 800

5

10

15

20

25

EOT = 1nm

Circles: 2-D Simulation

Lines: Models l0a

- l0i

i

h

gf

e

d

c

b

a

Sca

le l

en

gth

(n

m)

Dielectric constant of gate insulator

l0a, l0b : Polynomial potential model.

l0c: BSIM3.

l0d, l0e, l0h: Zero field BC at bottom.

l0g = (2/)[Wdm + (si/i)ti] (one-region).

l0i : Two region scale length model.

For a fixed EOT (ox/i)ti,

only the two-region l0i model

depicts the correct

dependence on i (due to

lateral field in oxide.)

Wdm=10 nm

ti

Page 30: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

2013/9/4 30

Bulk, SOI and DG-MOSFET

S D

G

S D

G

BOX

S D

G

G

Bulk Fully-depleted

SOI Double-Gate

Bulk MOSFETs scale by decreasing depletion width with higher body doping. (High Vt, tunneling, poor sub-Vt slope, dopant fluctuation.)

FD-SOI and double-gate MOSFETs scale by silicon film thickness without doping.

Page 31: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

SCE in Thin Body (FD) SOI MOSFETs

Bulk MOSFET

Wdm=10nm

tox=1nm

SOI MOSFET

tsi=10nm

tox=1nm

SOI: Field penetration into BOX (200nm).

No analytic scale length.

Page 32: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

Scale length: Bulk vs. SOI

Bulk MOSFET

Wdm=10nm

tox=1nm

SOI MOSFET

tsi=10nm

tox=1nm

No analytic scale length.

Lmin 3.5l0i 28nm (50mV Vt)

, l0i = 8 nm

Lmin 58nm (50mV Vt)

02

tan12

tan1

00

i

dm

sii

i

i l

W

l

t

Page 33: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

Charge and potential in short-channel SOI

For Vbs=0, inversion charge is higher at back surface in a short device.

Large substrate reverse bias restore the channel to the front surface.

sisi t

kTq

i

tkTq

ii ddxd

endxenQ

0

/

0

/

/

In subthreshold

Page 34: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

Lmin hits a floor until very large reverse bias.

Lmin of SOI vs. reverse substrate bias

?

Xie et al.,

TED 2013.

Page 35: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

Very Large Substrate Reverse Bias:

Backside Accumulation

SOI becomes bulk-like

with Wdm = tsi.

Body effect > 60 mV/dec.

Backside accumulation starts at

si

BOXg

BOX

ox

si

si

gg

subt

t

q

Et

qt

E

q

EV

31

min

But, high field issues.

Page 36: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 36

Double-Gate MOSFETs: Three-region scale length model

Three-region scale length model:

1

111

)(2sin

2sinh

)(2sinh

),( n n

n

n

nLl

tx

l

L

l

yL

byxu

1

22

2sin

2sinh

)(2sinh

),( n n

n

n

nLl

x

l

L

l

yL

byxu

1

3233

)(2sin

2sinh

)(2sinh

),( n n

n

n

nLl

ttx

l

L

l

yL

byxu

l

t

l

t

l

t

l

t

l

t

l

t 3

3

2

2

1

1

321

31

2 2tan

12tan

12tan

12tan

2tan

2tan

Eliminate from the two boundary conditions:

Eigenvalue eq.

Bottom conductor: Either gate or substrate.

Page 37: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 37

Scale Length of Double-Gate MOSFETs

Let 1 = 3 = i, t1 = t3 = ti, and 2 = si, t2 = tsi :

l

t

l

t

l

t

l

t si

si

i

i

sii

i

si 2tan

12tan

22tan

2tan 2

2

012

cot2

tan22

tan2

2

i

si

l

t

l

t

l

t sii

i

sii

lt

lt

l

t

l

t

l

t

si

sisisii

i

si

/2sin

1/2cos1

2cot

2cot

2tan 2

si

isii

l

t

l

t

tan

2tan

si

isii

l

t

l

t

cot

2tanTwo solutions: and

The longest l comes from the first eq. The second eq. requires

one of the angles to exceed /2.

Page 38: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

9/4/2013 38

Scale Length of Double-Gate MOSFETs

For i = si, l = (2/tsi + 2ti), tsi +

2ti is the physical height between

the two gates.

DG MOSFET scales better than

bulk because tsi can be < Wdm with

no doping.

In any case, l (2/tsi and l

(4/ti regardless of i/si.

si

isii

l

t

l

t

tan

2tan

(2/)(tsi/l)

(2/)(ti/l)

Lmin 3l max(2tsi, 4ti)

Page 39: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

Nanowire MOSFETs

]/)(2[

]/)(2[1

)/2(

)/2(

)/2(

)/2(

0

0

0

0

0

0

ltRJ

ltRY

lRJ

lRY

lRJ

lRY

i

i

i

si

i

si

0)()(1

yy

2-D Poisson’s eq. in

cylindrical coordinates:

Scale length l:

Page 40: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

Nanowire MOSFETs

If si =i, l = 0.83(R +ti )

If i >>si (very high-),

Lmin=the larger of 2.5R , 3.5ti .

(tox=ti)

[DG: l = 0.64tsi +2ti)]

l (nanowire0.65l (DG)

if tsi 2R (why?)

Scaling limits?

(2/)(R/l)

(2/)(ti/l)

Page 41: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

So where is the limit?

Limited by quantum

confinement:

DG

E0=h2/(8mtsi2)

Nanowire

E0=a2h2/(8m2R2)

For same confinement,

tsi (/a)R 1.3R

How thin can silicon be?

a2.405 is the 1st zero of J0(x).]

Page 42: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

So where is the limit?

DG: l = 0.64tsi +2ti) tsi,min= 2.1 nm, Lmin 6.0 nm.

Nanowire: l = 0.83(R +ti )

Rmin=1.6 nm, Lmin 5.2 nm.

Assume si = i, ti = 0.5 nm,

InGaAs nanowire can only be scaled to Lmin ~ 10 nm because of

the stronger QM confinement from small electron effective mass.

Page 43: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

Conclusion

Many evolutions after the first introduction of

“scale length” in 1979, we now have a good

handle on analytically assessing short-channel

effect in MOSFETs.

The “scale length” concept has been generalized

to high- dielectrics, double-gate MOSFETs, and

nanowire MOSFETs.

Combining scale length with quantum mechanical

considerations allows the projection of scaling

limits.

Page 44: CMOS Device Scaling Past, Present, and Future · at the Si/oxide interface, the oxide region is replaced by an equivalent Si region ( si / ox)t ox 3t thick. In AFGH (oxide), In ABEF

List of References

1. L. D. Yau, "A simple theory to predict the threshold voltage of short- channel IGFET’s," Solid-State

Electronics, vol. 17 , pp. 1059-1063, Oct. 1974.

2. T. Toyabe and S. Asai, "Analytical models of threshold voltage and breakdown voltage of short-channel

MOSFET's derived from two-dimensional analysis," IEEE Trans. Electron Devices, vol.26, no.4, pp. 453-

461, Apr. 1979.

3. R. H. Yan, A. Ourmazd, and K. F. Lee, "Scaling the Si MOSFET: from bulk to SOI to bulk," IEEE Trans.

Electron Devices, vol.39, no.7, pp.1704-1710, Jul. 1992.

4. Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P. K. Ko, and Y.C. Cheng, "Threshold voltage model

for deep-submicrometer MOSFETs," IEEE Trans. Electron Devices, vol.40, no.1, pp.86-95, Jan. 1993.

5. K. Ratnakumar, and J. Meindl, "Short-channel MOST threshold voltage model," IEEE J. Solid-State

Circuits, vol.17, no.5, pp. 937-948, Oct. 1982.

6. D. R. Poole and D. L. Kwong, "Two-dimensional analytical modeling of threshold voltages of short-channel

MOSFET's," IEEE Electron Device Lett., vol.5, no.11, pp. 443-446, Nov. 1984.

7. T. N. Nguyen and J. D. Plummer, "Physical mechanisms responsible for short channel effects in MOS

devices," in IEDM Tech. Dig., 1981, pp. 596-599.

8. D. J. Frank, Y. Taur, and H.-S. P. Wong, "Generalized scale length for two-dimensional effects in

MOSFETs," IEEE Electron Device Lett., vol.19, no.10, pp.385-387, Oct. 1998.

9. Qian Xie, Chia-Jung Lee, Jun Xu, Clement Wann, Jack Y.-C. Sun, and Yuan Taur, “Comprehensive analysis

of short-channel effects in ultra-thin SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 60, no. 6, pp.

1814-1819, June 2013.

10. S.-H. Oh, D. Monroe, and J. M. Hergenrother, “Analytic description of short-channel effects in fully-

depleted double-gate and cylindrical, surrounding-gate MOSFETs,” IEEE Electron Device Lett. 9, 445-447,

Sept. 2000.

11. B. Yu, L. Wang, Y. Yuan, P. M. Asbeck, and Y. Taur, “Scaling of nanowire transistors,” IEEE Trans. Electron

Devices, vol. 55, pp. 2846-2858, Nov. 2008.

12. Qian Xie, Jun Xu, and Yuan Taur, “Review and Critique of Analytic Models of MOSFET Short-Channel

Effects in Subthreshold,” IEEE Transaction on Electron Devices, 2012.

13. Y. Taur and T. H. Ning, Fundamentals of modern VLSI devices, Cambridge, U.K.: Cambridge University

Press, 2009.