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CMOS Addersfor the
Simplified MIPS Processor
Specifications
• Needs to be fast: well under 1ns
• Needs to fit width of bitslice: 80λ
• Needs to be a reasonable length: <1500 λ
Bitslice layout ~2000λTotal core area 3500λ x 3500λ
Exploring the Options
• Static CMOS?– Easy to design and layout– Not very fast though
• Dynamic CMOS?– Not easy to design– Fast
P0
Ci,0
P1
G0
P2
G1
P3
G2
P4
G3 G4
VDD
Dynamic CMOS
Manchester Carry Chain
Static CMOS Options
• Ripple Carry Adder– Simple to design and layout– Small footprint– Slow: Cout must propagate through all bits
• Carry Lookahead Adder– More complex design and carry logic– Significantly larger footprint– Faster than ripple carry
Static CMOS Options cont.
• Carry Skip Adder– Faster than ripple carry adder– Slower than carry lookahead adder– Smaller footprint than carry lookahead adder– Larger footprint than ripple carry addder
Cin+
S4:1
P4:1
A4:1 B4:1
+
S8:5
P8:5
A8:5 B8:5
+
S12:9
P12:9
A12:9 B12:9
+
S16:13
P16:13
A16:13 B16:13
CoutC4
1
0
C81
0
C121
0
1
0
16-bit carry skip adder with 4-bit carry lookahead groups
Static CMOS Ripple Carry Adders
• Zhuang Full Adder– Fast: Transmission gates as MUXs– Low transistor count (22) leads to small layout– Already have it laid out, tested and spec’ed
Static CMOS Ripple Carry Adders
• Full Adder structure– Higher transistor count (28)– Larger transistors (8x for some pMOS!)– Carry out is no longer critical path
Static CMOS Ripple Carry Adders
• Delay with no parasitics modeled• Worst case determined to be
11111111 00000000+ 1 CinS 00000000Cout = 1
• B set to 11111111 Cin then set to 1• Time from when Cin at 50% until Cout a 50%
– 1.035ns(!!!)
Zhuang Full Adder
• Same test case as before
• Delay found to be .662ns
• Significanly faster than other static CMOS implementation
Zhuang Full Adder
• Simulated with parasitics added
• Same test pattern applied
• Delay now found to be .970ns
• Still faster than other adder without parasitics
• Use Zhuang full adder
Zhuang Full Adder Layout
• Had Zhuang layout from before
• Fit nicely in bitslice in IP library– 80λ width– Exports at correct places– Perfect!
Zhuang Full Adder layout completed
Zhuang Full Adder Simulation
• Exported layout to SPICE
• Same test case as used before
• Delay is now 1.23ns
Completed ALU ready to be placed in bitslice ~550 λ
Adders Wrap Up
• Total bitslice size ~2500λ
• Well under 3500λ
Distorted (squished horizontally, too long to display) view of completed bitslice.
Adder Wrap Up
• Not fast enough though– Dynamic CMOS?– Static carry lookahead use more space?