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Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Page 1: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

Clock Simulation

Jenn Transue, Tim Murphy, and Jacob Medinilla

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Page 2: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Overview

Project Overview Introduction

Background

Design Specifications

Preliminary Design

Simulation

Conclusion

Page 3: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

Project Overview

Tim Murphy

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Page 4: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Introduction

Clock simulation

Closed-loop position

Tracking a stepped input

Page 5: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Background

12° every 2 seconds

1 complete revolution every minute

Plant transfer function:

Page 6: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Design Specifications

Time domain specifications: Settling time: < 0.5 seconds

Percent overshoot: < 10%

Zero steady-state error

Variation of a PID controller

Page 7: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Preliminary Design

Jenn Transue

Page 8: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Preliminary Design

Response to a step input Uncompensated System

Proportional (P) Controller

Proportional Derivative (PD) Controller

Page 9: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Preliminary Design – Uncompensated

Uncompensated closed-loop system: 54.6% overshoot

1.01 second settling time

Zero steady-state error

Page 10: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Preliminary Design – P Controller

Root Locus Analysis: 10% Overshoot

KP = 0.102

Page 11: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Preliminary Design – P Controller

Compensated closed-loop system: Kp = 0.102

9.97% overshoot

0.94 second settling time

Zero steady-state error

Cannot meet settling time specification

Page 12: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Preliminary Design – PD Controller

From Specifications and Plant: Resulted in:

13.3% Overshoot

0.386 Second Settling Time

Need to adjust to achieve desired overshoot

Page 13: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Preliminary Design – PD Controller

Adjusted overshoot specification in calculations

Compensated closed-loop system: Kp = 0.3895

Kd = 0.0219

10% overshoot

0.427 second settling time

Zero steady-state error

Do not need an integral component

Page 14: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

Simulation

Jacob Medinilla

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Page 15: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Simulation – Pole-Zero Plot

Compensated closed-loop system

Stable

Relatively fast system

Page 16: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Simulation – Model

Compensated System Response to Stepped Input

Page 17: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Simulation – Results

Compensated System Response to Stepped Input

Page 18: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Conclusion – Expected Challenges

Design not validated Potential for unexpected behavior

Sensitivity to controller tuning

Possibility erroneous values from previous labs

Page 19: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Conclusion – Schematic

Page 20: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Summary

Uncompensated System cannot meet specifications

Proportional Controller cannot meet specifications

PD Controller required Kp = 0.3895

Kd = 0.0219

Will need to adjust gains to achieve specifications in lab

Page 21: Clock Simulation Jenn Transue, Tim Murphy, and Jacob Medinilla 1

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Questions?