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Classification of Digital Circuits
Combinational.Output depends only on current input values.
Sequential.Output depends on current input values and present state of the circuit, where the present state of the circuit is the current value of the devices’ memory.Also called finite state machines.
State of a CircuitThe contents of storage elements.A collection of know internal signal values that contain information about the past necessary to account the future behavior of the circuit.
ClockSignal that determines the change of state in most sequential circuits.
CLK
tper
tHtL
tLtHtper
state changes occur here(a)
state changes occur here
CLK_L
(b)
duty cycle = tH / tper
frequency = 1 / tper
period = tper
duty cycle = tL / tper
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Bi-stable ElementsThe simplest sequential circuit.It consist of a pair of inverters connected as shown below. Notice the feedback loop.
Vin1 Vout1
Vout2Vin2
Q
Q_L
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Digital AnalysisTwo stable states.If Q is HIGH then the lower inverter has a HIGH at its input and a LOW at its output. This in turn forces the upper inverter’s input to be LOW and its output to be HIGH.If Q is LOW then the lower inverter has a LOW at its input and a HIGH at its output. This in turn forces the upper inverter’s input to be HIGH and its output to be LOW.
Analog AnalysisConsidering the steady state behavior of the bistable element.
Vin1 = Vout2
Vin1 = T(Vin2)Vin1 = T(Vout1)Vin1 = T(T(Vin1))
Vout1
= Vout2Vin1
= V in2
stable
metastable
stable
Transfer function:
Vout1 = T(Vin1)
Vout2 = T(Vin2)
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Analog AnalysisMetastable behavior:
Consider the middle intersecting point in the diagram shown below.What would happen if a small amount of noise varies either input voltage.
Vout1
= Vout2Vin1
= V in2
stable
metastable
stable
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Analog AnalysisThe drawing on this slide shows a very good analogy to the stable and metastable behavior of a bi-stable element.
stable stable
metastable
Latches and Flip-FlopsBinary cells capable of storing 1 bit of information.Generates one of two possible stable states.Two outputs labeled Q and Q’.One or more inputs.
Latches and Flip-FlopsThese sequential devices differ in the way their outputs are changed:
The output of a latch changes independent of a clocking signal.The output of a flip–flop changes at specific times determined by a clocking signal.
S-R LatchR
S
Q0 0
0 1
1 0
1 1
S R
0
0
1
last Q
Q
1
0
0
(a) (b)
QN
last QN
QN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
SR latch based on NOR gates.The S input sets the Q output to 1 while R reset it to 0.
S-R LatchR
S
Q0 0
0 1
1 0
1 1
S R
0
0
1
last Q
Q
1
0
0
(a) (b)
QN
last QN
QN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
When R=S=0 then the output keeps the previous value.When R=S=1 then Q=Q’=0, and the latch may go to an unpredictable next state.
S-R Latch
Double negation is not a good idea. It is confusing and it creates problems.
Q
QNR
(b) (c)(a)
S Q
QNR
S SQ
QR
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
S-R LatchS
R
Q
tpHL(RQ)tpLH(SQ)
(2)
(1)
tpw(min)
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
S
R
Q
(a) (b)
QN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
S’-R’ Latch
S_L
R_L
Q0 0
0 1
1 01 1 last Q
1
0
1
Q
0
1
1
(a) (b) (c)
S Q
QR
last QN
QNor S
or R
QN
S_L R_L
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
S’R’ latch based on NAND gates.The S’ input sets the Q output to 1 while R’ reset it to 0.
S’-R’ Latch
When R’=S’=1 then the output keeps the previous value.When R’=S’=0 then Q=Q’=1, and the latch may go to an unpredictable next state.
S_L
R_L
Q0 0
0 1
1 01 1 last Q
1
0
1
Q
0
1
1
(a) (b) (c)
S Q
QR
last QN
QNor S
or R
QN
S_L R_L
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
S-R Latch With EnableThe outputs change only when the enable input C is asserted.
1 1
0 1
1 0
S
1
1
1
CR
0
1
1
Q
0 0 1 last Q
xx 0 last Q
1
0
1
(b) (c)(a)
Q
S
C
R
S Q
QR
C
QN
last QN
last QNQN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
S-R Latch With EnableS
R
C
Q
Ignored since C is 0. Ignored until C is 1.
QN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Notice that the outputs only change when the input C is asserted.
D LatchThis latch eliminates the problem that occurs in the S’R’ latch when R=S=0.C is an enable input:
When C=1 then the output follows the input D and the latch is said to be open. Due to this fact this latch is also called transparent latch.When C=0 then the output retains its last value and the latch is said to be closed.
(b) (c)(a)
Q
D
C 0
1
D
1
1
C
0
1
Q
x0 last Q
1
0
D Q
QC
QN
QN
last QN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
D Latch
(b) (c)(a)
Q
D
C 0
1
D
1
1
C
0
1
Q
x0 last Q
1
0
D Q
QC
QN
QN
last QN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
D
C
Q
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
D Latch
For proper operation the D input must not change during a time interval around the falling edge of C.This time interval is defined by the setup time – tsetup and the hold time –thold .
D
C
Q
tholdtsetuptpLH(DQ)tpLH(DQ)
tpHL(DQ)tpLH(CQ)
tpHL(CQ)
(1) (2) (3) (5)(4)
Edge Triggered D Flip-FlopThis flip-flop is made out of two D latches. The first latch is the master, and the second the slave.When CLK_L = 1 the master is open (on) and the slave is closed (off). Qmand Ds follow Dm .
(b) (c)(a)
QD
CLK_L
CLK_L
0
1
D
0
1
Q
0x last Q
1
0
1x last Q
D Q
C
D Q
QC
D Q
QCLK
QN
QN
last QN
last QN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Edge Triggered D Flip-FlopWhen CLK_L = 0 the master is closed, the slave is open and Qm is transferred to Qs . Note that Qs does not change if Dm changes because the master latch is closed leaving Qmfixed.
(b) (c)(a)
QD
CLK_L
CLK_L
0
1
D
0
1
Q
0x last Q
1
0
1x last Q
D Q
C
D Q
QC
D Q
QCLK
QN
QN
last QN
last QN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Edge Triggered D Flip-Flop
Positive edge-triggered D flip-flop.Q* = D
(b) (c)(a)
QD
CLK
CLK
0
1
D
0
1
Q
0x last Q
1
0
1x last Q
D Q
C
D Q
QCD Q
QCLK
QM
QN
QN
last QN
last QN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
D
CLK
QM
Q
QN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Edge Triggered D Flip-Flop
If the set-up and hold times are not met the flip-flop’s output will go to a stable, though unpredictable, state.
D
CLK
Q
tholdtsetuptpHL(CQ)tpLH(CQ)
Edge Triggered D Flip-Flop
Asynchronous inputs are used to force the output of the flip-flop to a particular state.PR (preset) – Q = 1.CLR (clear) – Q = 0.
(a)
DPR
CLR
Q
QCLK
D
PR_L
CLK
CLR_L
Q
(b)
QN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Edge Triggered D Flip-Flop
D
CLK
PR_L
CLR_L Q
QN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
(a)
DPR
CLR
Q
QCLK
D
PR_L
CLK
CLR_L
Q
(b)
QN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Edge Triggered D Flip-FlopEdge triggered D flip-flop with enable.
(b) (c)(a)
Q
D
CLK
CLK
0
1
D
0
1
Q
0x last Q
1
0
1x last Q
D Q
Q
D Q
QCLKQN
QN
last QN
last QN
EN 1
1
EN
x
x
x 0 last Q last QN
EN
CLK
Scan Flip-FlopThis flip-flop allows its inputs to be driven from alternate sources, which can be very useful during device testing.
(b) (c)(a)
Q
D
CLK
CLK
x
x
TI
0
1
Q
0x last Q
1
0
1x last Q
D Q
Q
DQ
Q
QN
QN
last QN
last QN
TE 0
1
D
x
x
TE
TI
0
0
TE
x
x
CLK
TI0
1
0
1
1
0
x
x
1
1
CLK
DQ
Q
TE
CLK
TI
DQ
Q
TE
CLK
TI
DQ
Q
TE
CLK
TI
DQ
Q
TE
CLK
TI
CLK
TE
TI TO
ASICexternal
pins
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Master/Slave S-R Flip-FlopThe postponed output indicator shows that the output signal does not change until the enable C input is negated.Flip-flops with this kind of behavior are called pulse-triggered flip-flops.Q* = S+R’QSR = 0
(b) (c)(a)
Q
QN
S
C
C
0
R Q
last Q last QN
QN
0
S
x 0 last Q last QNx
1 0 10
0 1 01
1 undef. undef.1
R
S Q
QR
C
S Q
QR
C
S Q
QR
C
QM
QM_L
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Master/Slave S-R Flip-Flop
R
S
C
QM
QM_L
Q
QN
Ignored since C is 0. Ignored until C is 1. Ignored until C is 1.
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Master/Slave J-K Flip-FlopThe J and the K inputs of the J-K flip-flop are analogous to the S and R inputs of the S-R flip-flop, except in the case where J=K=1. In this case the outputs of the J-K flip-flop will toggle to the opposite state.
(b) (c)(a)
Q
QN
J
C
C
0
K Q
last Q last QN
QN
0
J
x 0 last Q last QNx
1 0 10
0 1 01
1 last QN last Q1
K
S Q
QR
C
S Q
QR
C
J Q
QK
CQM
QM_L
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Master/Slave J-K Flip-FlopQ* = JQ’+K’Q
K
J
C
QM
QM_L
Q
QN
Ignoredsince QN is 0.
Ignoredsince C is 0.
Ignoredsince QN is 0.
Ignoredsince Q is 0.
Ignoredsince C is now 0.
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
(b) (c)(a)
Q
QN
J
C
C
0
K Q
last Q last QN
QN
0
J
x 0 last Q last QNx
1 0 10
0 1 01
1 last QN last Q1
K
S Q
QR
C
S Q
QR
C
J Q
QK
CQM
QM_L
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Edge Triggered J-K Flip-FlopQ* = JQ’+K’Q
(b)(a) (c)CLK
0
K Q
last Q last QN
QN
0
J
x 1 last Q last QNx
x 0 last Q last QNx
1 0 10
0 1 01
1 last QN last Q1
Q
QN
J
CLK
KD Q
QCLK
J Q
QK
CLK
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
K
J
CLK
Q
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Edge Triggered J-K Flip-Flop74LS109
J
CLK
PR_L
CLR_L Q
QN
K_L
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
T Flip-FlopFlip-flop changes state every tick of the clock.Q* = Q’
Q
QT
(a) (b)
T
Q
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Q
Q QN
QT
J
K
CLKQN
Q
(a)
D Q
QCLKT
(b)
1
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
T Flip-Flop With EnableFlip-flop changes state every tick of the clock when enable is asserted.Q* = ENQ’+EN’Q
Q
QT
EN
(a) (b)
T
EN
Q
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Q
Q QN
QT
J
K
CLKQN
Q
(a)
D Q
QCLKT
EN
(b)
EN
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Clocked SynchronousState-Machine Analysis
State machine – Another term for a sequential circuit.Clocked – Refers to the fact that their flip-flops employ a clock input.Synchronous – Same clock signal is used by all flip-flops.A state machine with n flip-flops can have up to 2n distinct states.
State Machine StructureState memory – a set of n flip-flops.Next-state logic – combinational logic circuit which determines the next state.
Next-state = F(current state,input)Output logic – combinational logic circuit which determines the output.There are two models for the output logic:
Mealy Model.Moore Model.
Mealy ModelThe output is based on both current state and input.
Output = G(current state,input)
StateMemory
clock input
Next-stateLogic
F
OutputLogic
G
excitation current stateinputs
clocksignal
outputs
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Moore ModelThe output is based on current state only.
Output = G(current state)
In high speed circuits the output circuit may be absent and the output is generated directly from the flip-flop’s outputs. This is called output coded state assignment.
StateMemory
clock input
Next-stateLogic
F
OutputLogic
G
excitation current stateinputs
clocksignal
outputs
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
Mealy ModelPipelined outputs – a design approach that ensures the output of a Mealy model circuit only changes with the clock.
StateMemory
clock input
Next-stateLogic
F
OutputLogic
G
excitation current stateinputs
clocksignal
pipelinedoutputs
OutputPipelineMemory
clock input
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
AnalysisDetermine the next-state and output functions F and G.Use F and G to construct a state/output table that completely specifies the next state and output of the circuit for every possible combination of current state and input.Draw a state diagram.
State Machines With D Flip-FlopsD0 = Q0 · EN’ + Q0’ · END1 = Q1 · EN’ + Q1’ · Q0 · EN + Q1 · Q0’ · EN
EN
CLK
D0 Q0
D1 Q1
MAX
D Q
QCLK
D Q
QCLK
current state
excitation
output
input
clock signal
Next-state Logic F State Memory Output Logic G
EN′
EN
Q0′
Q0
Q1′
Q1
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
State Machines With D Flip-FlopsQ0* = D0Q1* = D1
Q0* = Q0 · EN’ + Q0’ · ENQ1* = Q1 · EN’ + Q1’ · Q0 · EN + Q1 · Q0’ · EN
EN
CLK
D0 Q0
D1 Q1
MAX
D Q
QCLK
D Q
QCLK
current state
excitation
output
input
clock signal
Next-state Logic F State Memory Output Logic G
EN′
EN
Q0′
Q0
Q1′
Q1
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
State Machines With D Flip-FlopsMAX = Q1 · Q0 · EN
EN
CLK
D0 Q0
D1 Q1
MAX
D Q
QCLK
D Q
QCLK
current state
excitation
output
input
clock signal
Next-state Logic F State Memory Output Logic G
EN′
EN
Q0′
Q0
Q1′
Q1
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
State Machines With D Flip-FlopsQ0* = Q0 · EN’ + Q0’ · ENQ1* = Q1 · EN’ + Q1’ · Q0 · EN + Q1 · Q0’ ·ENMAX = Q1 · Q0 · EN
Present State Input Next State OutputS EN S* MAXA 0 A 0A 1 B 0B 0 B 0B 1 C 0C 0 C 0C 1 D 0D 0 D 0D 1 A 1
Input OutputQ1 Q0 EN Q1* Q0* MAX0 0 0 0 0 00 0 1 0 1 00 1 0 0 1 00 1 1 1 0 01 0 0 1 0 01 0 1 1 1 01 1 0 1 1 01 1 1 0 0 1
Present State Next State
State Machines With D Flip-Flops
(a) EN (b) EN (c) EN Table 7-2Transition, state, and state/output tables for the state machine in Figure 7-38.
Q1 Q0 0 1 S 0 1 S 0 1
00 00 01 A A B A A, 0 B, 0
01 01 10 B B C B B, 0 C, 0
10 10 11 C C D C C, 0 D, 0
11 11 00 D D A D D, 0 A, 1
Q1∗ Q0∗ S∗ S∗, MAX
State Machines With D Flip-Flops
(a) EN (b) EN (c) EN Table 7-2Transition, state, and state/output tables for the state machine in Figure 7-38.
Q1 Q0 0 1 S 0 1 S 0 1
00 00 01 A A B A A, 0 B, 0
01 01 10 B B C B B, 0 C, 0
10 10 11 C C D C C, 0 D, 0
11 11 00 D D A D D, 0 A, 1
Q1∗ Q0∗ S∗ S∗, MAX
A B
D C
EN = 1
(MAX = 0)
EN = 1
(MAX = 0)
EN = 1
(MAX = 0)
EN = 0
(MAX = 0)
EN = 0
(MAX = 0)
EN = 0
(MAX = 0)
EN = 0
(MAX = 0)
EN = 1
(MAX = 1)
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
State Machines With D Flip-Flops
A B
D C
EN = 1
(MAX = 0)
EN = 1
(MAX = 0)
EN = 1
(MAX = 0)
EN = 0
(MAX = 0)
EN = 0
(MAX = 0)
EN = 0
(MAX = 0)
EN = 0
(MAX = 0)
EN = 1
(MAX = 1)
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
CLOCK
EN
Q1
Q0
MAX
STATE D A AC D DA A B C C
MAXS
Copyright © 2000 by Prentice Hall, Inc.Digital Design Principles and Practices, 3/e
State Machines With J-K Flip-Flops
Clocked Synchronous State Machine Design
Derive a state/output table from the problem specification.Minimize the number of states in the state/output table by eliminating equivalent states.Choose a set of state variables. Assign to each state a unique combination from the set derived above.Create a transition/output table.Choose a flip-flop type and derive its excitation table.Using the excitation table fill the values for the input excitation function columns on the transition/output table.Derive the excitation and output equations.Draw logic diagram.
Clocked Synchronous State Machine Design
Design a sequential circuit with one input ( I ) and one output ( Z )The output is asserted when the input sequence 0-1-1 is received.See state/output table below.
Input OutputI Z0 S 0 01 Init 00 S 0 01 S 01 00 S 0 01 S 011 00 S 011 11 S 011 1
S 01
S 011
Present State Next stateInit
S 0
Clocked Synchronous State Machine Design
Set of state variables and their unique assignment to the different states.
State Q1 Q0Init 0 0S 0 0 1S 01 1 1S 011 1 0
Clocked Synchronous State Machine Design
Transition/output table
Input OutputQ 1 Q 0 I Q 1 * Q 0 * Z
0 0 0 0 1 00 0 1 0 0 00 1 0 0 1 00 1 1 1 1 01 0 0 1 0 11 0 1 1 0 11 1 0 0 1 01 1 1 1 0 0
Present State Next state
Clocked Synchronous State Machine Design
Excitation table.
D J K T0 0 0 0 X 00 1 1 1 X 11 0 0 X 1 11 1 1 X 0 0
Present State Next StateRequired inputs
Clocked Synchronous State Machine Design
Equations derived from the table above:J1 = IQ0
K1 = I’Q0
J0 = I’Q1‘K0 = IQ1
Z = Q1Q0’
Input OutputQ 1 Q 0 I Q 1 * Q 0 * Z J 1 K 1 J 0 K 0
0 0 0 0 1 0 0 X 1 X0 0 1 0 0 0 0 X 0 X0 1 0 0 1 0 0 X X 00 1 1 1 1 0 1 X X 01 0 0 1 0 1 X 0 0 X1 0 1 1 0 1 X 0 0 X1 1 0 0 1 0 X 1 X 01 1 1 1 0 0 X 0 X 1
Present State Next state Input Excitation
Clocked Synchronous State Machine Design
Logic diagram.J1 = IQ0
K1 = I’Q0
J0 = I’Q1‘K0 = IQ1
Z = Q1Q0’