Class02 Signal Parameters I

8/7/2019 Class02 Signal Parameters I

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Signal and Timing Parameters ICommon Clock – Class 2

Prerequisite Reading assignment: CH8 to 9.3

Acknowledgements: Intel Bus Boot Camp:Howard Heck



Signal Parameters & Timing Class 2

2

Agenda Voltage and Time

Budgets

Computer Signaling Elements and Circuits

Flight time

Synchronous Bus Operation Clock Skew and Jitter

Setup and Hold

Manufacturing Considerations Advanced Topics




3

Voltage and time

SI boils down to meeting voltage and time

specifications True for most I/O computer interfaces Violating a time or voltage specification i.e.

exceeding a limit, may cause a circuit to fail

Notice the use of the word “may” rather than “will”Most limits are at least 3 sigma limits.

The actual sigma limits are usually a company secret.

Margin is the difference between a specification andthe respective measured signal parameter. Margin isconsidered a quality factor for a design.




4

SI Budgets

An SI budget is a technique used to report

timing and voltage margin in terms of voltageand timing components (“buckets”) for allconfigurations and conditions of a particularbus design.

The budget is often represented in a spreadsheet.

Margin Voltage Spec Noise Bucket Measured Voltage Measurement Error

14 100 10 56 20 (mv)

=B2-(C2+D2+E2) … Cell formula




5

What Failing SI Means: Negative margin

- limit +limitMean

Probability thata parameter

is a certainvalue

Measuredparametervalue

• The integral of the probability function outside theselimits is the failing population

• Pf X volume X cost/unit = variable cost of failure

• Not the whole story – A bad name can cost billions infixed costs (good will)




6

Simple I/O Architecture

Pre- ’00 the most common computer I/Ointerface was synchronous memory transfer

Intel Xeon 100 MHz bus was just about the lastin this class

Clock distribution is a challenge – more onthis later

CPUs RAM Memory& I/O control

clock




7

Synchronous Memory Elements - Operation

Operation A data signal (in ) that is present at the input to

the flip-flop is “latched” into the flip-flop bythe rising edge of the input clock signal (clk ).

On the next rising edge of clk , the data signalis released to the output of the flip-flop (out ).

This means data is clocked out of device a onone clock edge and received at device b on thenext clock edge.

This is also called common clocking.

Memory MemoryInter-

connect

Clock

Device a Device b

out in

clk

Edge T

riggered

Flip

Flop

input data output data

clock




8

Synchronous Memory Elements - Timing

Timing Valid data must be present for a minimum amount of time

prior to the input clock edge to guarantee successful captureof the data. This is known as setup time, T

setup.

Data must remain valid for a minimum amount of time after

the input clock edge to guarantee that the proper value iscaptured. This is called hold time, T hold

.

T setup

T hold

clk

in




9

Simple Flight Time Concept

The time it takes a signal to travel from device a to device b or

the delay between transmitted (a) and received (b) signals.This is not the definition that SI engineers use in a timing budgetThere are issues with timing budgets and device timing parametersthat make this a poor definition.We will develop the exact definition of flight time for SI later

SI engineers use the term propagation delay but it is not the

same as AC propagation delay. We will develop the exactdefinition later; for now let’s consider all delays the same. AC is frequency domain analysis.

Device a Connection Trace Device b




10

Synchronous Bus Operation

We wish to use the clock to control the transmission of data from the latch inthe source (a) to the latch in the destination (b).

The initial clock pulse causes the source latch to release the data onto theinterconnect.

The next clock pulse causes the destination latch to capture the data that wastransmitted on the interconnect

We have 1 full clock cycle to get the data from the source to destination.

clk

D QCLK

D QCLK

a bFROM

CORE

TO

CORE

Explainpicture?




11

Transmit Clock Sequence

1. Initial (driving) clock pulse transmission from clock

generator to source.a) T

drv_clk = delay of the clock buffer circuit connected to the

source from node 1 to node 1a.

b) T prop_clk

= delay of the interconnect between clk & a.

clk

D QCLK

D QCLK

a bFROM

CORE

TO

CORE

T drv_clk (1a)

T prop_clk

(1b)

(1)




12

Data Path Sequence

2. Data transmission from source to destination.a) T

drv= delay of the output buffer circuit for the data signal.

b) T prop

= interconnect delay between source and destination.

c) T setup

= delay of the input buffer plus the flip-flop setup

requirement.

clk

D QCLK

D QCLK

a bFROM

CORE

TO

CORE

T drv_clk

(1a)

T prop_clk

(1b)

T drv (2a)

T prop

(2b)

T setup (2c)

(1)




13

Receive Clock Sequence

3. Second (receiving) clock pulse transmission from clock generator to

destination.

a) T drv_clk

(b) = delay of the clock buffer circuit connected to b.

b) T prop_clk

(b) = delay of the interconnect between clk & b.

c) Ideal assumption: T drv_clk

= T drv_clk

(b) & T prop_clk

= T prop_clk

(b)

clk

D QCLK

D QCLK

a bFROM

CORE

TO

CORE

T drv_clk

(1a)

T prop_clk

(1b)

T drv (2a)

T prop

(2b)

T setup (2c)

T drv_clk (b)

(3a)

T prop_clk (b)

(3b)

(1)




14

Clock Skew

What happens if the clock signals at the source and destination arenot in phase?

What if the clock arrives at the destination before it reaches the source?Vice-versa?

What are the sources of uncertainty in the phase relationship betweendifferent clock signals?

Clock Skew: pin-to-pin variation in the timing of input clock at eachagent (source & destination, in our example) on a bus.

The net effect of clock skew is that it canreduce the total delay that signals are allowed to have for a givenfrequency target.require larger minimum signal delays in order to avoid logic errors. (We’llcover this in more detail shortly.)

Transmitclock at

device a

Receiveclock atdevice b




15

Sources of Clock SkewClock skew is caused by:

variation between the clock driver circuits in a given part (T drv).

variation in the loading between different agents on the bus(C

L).

variation in interconnect characteristics (Z 0, τ

d ).

variation in electrical lengths. What is electrical length?

Z Z 00 ,, ττ d d

Z Z 00 ,, ττ d d

C C LL

C C LLT T

drvdrv

T T drvdrv

Cloc

kD

river

Cloc

kD

river

bb

aa




16

Clock Jitter

Cycle to cycle variation of clock Changes the time available for data to get from

transmitter to receiver Jitter + Skew = Clock uncertainty for setup Skew = Clock uncertainty for hold

Hold uses same cycle of clockIn many cases we can ignore certain types of jitter

There are other types of jitter – more advancedtopic

Ideaclock

Bar graph

of eachcycle time

Clock withCycle toCycleJitter

Pulse Width

(Ideal)

Pulse Width

(Actual)




17

Skew & Jitter Example

100 MHz bus

Minimum clock period = 10 ns Given:

Maximum skew = 250 ps

Maximum edge-edge jitter = 250 ps.

Calculate the minimum effective clock period:

minimum effective period =minimum period – maximum skew – maximum jitter

min effective period = 10.0 ns – 0.25 ns – 0.25 ns = 9.5 ns

Therefore, maximum allowed for silicon plusinterconnect delay is 9.5 ns.




18Setup Timing Diagram & Loop Analysis

CLOCK

@ clk input

T prop_clk

T drv_clk

T cycle

CLOCK(b)

@ clk output

CLOCK(b) @ b

CLOCK(a) @ a

CLOCK(a)

@ clk output

DATA @ b

DATA @ a

T drv

T prop

T margin

T jitter

T prop_clk (b)

T drv_clk (b)

T setup

( ) ( ) 0 _ _ arg_ _ =−−−−−−−++ clk drvclk propdrvpropinmsetupjitter clk propclk drvcycle T T T T T T T bT bT T




19

Hold Timing Equation

T T T clk drv clk prop clk ≡ +_ _

( ) clk clk setupskew T bT T −≡_

( ) ( ) 0_ _ _ arg_ _ =−−−−+++ bT bT T T T T T T clk drvclk prophold hold inmpropdrvclk propclk drv

hold skewhold propdrvhold inm T T T T T _ _ arg −−+=




20

Manufacturability Considerations Sources of variability in silicon:

manufacturing process (e.g. silicon gate length)operating temperature (MOS speed ⇓ as temp ⇑)operating voltage (MOS speed ⇑ as voltage ⇑)

Impact: variability leads to a range of values fordriver and receiver timings

Example: Pentium® Pro GTL+ timingsMinimum driver valid delay = 0.55 nsMaximum driver valid delay = 4.40 nsMaximum receiver setup time = 2.20 nsMaximum receiver hold time = 0.45 ns

Sources of interconnect variability:Manufacturing variation (Z 0, ε

r )

Trace length variation (among 144 signals for FSB, forexample)




21

Revised Timing Equations

Product specifications must comprehend the expected variation.

We need to modify the setup & hold equations:

The setup equation defines the minimum clock cycle time (maxfrequency) in terms of the maximum system delay terms. We wantT

margin_setup ≥ 0.

Excessive system delays can be handled by increasing cycle time, atthe cost of reduced performance.

The hold equation defines minimum system delay requirements toavoid logic errors due to hold violations. We want T margin_hold

≥ 0.

Minimum delay violations cannot be fixed by increasing cycle time.Why?

Setup jitter setupskewpropsetupdrvcyclesetupinm T T T T T T T −−−−−= _ max,max,min,_ arg

Hold T T T T T m in hold drv prop hold skew hold arg _ ,min ,min _ = + − −




22

Device Specs and Test Loads

Device specifications vs. system conditions

The manufacturer guarantees that the parts meet thevalues in the timing specifications when driving into the“spec load”.

This is really the only way devices can be tested.

The spec load is typically equal to the load presented tothe device by the device level test environment.This spec load is generally not the same as the loadpresented to the device by the system interconnect.

65Ω10pF

Spec Load System




23

Impact of Spec Loads

Since the spec load is NOT equal to theload on the device when placed in asystem:

An output buffer will have a different

delay in the system than in the testenvironment.

To deal with this:

define new timing termschange the way we break the timings intoseparate components.




24

Flight Time

Time

Voltage

Threshold

Clock Input to

Transmitting

Chip

Driver Pin into

Test Load

Driver Pin into

System Load

Receiver Pin

T drv T prop

T co T flight




25

Define T co

(time from clock-in to data-out) as the delay from the

input clock to the output data when driving into the test load . Define T

flight (flight time) as the delay to the receiver minus the

T co.

By defining the timings in this way, the flight time accountsfor the propagation delay of the interconnect PLUS the

difference between the driver delays when driving test loadvs. the system load.

Notice:

We defined T co and T flight this way to guarantee the overall

system timings remain the same.

Flight Time Explained

flight copropdrv T T T T +=+




26

Revised Timing Equations

The system designer relies on the synchronous

timing equations help define the working flight timewindow (min-to-max) with the given componenttiming specs.

Ultimately, the equations provide a tool for a design

team.Use them to evaluate design trade-offs in order to achievesystem performance (frequency) targets.

Setup jitter setupskewflight setupcocyclesetupinm T T T T T T T −−−−−= _ max,max,min,_ arg

Hold hold skewhold flight cohold inm T T T T T _ min,min,_ arg −−+=




27

Example: Bus Timing Spread Sheet – Setup times

Tco Max(ns) (

CPU 1 3.2CPU 2 3.2

Chip Set 7CPU 3 3.2




28

Synchronous Timing Summary Synchronous memory elements require a stable data signal for

a minimum amount of time prior to (SETUP) & after (HOLD)the input clock.

Hold and setup conditions determine the minimum and maximumsystem delays.

Setup and hold conditions can be analyzed by constructing

timing loops in the timing diagrams. Component delays exhibit variation across process and

environmental conditions. Interconnect delays vary due todesign and process.

Redefining driver and interconnect delays in terms of system

and “spec” loads allows manufacturers to specify and testcomponent delays.

System timing equations provide a key tool for examiningtrade-offs during system design.




29

Assignment

Create Budget Spreadsheet for setup andhold

Find and justify maximum frequency ofoperation

Find all minimum lengths

CPU1

CPU2 CPU3

CPU4

Chipset

L1=5”

L2=2”

L3=2”L4=3”

Tc

(n

CPU 1CPU 2

Chi S t

Documents

Class02 Signal Parameters I